--- _id: '10727' author: - first_name: Daniel full_name: Pudelko, Daniel last_name: Pudelko citation: ama: Pudelko D. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University; 2013. apa: Pudelko, D. (2013). Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs. Paderborn University. bibtex: '@book{Pudelko_2013, title={Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs}, publisher={Paderborn University}, author={Pudelko, Daniel}, year={2013} }' chicago: Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University, 2013. ieee: D. Pudelko, Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs. Paderborn University, 2013. mla: Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University, 2013. short: D. Pudelko, Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs, Paderborn University, 2013. date_created: 2019-07-10T11:54:45Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner title: Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs type: bachelorsthesis user_id: '3118' year: '2013' ... --- _id: '10730' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler citation: ama: Riebler H. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University; 2013. apa: Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Paderborn University. bibtex: '@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Paderborn University}, author={Riebler, Heinrich}, year={2013} }' chicago: Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University, 2013. ieee: H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Paderborn University, 2013. mla: Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University, 2013. short: H. Riebler, Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs, Paderborn University, 2013. date_created: 2019-07-10T11:54:49Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs type: mastersthesis user_id: '3118' year: '2013' ... --- _id: '10741' author: - first_name: Alexander full_name: Sprenger, Alexander last_name: Sprenger citation: ama: 'Sprenger A. MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University; 2013.' apa: 'Sprenger, A. (2013). MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung. Paderborn University.' bibtex: '@book{Sprenger_2013, title={MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung}, publisher={Paderborn University}, author={Sprenger, Alexander}, year={2013} }' chicago: 'Sprenger, Alexander. MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University, 2013.' ieee: 'A. Sprenger, MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung. Paderborn University, 2013.' mla: 'Sprenger, Alexander. MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University, 2013.' short: 'A. Sprenger, MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung, Paderborn University, 2013.' date_created: 2019-07-10T11:59:40Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner title: 'MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung' type: bachelorsthesis user_id: '3118' year: '2013' ... --- _id: '10743' author: - first_name: Philipp full_name: Steppeler, Philipp last_name: Steppeler citation: ama: Steppeler P. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University; 2013. apa: Steppeler, P. (2013). Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen. Paderborn University. bibtex: '@book{Steppeler_2013, title={Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen}, publisher={Paderborn University}, author={Steppeler, Philipp}, year={2013} }' chicago: Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University, 2013. ieee: P. Steppeler, Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen. Paderborn University, 2013. mla: Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University, 2013. short: P. Steppeler, Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen, Paderborn University, 2013. date_created: 2019-07-10T12:00:44Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen type: bachelorsthesis user_id: '3118' year: '2013' ... --- _id: '10745' author: - first_name: Christian full_name: Toebermann, Christian last_name: Toebermann - first_name: Daniel full_name: Geibel, Daniel last_name: Geibel - first_name: Manuel full_name: Hau, Manuel last_name: Hau - first_name: Ron full_name: Brandl, Ron last_name: Brandl - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Chenjie full_name: Ma, Chenjie last_name: Ma - first_name: Martin full_name: Braun, Martin last_name: Braun - first_name: Tobias full_name: Degner, Tobias last_name: Degner citation: ama: 'Toebermann C, Geibel D, Hau M, et al. Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation. In: Real-Time Conference. OPAL RT Paris; 2013.' apa: Toebermann, C., Geibel, D., Hau, M., Brandl, R., Kaufmann, P., Ma, C., … Degner, T. (2013). Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation. In Real-Time Conference. OPAL RT Paris. bibtex: '@inproceedings{Toebermann_Geibel_Hau_Brandl_Kaufmann_Ma_Braun_Degner_2013, title={Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation}, booktitle={Real-Time Conference}, publisher={OPAL RT Paris}, author={Toebermann, Christian and Geibel, Daniel and Hau, Manuel and Brandl, Ron and Kaufmann, Paul and Ma, Chenjie and Braun, Martin and Degner, Tobias}, year={2013} }' chicago: Toebermann, Christian, Daniel Geibel, Manuel Hau, Ron Brandl, Paul Kaufmann, Chenjie Ma, Martin Braun, and Tobias Degner. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” In Real-Time Conference. OPAL RT Paris, 2013. ieee: C. Toebermann et al., “Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation,” in Real-Time Conference, 2013. mla: Toebermann, Christian, et al. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” Real-Time Conference, OPAL RT Paris, 2013. short: 'C. Toebermann, D. Geibel, M. Hau, R. Brandl, P. Kaufmann, C. Ma, M. Braun, T. Degner, in: Real-Time Conference, OPAL RT Paris, 2013.' date_created: 2019-07-10T12:01:51Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' publication: Real-Time Conference publisher: OPAL RT Paris status: public title: Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation type: conference user_id: '3118' year: '2013' ... --- _id: '10774' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Majid full_name: Yazdani, Majid last_name: Yazdani - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587' apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli, G. (2013). A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (pp. 83–88). IEEE. https://doi.org/10.1109/DFT.2013.6653587 bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2013, title={A fast TCAD-based methodology for Variation analysis of emerging nano-devices}, DOI={10.1109/DFT.2013.6653587}, booktitle={2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, year={2013}, pages={83–88} }' chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani, and Giovanni De Micheli. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.” In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 83–88. IEEE, 2013. https://doi.org/10.1109/DFT.2013.6653587. ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “A fast TCAD-based methodology for Variation analysis of emerging nano-devices,” in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013, pp. 83–88. mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.” 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83–88, doi:10.1109/DFT.2013.6653587. short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83–88.' date_created: 2019-07-10T12:10:17Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/DFT.2013.6653587 extern: '1' language: - iso: eng page: 83-88 publication: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) publisher: IEEE status: public title: A fast TCAD-based methodology for Variation analysis of emerging nano-devices type: conference user_id: '3118' year: '2013' ... --- _id: '10775' author: - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: 'Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673' apa: 'Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013). Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6). IEEE. https://doi.org/10.1109/LATW.2013.6562673' bibtex: '@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}, DOI={10.1109/LATW.2013.6562673}, booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013}, pages={1–6} }' chicago: 'Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW, 1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.' ieee: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.' mla: 'Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.' short: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.' date_created: 2019-07-10T12:10:18Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/LATW.2013.6562673 extern: '1' language: - iso: eng page: 1-6 publication: 2013 14th Latin American Test Workshop-LATW publisher: IEEE status: public title: 'Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study' type: conference user_id: '3118' year: '2013' ... --- _id: '13645' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Lars full_name: Schäfers, Lars last_name: Schäfers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proceedings of the International Conference on Computers and Games (CG). Springer; 2013.' apa: Graf, T., Schäfers, L., & Platzner, M. (2013). On Semeai Detection in Monte-Carlo Go. In Proceedings of the International Conference on Computers and Games (CG). Springer. bibtex: '@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers, Lars and Platzner, Marco}, year={2013} }' chicago: Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proceedings of the International Conference on Computers and Games (CG). Springer, 2013. ieee: T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go.,” in Proceedings of the International Conference on Computers and Games (CG), 2013. mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings of the International Conference on Computers and Games (CG), Springer, 2013. short: 'T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.' date_created: 2019-10-04T22:50:51Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Conference on Computers and Games (CG) publisher: Springer status: public title: On Semeai Detection in Monte-Carlo Go. type: conference user_id: '398' year: '2013' ... --- _id: '528' abstract: - lang: eng text: Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394' apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394 bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }' chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394. ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.' mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394. short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.' date_created: 2017-10-17T12:42:35Z date_updated: 2023-09-26T13:37:35Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FPT.2013.6718394 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:36:08Z date_updated: 2018-03-15T10:36:08Z file_id: '1294' file_name: 528-plessl13_fpt.pdf file_size: 822680 relation: main_file success: 1 file_date_updated: 2018-03-15T10:36:08Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 386-389 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '13' name: SFB 901 - Subproject C1 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) publisher: IEEE quality_controlled: '1' status: public title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES type: conference user_id: '15278' year: '2013' ... --- _id: '505' abstract: - lang: eng text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Peter full_name: Kling, Peter last_name: Kling - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Friedhelm full_name: Meyer auf der Heide, Friedhelm id: '15523' last_name: Meyer auf der Heide citation: ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232' apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232' bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }' chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.' ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.' mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.' short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.' date_created: 2017-10-17T12:42:30Z date_updated: 2023-09-26T13:38:20Z ddc: - '040' department: - _id: '63' - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISORC.2013.6913232 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T13:38:56Z date_updated: 2018-03-15T13:38:56Z file_id: '1308' file_name: 505-Plessl13_seus.pdf file_size: 1040834 relation: main_file success: 1 file_date_updated: 2018-03-15T13:38:56Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) publisher: IEEE quality_controlled: '1' status: public title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services' type: conference user_id: '15278' year: '2013' ... --- _id: '1787' author: - first_name: Tim full_name: Suess, Tim last_name: Suess - first_name: Andrew full_name: Schoenrock, Andrew last_name: Schoenrock - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136' apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136 bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }' chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.' ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.' mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136. short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.' date_created: 2018-03-26T14:51:05Z date_updated: 2023-09-26T13:38:05Z department: - _id: '27' - _id: '518' - _id: '78' - _id: '63' doi: 10.1109/IPDPSW.2013.136 language: - iso: eng page: 64-73 place: Washington, DC, USA project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) publication_identifier: isbn: - 978-0-7695-4979-8 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer type: conference user_id: '15278' year: '2013' ... --- _id: '2097' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125' apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125 bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }' chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125. ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140. mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125. short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.' date_created: 2018-03-29T14:34:48Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/FPT.2012.6412125 page: 135-140 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2100' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.' apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG). bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }' chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012. ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012. mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012. short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.' date_created: 2018-03-29T14:43:18Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' publication: Int. Architecture and Engineering Symp. (ARCHENG) status: public title: FPGA implementation of a second-order convolutive blind signal separation algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2103' author: - first_name: Martin full_name: Wistuba, Martin last_name: Wistuba - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143' apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143 bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }' chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143. ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99. mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143. short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.' date_created: 2018-03-29T14:59:35Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/CIG.2012.6374143 page: 91-99 publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG) publisher: IEEE status: public title: Comparison of Bayesian Move Prediction Systems for Computer Go type: conference user_id: '24135' year: '2012' ... --- _id: '2172' author: - first_name: Kris full_name: Thielemans, Kris last_name: Thielemans - first_name: Charalampos full_name: Tsoumpas, Charalampos last_name: Tsoumpas - first_name: Sanida full_name: Mustafovic, Sanida last_name: Mustafovic - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Pablo full_name: Aguiar, Pablo last_name: Aguiar - first_name: Nikolaos full_name: Dikaios, Nikolaos last_name: Dikaios - first_name: Matthew full_name: W Jacobson, Matthew last_name: W Jacobson citation: ama: 'Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867' apa: 'Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867' bibtex: '@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }' chicago: 'Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel, Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no. 4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.' ieee: 'K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.' mla: 'Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.' short: K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883. date_created: 2018-04-03T09:02:27Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1088/0031-9155/57/4/867 intvolume: ' 57' issue: '4' page: 867-883 publication: Physics in Medicine and Biology publisher: IOP Publishing status: public title: 'STIR: Software for Tomographic Image Reconstruction Release 2' type: journal_article user_id: '24135' volume: 57 year: '2012' ... --- _id: '2173' author: - first_name: Soydan full_name: Redif, Soydan last_name: Redif - first_name: Server full_name: Kasap, Server last_name: Kasap citation: ama: Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343 apa: Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343 bibtex: '@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }' chicago: 'Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.' ieee: S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012. mla: Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343. short: S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651. date_created: 2018-04-03T09:05:36Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1080/00207217.2012.751343 intvolume: ' 100' issue: '12' page: 1646-1651 publication: Int. Journal of Electronics publisher: Taylor & Francis status: public title: Parallel algorithm for computation of second-order sequential best rotations type: journal_article user_id: '24135' volume: 100 year: '2012' ... --- _id: '2174' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Khaled full_name: Benkrid, Khaled last_name: Benkrid citation: ama: Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328. apa: Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328. bibtex: '@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }' chicago: 'Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.' ieee: S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012. mla: Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28. short: S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328. date_created: 2018-04-03T09:08:00Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' intvolume: ' 7' issue: '6' page: 1312-1328 publication: Journal of Computers publisher: Academy Publishers status: public title: Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer type: journal_article user_id: '24135' volume: 7 year: '2012' ... --- _id: '586' abstract: - lang: eng text: FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety. - lang: ger text: FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit. author: - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky citation: ama: 'Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.' apa: 'Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn.' bibtex: '@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }' chicago: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.' ieee: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.' mla: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.' short: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012.' date_created: 2017-10-17T12:42:46Z date_updated: 2022-01-06T07:02:44Z ddc: - '040' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:38:19Z date_updated: 2018-03-15T08:38:19Z file_id: '1261' file_name: 586-Drzevitzky-PhD_01.pdf file_size: 1438436 relation: main_file success: 1 file_date_updated: 2018-03-15T08:38:19Z has_accepted_license: '1' language: - iso: eng main_file_link: - open_access: '1' url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423 oa: '1' page: '114' project: - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication_status: published publisher: Universität Paderborn status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: 'Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security' type: dissertation user_id: '477' year: '2012' ... --- _id: '587' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers citation: ama: Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012. apa: Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine. bibtex: '@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }' chicago: Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012. ieee: C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine, 2012. mla: Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012. short: C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012. date_created: 2017-10-17T12:42:46Z date_updated: 2022-01-06T07:02:44Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:37:02Z date_updated: 2018-03-15T08:37:02Z file_id: '1260' file_name: 587-2012_plessl_awareness_magazine.pdf file_size: 353057 relation: main_file success: 1 file_date_updated: 2018-03-15T08:37:02Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publisher: Awareness Magazine status: public title: Programming models for reconfigurable heterogeneous multi-cores type: misc user_id: '398' year: '2012' ... --- _id: '10636' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2012.' apa: Boschmann, A., & Platzner, M. (2012). Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). bibtex: '@inproceedings{Boschmann_Platzner_2012, title={Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2012} }' chicago: Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012. ieee: A. Boschmann and M. Platzner, “Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012. mla: Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012. short: 'A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012.' date_created: 2019-07-10T11:03:21Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC) status: public title: Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array type: conference user_id: '3118' year: '2012' ... --- _id: '10650' author: - first_name: Denis full_name: Dridger, Denis last_name: Dridger citation: ama: Dridger D. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University; 2012. apa: Dridger, D. (2012). Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University. bibtex: '@book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }' chicago: Dridger, Denis. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012. ieee: D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012. mla: Dridger, Denis. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012. short: D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer, Paderborn University, 2012. date_created: 2019-07-10T11:10:59Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer type: mastersthesis user_id: '3118' year: '2012' ... --- _id: '10652' abstract: - lang: eng text: "The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores." author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers citation: ama: 'Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.' apa: 'Giefers, H. (2012). Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH.' bibtex: '@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }' chicago: 'Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.' ieee: 'H. Giefers, Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.' mla: Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Logos Verlag Berlin GmbH, 2012. short: H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores, Logos Verlag Berlin GmbH, Berlin, 2012. date_created: 2019-07-10T11:13:12Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: '159' place: Berlin publication_identifier: isbn: - 978-3-8325-3165-2 publication_status: published publisher: Logos Verlag Berlin GmbH status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Design and Programming of Reconfigurable Mesh based Many-Cores type: dissertation user_id: '3118' year: '2012' ... --- _id: '10658' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf citation: ama: Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012. apa: Graf, T. (2012). Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go. Paderborn University. bibtex: '@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }' chicago: Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012. ieee: T. Graf, Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go. Paderborn University, 2012. mla: Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012. short: T. Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go, Paderborn University, 2012. date_created: 2019-07-10T11:13:34Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Lars full_name: Schäfers, Lars last_name: Schäfers title: Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go type: mastersthesis user_id: '3118' year: '2012' ... --- _id: '10667' author: - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann citation: ama: Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012. apa: Hangmann, H. (2012). Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University. bibtex: '@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }' chicago: Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012. ieee: H. Hangmann, Generating Adjustable Temperature Gradients on modern FPGAs. Paderborn University, 2012. mla: Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012. short: H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Paderborn University, 2012. date_created: 2019-07-10T11:15:12Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Markus full_name: Happe, Markus last_name: Happe title: Generating Adjustable Temperature Gradients on modern FPGAs type: bachelorsthesis user_id: '3118' year: '2012' ... --- _id: '10685' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jim full_name: Torresen, Jim last_name: Torresen citation: ama: 'Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102' apa: 'Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2012). Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), 3(4), 17–31. https://doi.org/10.4018/jaras.2012100102' bibtex: '@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}, volume={3}, DOI={10.4018/jaras.2012100102}, number={4}, journal={International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }' chicago: 'Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3, no. 4 (2012): 17–31. https://doi.org/10.4018/jaras.2012100102.' ieee: 'P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012.' mla: 'Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:10.4018/jaras.2012100102.' short: P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31. date_created: 2019-07-10T11:28:10Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.4018/jaras.2012100102 intvolume: ' 3' issue: '4' language: - iso: eng page: 17-31 publication: International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) publisher: IGI Global status: public title: 'Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture' type: journal_article user_id: '3118' volume: 3 year: '2012' ... --- _id: '10723' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann citation: ama: Platzner M, Boschmann A, Kaufmann P. Wieder Natürlich Gehen Und Greifen.; 2012:6-11. apa: Platzner, M., Boschmann, A., & Kaufmann, P. (2012). Wieder natürlich gehen und greifen (pp. 6–11). bibtex: '@book{Platzner_Boschmann_Kaufmann_2012, title={Wieder natürlich gehen und greifen}, author={Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}, year={2012}, pages={6–11} }' chicago: Platzner, Marco, Alexander Boschmann, and Paul Kaufmann. Wieder Natürlich Gehen Und Greifen, 2012. ieee: M. Platzner, A. Boschmann, and P. Kaufmann, Wieder natürlich gehen und greifen. 2012, pp. 6–11. mla: Platzner, Marco, et al. Wieder Natürlich Gehen Und Greifen. 2012, pp. 6–11. short: M. Platzner, A. Boschmann, P. Kaufmann, Wieder Natürlich Gehen Und Greifen, 2012. date_created: 2019-07-10T11:54:15Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng page: 6-11 status: public title: Wieder natürlich gehen und greifen type: misc user_id: '398' year: '2012' ... --- _id: '10734' author: - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz citation: ama: Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012. apa: Schmitz, H. (2012). Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University. bibtex: '@book{Schmitz_2012, title={Stereo Matching on a HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Schmitz, Henning}, year={2012} }' chicago: Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012. ieee: H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012. mla: Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012. short: H. Schmitz, Stereo Matching on a HC-1 Hybrid Core Computer, Paderborn University, 2012. date_created: 2019-07-10T11:58:08Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Stereo Matching on a HC-1 Hybrid Core Computer type: bachelorsthesis user_id: '3118' year: '2012' ... --- _id: '10747' author: - first_name: Christoph full_name: Topmöller, Christoph last_name: Topmöller citation: ama: Topmöller C. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University; 2012. apa: Topmöller, C. (2012). Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System. Paderborn University. bibtex: '@book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }' chicago: Topmöller, Christoph. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University, 2012. ieee: C. Topmöller, Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System. Paderborn University, 2012. mla: Topmöller, Christoph. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University, 2012. short: C. Topmöller, Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System, Paderborn University, 2012. date_created: 2019-07-10T12:01:53Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System type: bachelorsthesis user_id: '3118' year: '2012' ... --- _id: '10754' author: - first_name: Martin full_name: Wistuba, Martin last_name: Wistuba citation: ama: Wistuba M. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University; 2012. apa: Wistuba, M. (2012). Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University. bibtex: '@book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }' chicago: Wistuba, Martin. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012. ieee: M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012. mla: Wistuba, Martin. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012. short: M. Wistuba, Analysis of Pattern Based Model Design and Learning in Computer-Go, Paderborn University, 2012. date_created: 2019-07-10T12:05:19Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Analysis of Pattern Based Model Design and Learning in Computer-Go type: mastersthesis user_id: '3118' year: '2012' ... --- _id: '13462' author: - first_name: Peter full_name: Lewis, Peter last_name: Lewis - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Xin full_name: Yao, Xin last_name: Yao citation: ama: Lewis P, Platzner M, Yao X. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine; 2012. apa: Lewis, P., Platzner, M., & Yao, X. (2012). An outlook for self-awareness in computing systems. Awareness Magazine. bibtex: '@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }' chicago: Lewis, Peter, Marco Platzner, and Xin Yao. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine, 2012. ieee: P. Lewis, M. Platzner, and X. Yao, An outlook for self-awareness in computing systems. Awareness Magazine, 2012. mla: Lewis, Peter, et al. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine, 2012. short: P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012. date_created: 2019-09-30T09:24:09Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 publisher: Awareness Magazine status: public title: An outlook for self-awareness in computing systems type: misc user_id: '398' year: '2012' ... --- _id: '2106' abstract: - lang: eng text: "Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view." author: - first_name: Björn full_name: Meyer, Björn last_name: Meyer - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: 'Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370' apa: Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370 bibtex: '@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }' chicago: Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370. ieee: 'B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.' mla: Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370. short: 'B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.' conference: name: 22nd International Conference on Field Programmable Logic and Applicaitons (FPL) date_created: 2018-03-29T15:04:25Z date_updated: 2023-09-26T13:39:13Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '15' - _id: '78' doi: 10.1109/FPL.2012.6339370 file: - access_level: closed content_type: application/pdf creator: fossie date_created: 2019-02-13T09:04:46Z date_updated: 2019-02-13T09:04:46Z file_id: '7638' file_name: 2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf file_size: 2148787 relation: main_file success: 1 file_date_updated: 2019-02-13T09:04:46Z has_accepted_license: '1' keyword: - funding-upb-forschungspreis - funding-maxup - tet_topic_hpc language: - iso: eng page: 189-196 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? type: conference user_id: '15278' year: '2012' ... --- _id: '2108' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002' bibtex: '@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.' mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.' short: T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126. date_created: 2018-03-29T15:12:38Z date_updated: 2023-09-26T13:39:30Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2011.04.002 intvolume: ' 36' issue: '2' keyword: - funding-altera language: - iso: eng page: 110-126 publication: Microprocessors and Microsystems publication_identifier: issn: - 0141-9331 quality_controlled: '1' status: public title: 'IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators' type: journal_article user_id: '15278' volume: 36 year: '2012' ... --- _id: '615' abstract: - lang: eng text: Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745' apa: Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745 bibtex: '@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }' chicago: Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745. ieee: 'M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.' mla: Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745. short: 'M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:51Z date_updated: 2023-09-26T13:42:26Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416745 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T06:48:32Z date_updated: 2018-03-15T06:48:32Z file_id: '1246' file_name: 615-ReConFig12_01.pdf file_size: 730144 relation: main_file success: 1 file_date_updated: 2018-03-15T06:48:32Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators type: conference user_id: '15278' year: '2012' ... --- _id: '591' abstract: - lang: eng text: One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz citation: ama: 'Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773' apa: Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773 bibtex: '@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }' chicago: Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773. ieee: 'T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.' mla: Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773. short: 'T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:47Z date_updated: 2023-09-26T13:41:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416773 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:33:18Z date_updated: 2018-03-15T08:33:18Z file_id: '1257' file_name: 591-ReConFig2012Kenter_Schmitz_Plessl.pdf file_size: 371235 relation: main_file success: 1 file_date_updated: 2018-03-15T08:33:18Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Pragma based parallelization - Trading hardware efficiency for ease of use? type: conference user_id: '15278' year: '2012' ... --- _id: '609' abstract: - lang: eng text: Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.' apa: Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9. bibtex: '@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }' chicago: Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012. ieee: M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. mla: Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. short: 'M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.' date_created: 2017-10-17T12:42:50Z date_updated: 2023-09-26T13:41:36Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:14:17Z date_updated: 2018-03-15T08:14:17Z file_id: '1249' file_name: 609-happe12_fpl_awareness.pdf file_size: 146789 relation: main_file success: 1 file_date_updated: 2018-03-15T08:14:17Z has_accepted_license: '1' language: - iso: eng page: 8-9 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) quality_controlled: '1' status: public title: Hardware/Software Platform for Self-aware Compute Nodes type: conference user_id: '15278' year: '2012' ... --- _id: '567' abstract: - lang: eng text: Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. author: - first_name: Pablo full_name: Barrio, Pablo last_name: Barrio - first_name: Carlos full_name: Carreras, Carlos last_name: Carreras - first_name: Roberto full_name: Sierra, Roberto last_name: Sierra - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973' apa: 'Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973' bibtex: '@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }' chicago: 'Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.' ieee: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.' mla: 'Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.' short: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.' date_created: 2017-10-17T12:42:42Z date_updated: 2023-09-26T13:42:54Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/HPCSim.2012.6266973 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:20:24Z date_updated: 2018-03-15T10:20:24Z file_id: '1275' file_name: 567-ba-ca-12a.pdf file_size: 288508 relation: main_file success: 1 file_date_updated: 2018-03-15T10:20:24Z has_accepted_license: '1' language: - iso: eng page: 559-565 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) publisher: IEEE quality_controlled: '1' status: public title: 'Turning control flow graphs into function calls: Code generation for heterogeneous architectures' type: conference user_id: '15278' year: '2012' ... --- _id: '612' abstract: - lang: eng text: While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. author: - first_name: Christoph full_name: Rüthing, Christoph last_name: Rüthing - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370' apa: Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370 bibtex: '@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }' chicago: Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370. ieee: 'C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.' mla: Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370. short: 'C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.' date_created: 2017-10-17T12:42:51Z date_updated: 2023-09-26T13:42:03Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FPL.2012.6339370 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T06:49:03Z date_updated: 2018-03-15T06:49:03Z file_id: '1247' file_name: 612-ruething_fpl12.pdf file_size: 202923 relation: main_file success: 1 file_date_updated: 2018-03-15T06:49:03Z has_accepted_license: '1' language: - iso: eng page: 559-562 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs type: conference user_id: '15278' year: '2012' ... --- _id: '2180' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.' apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }' chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012. ieee: T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012. mla: Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012. short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.' date_created: 2018-04-03T09:18:33Z date_updated: 2023-09-26T13:40:17Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - funding-enhance language: - iso: eng project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) quality_controlled: '1' status: public title: Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux type: conference user_id: '15278' year: '2012' ... --- _id: '2177' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315 apa: Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315 bibtex: '@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }' chicago: Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315. ieee: 'M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.' mla: Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315. short: M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012). date_created: 2018-04-03T09:13:22Z date_updated: 2023-09-26T13:39:48Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2012/418315 language: - iso: eng publication: Int. Journal of Reconfigurable Computing (IJRC) publisher: Hindawi Publishing Corp. quality_controlled: '1' status: public title: On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors type: journal_article user_id: '15278' year: '2012' ... --- _id: '2191' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Michael full_name: Kauschke, Michael last_name: Kauschke citation: ama: 'Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.' apa: Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference. bibtex: '@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }' chicago: Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011. ieee: T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011. mla: Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011. short: 'T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.' date_created: 2018-04-03T14:34:57Z date_updated: 2022-01-06T06:55:19Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - funding-intel publication: Intel European Research and Innovation Conference status: public title: Estimation and Partitioning for CPU-Accelerator Architectures type: conference user_id: '24135' year: '2011' ... --- _id: '2202' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global; 2011. doi:10.4018/978-1-60960-086-0' apa: 'Plessl, C., & Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui & H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global. https://doi.org/10.4018/978-1-60960-086-0' bibtex: '@inbook{Plessl_Platzner_2011, place={Hershey, PA, USA}, title={Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}, DOI={10.4018/978-1-60960-086-0}, booktitle={Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}, publisher={IGI Global}, author={Plessl, Christian and Platzner, Marco}, editor={Khalgui, Mohamed and Hanisch, Hans-MichaelEditors}, year={2011} }' chicago: 'Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-086-0.' ieee: 'C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.' mla: 'Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:10.4018/978-1-60960-086-0.' short: 'C. Plessl, M. Platzner, in: M. Khalgui, H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011.' date_created: 2018-04-03T15:11:16Z date_updated: 2022-01-06T06:55:22Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.4018/978-1-60960-086-0 editor: - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Hans-Michael full_name: Hanisch, Hans-Michael last_name: Hanisch place: Hershey, PA, USA project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: 'Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility' publication_identifier: isbn: - 978-1-60960-086-0 publisher: IGI Global status: public title: Hardware Virtualization on Dynamically Reconfigurable Embedded Processors type: book_chapter user_id: '24135' year: '2011' ... --- _id: '2204' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Ulf full_name: Lorenz, Ulf last_name: Lorenz - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers citation: ama: 'Graf T, Lorenz U, Platzner M, Schaefers L. Parallel Monte-Carlo Tree Search for HPC Systems. In: Proc. European Conf. on Parallel Processing (Euro-Par). Vol 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2011. doi:10.1007/978-3-642-23397-5_36' apa: 'Graf, T., Lorenz, U., Platzner, M., & Schaefers, L. (2011). Parallel Monte-Carlo Tree Search for HPC Systems. In Proc. European Conf. on Parallel Processing (Euro-Par) (Vol. 6853). Berlin / Heidelberg: Springer. https://doi.org/10.1007/978-3-642-23397-5_36' bibtex: '@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={10.1007/978-3-642-23397-5_36}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: 'Graf, Tobias, Ulf Lorenz, Marco Platzner, and Lars Schaefers. “Parallel Monte-Carlo Tree Search for HPC Systems.” In Proc. European Conf. on Parallel Processing (Euro-Par), Vol. 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2011. https://doi.org/10.1007/978-3-642-23397-5_36.' ieee: T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in Proc. European Conf. on Parallel Processing (Euro-Par), 2011, vol. 6853. mla: Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36. short: 'T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.' date_created: 2018-04-03T15:14:56Z date_updated: 2022-01-06T06:55:23Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-642-23397-5_36 intvolume: ' 6853' place: Berlin / Heidelberg publication: Proc. European Conf. on Parallel Processing (Euro-Par) publisher: Springer series_title: Lecture Notes in Computer Science (LNCS) status: public title: Parallel Monte-Carlo Tree Search for HPC Systems type: conference user_id: '24135' volume: 6853 year: '2011' ... --- _id: '666' abstract: - lang: eng text: Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach. author: - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Drzevitzky S, Platzner M. Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In: Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2011:58-65. doi:10.1109/ReCoSoC.2011.5981499' apa: Drzevitzky, S., & Platzner, M. (2011). Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 58–65). https://doi.org/10.1109/ReCoSoC.2011.5981499 bibtex: '@inproceedings{Drzevitzky_Platzner_2011, title={Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}, DOI={10.1109/ReCoSoC.2011.5981499}, booktitle={Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Drzevitzky, Stephanie and Platzner, Marco}, year={2011}, pages={58–65} }' chicago: Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 58–65, 2011. https://doi.org/10.1109/ReCoSoC.2011.5981499. ieee: S. Drzevitzky and M. Platzner, “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach,” in Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65. mla: Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach.” Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65, doi:10.1109/ReCoSoC.2011.5981499. short: 'S. Drzevitzky, M. Platzner, in: Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65.' date_created: 2017-10-17T12:43:01Z date_updated: 2022-01-06T07:03:14Z ddc: - '040' department: - _id: '78' doi: 10.1109/ReCoSoC.2011.5981499 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-14T13:40:48Z date_updated: 2018-03-14T13:40:48Z file_id: '1214' file_name: 666-drzevitzky11_recosoc.pdf file_size: 666039 relation: main_file success: 1 file_date_updated: 2018-03-14T13:40:48Z has_accepted_license: '1' language: - iso: eng page: 58-65 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) status: public title: Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach type: conference user_id: '477' year: '2011' ... --- _id: '10637' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Boschmann A, Kaufmann P, Platzner M. Accurate gait phase detection using surface electromyographic signals and support vector machines. In: Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT). ; 2011.' apa: Boschmann, A., Kaufmann, P., & Platzner, M. (2011). Accurate gait phase detection using surface electromyographic signals and support vector machines. In Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT). bibtex: '@inproceedings{Boschmann_Kaufmann_Platzner_2011, title={Accurate gait phase detection using surface electromyographic signals and support vector machines}, booktitle={Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT)}, author={Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco}, year={2011} }' chicago: Boschmann, Alexander, Paul Kaufmann, and Marco Platzner. “Accurate Gait Phase Detection Using Surface Electromyographic Signals and Support Vector Machines.” In Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011. ieee: A. Boschmann, P. Kaufmann, and M. Platzner, “Accurate gait phase detection using surface electromyographic signals and support vector machines,” in Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011. mla: Boschmann, Alexander, et al. “Accurate Gait Phase Detection Using Surface Electromyographic Signals and Support Vector Machines.” Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011. short: 'A. Boschmann, P. Kaufmann, M. Platzner, in: Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011.' date_created: 2019-07-10T11:03:22Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT) status: public title: Accurate gait phase detection using surface electromyographic signals and support vector machines type: conference user_id: '3118' year: '2011' ... --- _id: '10638' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Michael full_name: Robrecht, Michael last_name: Robrecht - first_name: Martin full_name: Hahn, Martin last_name: Hahn - first_name: Michael full_name: Winkler, Michael last_name: Winkler citation: ama: 'Boschmann A, Platzner M, Robrecht M, Hahn M, Winkler M. Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems. In: Proc. MyoElectric Controls Symposium (MEC). ; 2011.' apa: Boschmann, A., Platzner, M., Robrecht, M., Hahn, M., & Winkler, M. (2011). Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems. In Proc. MyoElectric Controls Symposium (MEC). bibtex: '@inproceedings{Boschmann_Platzner_Robrecht_Hahn_Winkler_2011, title={Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems}, booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander and Platzner, Marco and Robrecht, Michael and Hahn, Martin and Winkler, Michael}, year={2011} }' chicago: Boschmann, Alexander, Marco Platzner, Michael Robrecht, Martin Hahn, and Michael Winkler. “Development of a Pattern Recognition-Based Myoelectric Transhumeral Prosthesis with Multifunctional Simultaneous Control Using a Model-Driven Ppproach for Mechatronic Systems.” In Proc. MyoElectric Controls Symposium (MEC), 2011. ieee: A. Boschmann, M. Platzner, M. Robrecht, M. Hahn, and M. Winkler, “Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems,” in Proc. MyoElectric Controls Symposium (MEC), 2011. mla: Boschmann, Alexander, et al. “Development of a Pattern Recognition-Based Myoelectric Transhumeral Prosthesis with Multifunctional Simultaneous Control Using a Model-Driven Ppproach for Mechatronic Systems.” Proc. MyoElectric Controls Symposium (MEC), 2011. short: 'A. Boschmann, M. Platzner, M. Robrecht, M. Hahn, M. Winkler, in: Proc. MyoElectric Controls Symposium (MEC), 2011.' date_created: 2019-07-10T11:03:24Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Proc. MyoElectric Controls Symposium (MEC) status: public title: Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems type: conference user_id: '3118' year: '2011' ... --- _id: '10678' author: - first_name: Nikolaos full_name: Ikonomakis, Nikolaos last_name: Ikonomakis citation: ama: 'Ikonomakis N. PinSim: Schnelle Simulation Mit Pintools. Paderborn University; 2011.' apa: 'Ikonomakis, N. (2011). PinSim: Schnelle Simulation mit Pintools. Paderborn University.' bibtex: '@book{Ikonomakis_2011, title={PinSim: Schnelle Simulation mit Pintools}, publisher={Paderborn University}, author={Ikonomakis, Nikolaos}, year={2011} }' chicago: 'Ikonomakis, Nikolaos. PinSim: Schnelle Simulation Mit Pintools. Paderborn University, 2011.' ieee: 'N. Ikonomakis, PinSim: Schnelle Simulation mit Pintools. Paderborn University, 2011.' mla: 'Ikonomakis, Nikolaos. PinSim: Schnelle Simulation Mit Pintools. Paderborn University, 2011.' short: 'N. Ikonomakis, PinSim: Schnelle Simulation Mit Pintools, Paderborn University, 2011.' date_created: 2019-07-10T11:23:19Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: 'PinSim: Schnelle Simulation mit Pintools' type: bachelorsthesis user_id: '3118' year: '2011' ... --- _id: '10680' author: - first_name: Hendrik full_name: Kassner, Hendrik last_name: Kassner citation: ama: Kassner H. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern. Paderborn University; 2011. apa: Kassner, H. (2011). MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern. Paderborn University. bibtex: '@book{Kassner_2011, title={MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern}, publisher={Paderborn University}, author={Kassner, Hendrik}, year={2011} }' chicago: Kassner, Hendrik. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern. Paderborn University, 2011. ieee: H. Kassner, MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern. Paderborn University, 2011. mla: Kassner, Hendrik. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern. Paderborn University, 2011. short: H. Kassner, MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern, Paderborn University, 2011. date_created: 2019-07-10T11:23:21Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern type: bachelorsthesis user_id: '3118' year: '2011' ... --- _id: '10687' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Evolution of Embedded Systems. In: Müller-Schloer C, Schmeck H, Ungerer T, eds. Organic Computing---A Paradigm Shift for Complex Systems. Vol 1. Autonomic Systems. Springer Basel; 2011:193-206.' apa: Kaufmann, P., & Platzner, M. (2011). Multi-objective Intrinsic Evolution of Embedded Systems. In C. Müller-Schloer, H. Schmeck, & T. Ungerer (Eds.), Organic Computing---A Paradigm Shift for Complex Systems (Vol. 1, pp. 193–206). Springer Basel. bibtex: '@inbook{Kaufmann_Platzner_2011, series={Autonomic Systems}, title={Multi-objective Intrinsic Evolution of Embedded Systems}, volume={1}, booktitle={Organic Computing---A Paradigm Shift for Complex Systems}, publisher={Springer Basel}, author={Kaufmann, Paul and Platzner, Marco}, editor={Müller-Schloer, Christian and Schmeck, Hartmut and Ungerer, TheoEditors}, year={2011}, pages={193–206}, collection={Autonomic Systems} }' chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Evolution of Embedded Systems.” In Organic Computing---A Paradigm Shift for Complex Systems, edited by Christian Müller-Schloer, Hartmut Schmeck, and Theo Ungerer, 1:193–206. Autonomic Systems. Springer Basel, 2011. ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Evolution of Embedded Systems,” in Organic Computing---A Paradigm Shift for Complex Systems, vol. 1, C. Müller-Schloer, H. Schmeck, and T. Ungerer, Eds. Springer Basel, 2011, pp. 193–206. mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Evolution of Embedded Systems.” Organic Computing---A Paradigm Shift for Complex Systems, edited by Christian Müller-Schloer et al., vol. 1, Springer Basel, 2011, pp. 193–206. short: 'P. Kaufmann, M. Platzner, in: C. Müller-Schloer, H. Schmeck, T. Ungerer (Eds.), Organic Computing---A Paradigm Shift for Complex Systems, Springer Basel, 2011, pp. 193–206.' date_created: 2019-07-10T11:28:12Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' editor: - first_name: Christian full_name: Müller-Schloer, Christian last_name: Müller-Schloer - first_name: Hartmut full_name: Schmeck, Hartmut last_name: Schmeck - first_name: Theo full_name: Ungerer, Theo last_name: Ungerer intvolume: ' 1' language: - iso: eng page: 193-206 publication: Organic Computing---A Paradigm Shift for Complex Systems publisher: Springer Basel series_title: Autonomic Systems status: public title: Multi-objective Intrinsic Evolution of Embedded Systems type: book_chapter user_id: '3118' volume: 1 year: '2011' ... --- _id: '10736' author: - first_name: Arne full_name: Schwabe, Arne last_name: Schwabe citation: ama: Schwabe A. Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University; 2011. apa: Schwabe, A. (2011). Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University. bibtex: '@book{Schwabe_2011, title={Analysis of Algorithmic Approaches for Temporal Partitioning}, publisher={Paderborn University}, author={Schwabe, Arne}, year={2011} }' chicago: Schwabe, Arne. Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University, 2011. ieee: A. Schwabe, Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University, 2011. mla: Schwabe, Arne. Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University, 2011. short: A. Schwabe, Analysis of Algorithmic Approaches for Temporal Partitioning, Paderborn University, 2011. date_created: 2019-07-10T11:58:10Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Analysis of Algorithmic Approaches for Temporal Partitioning type: mastersthesis user_id: '3118' year: '2011' ... --- _id: '10737' author: - first_name: Lukas full_name: Sekanina, Lukas last_name: Sekanina - first_name: James Alfred full_name: Walker, James Alfred last_name: Walker - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic Circuits. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:125-179.' apa: Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., & Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg. bibtex: '@inbook{Sekanina_Walker_Kaufmann_Plessl_Platzner_2011, series={Natural Computing Series}, title={Evolution of Electronic Circuits}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2011}, pages={125–179}, collection={Natural Computing Series} }' chicago: Sekanina, Lukas, James Alfred Walker, Paul Kaufmann, Christian Plessl, and Marco Platzner. “Evolution of Electronic Circuits.” In Cartesian Genetic Programming, 125–79. Natural Computing Series. Springer Berlin Heidelberg, 2011. ieee: L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution of Electronic Circuits,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179. mla: Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–79. short: 'L. Sekanina, J.A. Walker, P. Kaufmann, C. Plessl, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.' date_created: 2019-07-10T11:59:35Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' - _id: '518' language: - iso: eng page: 125-179 publication: Cartesian Genetic Programming publisher: Springer Berlin Heidelberg series_title: Natural Computing Series status: public title: Evolution of Electronic Circuits type: book_chapter user_id: '3118' year: '2011' ... --- _id: '10748' author: - first_name: James Alfred full_name: Walker, James Alfred last_name: Walker - first_name: Julian F. full_name: Miller, Julian F. last_name: Miller - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walker JA, Miller JF, Kaufmann P, Platzner M. Problem Decomposition in Cartesian Genetic Programming. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:35-99.' apa: Walker, J. A., Miller, J. F., Kaufmann, P., & Platzner, M. (2011). Problem Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming (pp. 35–99). Springer Berlin Heidelberg. bibtex: '@inbook{Walker_Miller_Kaufmann_Platzner_2011, series={Natural Computing Series}, title={Problem Decomposition in Cartesian Genetic Programming}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}, year={2011}, pages={35–99}, collection={Natural Computing Series} }' chicago: Walker, James Alfred, Julian F. Miller, Paul Kaufmann, and Marco Platzner. “Problem Decomposition in Cartesian Genetic Programming.” In Cartesian Genetic Programming, 35–99. Natural Computing Series. Springer Berlin Heidelberg, 2011. ieee: J. A. Walker, J. F. Miller, P. Kaufmann, and M. Platzner, “Problem Decomposition in Cartesian Genetic Programming,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99. mla: Walker, James Alfred, et al. “Problem Decomposition in Cartesian Genetic Programming.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99. short: 'J.A. Walker, J.F. Miller, P. Kaufmann, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.' date_created: 2019-07-10T12:02:57Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng page: 35-99 publication: Cartesian Genetic Programming publisher: Springer Berlin Heidelberg series_title: Natural Computing Series status: public title: Problem Decomposition in Cartesian Genetic Programming type: book_chapter user_id: '3118' year: '2011' ... --- _id: '10750' author: - first_name: Daniel full_name: Welp, Daniel last_name: Welp citation: ama: Welp D. User Space Scheduling for Heterogeneous Systems. Paderborn University; 2011. apa: Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University. bibtex: '@book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems}, publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }' chicago: Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011. ieee: D. Welp, User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011. mla: Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011. short: D. Welp, User Space Scheduling for Heterogeneous Systems, Paderborn University, 2011. date_created: 2019-07-10T12:03:00Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: User Space Scheduling for Heterogeneous Systems type: mastersthesis user_id: '3118' year: '2011' ... --- _id: '13643' author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers citation: ama: 'Agne A, Platzner M, Lübbers E. Memory Virtualization for Multithreaded Reconfigurable Hardware. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2011:185-188. doi:10.1109/fpl.2011.42' apa: Agne, A., Platzner, M., & Lübbers, E. (2011). Memory Virtualization for Multithreaded Reconfigurable Hardware. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (pp. 185–188). IEEE. https://doi.org/10.1109/fpl.2011.42 bibtex: '@inproceedings{Agne_Platzner_Lübbers_2011, title={Memory Virtualization for Multithreaded Reconfigurable Hardware}, DOI={10.1109/fpl.2011.42}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Agne, Andreas and Platzner, Marco and Lübbers, Enno}, year={2011}, pages={185–188} }' chicago: Agne, Andreas, Marco Platzner, and Enno Lübbers. “Memory Virtualization for Multithreaded Reconfigurable Hardware.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 185–88. IEEE, 2011. https://doi.org/10.1109/fpl.2011.42. ieee: A. Agne, M. Platzner, and E. Lübbers, “Memory Virtualization for Multithreaded Reconfigurable Hardware,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2011, pp. 185–188. mla: Agne, Andreas, et al. “Memory Virtualization for Multithreaded Reconfigurable Hardware.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–88, doi:10.1109/fpl.2011.42. short: 'A. Agne, M. Platzner, E. Lübbers, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–188.' date_created: 2019-10-04T22:42:51Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2011.42 language: - iso: eng page: 185-188 publication: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781457714849' publication_status: published publisher: IEEE status: public title: Memory Virtualization for Multithreaded Reconfigurable Hardware type: conference user_id: '398' year: '2011' ... --- _id: '13644' author: - first_name: Jörg full_name: Henkel, Jörg last_name: Henkel - first_name: Lars full_name: Hedrich, Lars last_name: Hedrich - first_name: Andreas full_name: Herkersdorf, Andreas last_name: Herkersdorf - first_name: Rüdiger full_name: Kapitza, Rüdiger last_name: Kapitza - first_name: Daniel full_name: Lohmann, Daniel last_name: Lohmann - first_name: Peter full_name: Marwedel, Peter last_name: Marwedel - first_name: Marco full_name: Platzner, Marco last_name: Platzner - first_name: Wolfgang full_name: Rosenstiel, Wolfgang last_name: Rosenstiel - first_name: Ulf full_name: Schlichtmann, Ulf last_name: Schlichtmann - first_name: Olaf full_name: Spinczyk, Olaf last_name: Spinczyk - first_name: Mehdi full_name: Tahoori, Mehdi last_name: Tahoori - first_name: Lars full_name: Bauer, Lars last_name: Bauer - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich - first_name: Norbert full_name: Wehn, Norbert last_name: Wehn - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich - first_name: Joachim full_name: Becker, Joachim last_name: Becker - first_name: Oliver full_name: Bringmann, Oliver last_name: Bringmann - first_name: Uwe full_name: Brinkschulte, Uwe last_name: Brinkschulte - first_name: Samarjit full_name: Chakraborty, Samarjit last_name: Chakraborty - first_name: Michael full_name: Engel, Michael last_name: Engel - first_name: Rolf full_name: Ernst, Rolf last_name: Ernst - first_name: Hermann full_name: Härtig, Hermann last_name: Härtig citation: ama: 'Henkel J, Hedrich L, Herkersdorf A, et al. Design and architectures for dependable embedded systems. In: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11. ; 2011. doi:10.1145/2039370.2039384' apa: Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel, P., … Härtig, H. (2011). Design and architectures for dependable embedded systems. In Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11. https://doi.org/10.1145/2039370.2039384 bibtex: '@inproceedings{Henkel_Hedrich_Herkersdorf_Kapitza_Lohmann_Marwedel_Platzner_Rosenstiel_Schlichtmann_Spinczyk_et al._2011, title={Design and architectures for dependable embedded systems}, DOI={10.1145/2039370.2039384}, booktitle={Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11}, author={Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and et al.}, year={2011} }' chicago: Henkel, Jörg, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, et al. “Design and Architectures for Dependable Embedded Systems.” In Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011. https://doi.org/10.1145/2039370.2039384. ieee: J. Henkel et al., “Design and architectures for dependable embedded systems,” in Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11, 2011. mla: Henkel, Jörg, et al. “Design and Architectures for Dependable Embedded Systems.” Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011, doi:10.1145/2039370.2039384. short: 'J. Henkel, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, L. Bauer, J. Teich, N. Wehn, H.-J. Wunderlich, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, in: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011.' date_created: 2019-10-04T22:44:36Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1145/2039370.2039384 language: - iso: eng publication: Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11 publication_identifier: isbn: - '9781450307154' publication_status: published status: public title: Design and architectures for dependable embedded systems type: conference user_id: '398' year: '2011' ... --- _id: '2194' author: - first_name: Björn full_name: Meyer, Björn last_name: Meyer - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: 'Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12' apa: 'Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12' bibtex: '@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }' chicago: 'Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.' ieee: 'B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.' mla: 'Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.' short: 'B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.' date_created: 2018-04-03T14:55:57Z date_updated: 2023-09-26T13:44:11Z department: - _id: '27' - _id: '518' - _id: '15' - _id: '78' doi: 10.1109/SAAHPC.2011.12 keyword: - tet_topic_hpc language: - iso: eng page: 60-63 project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Symp. on Application Accelerators in High Performance Computing (SAAHPC) publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend' type: conference user_id: '15278' year: '2011' ... --- _id: '2193' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273' apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273 bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }' chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273. ieee: 'T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.' mla: Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273. short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.' date_created: 2018-04-03T14:37:14Z date_updated: 2023-09-26T13:43:48Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ASAP.2011.6043273 language: - iso: eng page: 223-226 project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publisher: IEEE Computer Society quality_controlled: '1' status: public title: Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler type: conference user_id: '15278' year: '2011' ... --- _id: '656' abstract: - lang: eng text: In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59' apa: Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59 bibtex: '@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }' chicago: Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59. ieee: 'M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.' mla: Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59. short: 'M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.' date_created: 2017-10-17T12:42:59Z date_updated: 2023-09-26T13:46:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2011.59 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-14T13:49:39Z date_updated: 2018-03-14T13:49:39Z file_id: '1220' file_name: 656-2011_happe_reconfig.pdf file_size: 502244 relation: main_file success: 1 file_date_updated: 2018-03-14T13:49:39Z has_accepted_license: '1' language: - iso: eng page: 55-60 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Measuring and Predicting Temperature Distributions on FPGAs at Run-Time type: conference user_id: '15278' year: '2011' ... --- _id: '2200' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Michael full_name: Kauschke, Michael last_name: Kauschke citation: ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448' apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448 bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }' chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.' ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.' mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448. short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.' date_created: 2018-04-03T15:08:13Z date_updated: 2023-09-26T13:45:04Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/1950413.1950448 keyword: - design space exploration - LLVM - partitioning - performance - estimation - funding-intel language: - iso: eng page: 177-180 place: New York, NY, USA publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) publication_identifier: isbn: - 978-1-4503-0554-9 publisher: ACM quality_controlled: '1' status: public title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures type: conference user_id: '15278' year: '2011' ... --- _id: '2201' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954' apa: 'Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC). https://doi.org/10.1155/2011/760954' bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={10.1155/2011/760954}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }' chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), 2011. https://doi.org/10.1155/2011/760954.' ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC), 2011, doi: 10.1155/2011/760954.' mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.' short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011). date_created: 2018-04-03T15:09:49Z date_updated: 2023-09-26T13:45:46Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2011/760954 keyword: - funding-altera language: - iso: eng publication: Int. Journal of Recon- figurable Computing (IJRC) publisher: Hindawi Publishing Corp. quality_controlled: '1' status: public title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study' type: journal_article user_id: '15278' year: '2011' ... --- _id: '2198' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153' apa: Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153 bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }' chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153. ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.' mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153. short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.' date_created: 2018-04-03T15:05:52Z date_updated: 2023-09-26T13:44:39Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/IPDPS.2011.153 language: - iso: eng page: 278-285 publication: Proc. Reconfigurable Architectures Workshop (RAW) publisher: IEEE Computer Society quality_controlled: '1' status: public title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture type: conference user_id: '15278' year: '2011' ... --- _id: '10605' author: - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Uwe full_name: Kastens, Uwe last_name: Kastens - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing. 2010;2010. doi:10.1155/2010/180242' apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing, 2010. https://doi.org/10.1155/2010/180242' bibtex: '@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={10.1155/2010/180242}, journal={International Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010} }' chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” International Journal of Reconfigurable Computing 2010 (2010). https://doi.org/10.1155/2010/180242.' ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” International Journal of Reconfigurable Computing, vol. 2010, 2010.' mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” International Journal of Reconfigurable Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242.' short: S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable Computing 2010 (2010). date_created: 2019-07-10T09:22:56Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' doi: 10.1155/2010/180242 intvolume: ' 2010' language: - iso: eng publication: International Journal of Reconfigurable Computing publisher: Hindawi Publishing Corporation status: public title: 'Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification' type: journal_article user_id: '3118' volume: 2010 year: '2010' ... --- _id: '10614' author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne citation: ama: Agne A. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University; 2010. apa: Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University. bibtex: '@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne, Andreas}, year={2010} }' chicago: Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010. ieee: A. Agne, Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010. mla: Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010. short: A. Agne, Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen, Paderborn University, 2010. date_created: 2019-07-10T09:25:12Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10629' alternative_title: - EMG-based Gait Analysis author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann citation: ama: Boschmann A. EMG-Basierte Ganganalyse. Paderborn University; 2010. apa: Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University. bibtex: '@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2010} }' chicago: Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010. ieee: A. Boschmann, EMG-basierte Ganganalyse. Paderborn University, 2010. mla: Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010. short: A. Boschmann, EMG-Basierte Ganganalyse, Paderborn University, 2010. date_created: 2019-07-10T09:40:27Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: EMG-basierte Ganganalyse type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10642' author: - first_name: Daniel full_name: Breitlauch, Daniel last_name: Breitlauch citation: ama: Breitlauch D. Evolvable Cache Controller. Paderborn University; 2010. apa: Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University. bibtex: '@book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2010} }' chicago: Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010. ieee: D. Breitlauch, Evolvable Cache Controller. Paderborn University, 2010. mla: Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010. short: D. Breitlauch, Evolvable Cache Controller, Paderborn University, 2010. date_created: 2019-07-10T11:03:43Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Evolvable Cache Controller type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10649' author: - first_name: Denis full_name: Dridger, Denis last_name: Dridger citation: ama: Dridger D. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University; 2010. apa: Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University. bibtex: '@book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010} }' chicago: Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010. ieee: D. Dridger, Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University, 2010. mla: Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010. short: D. Dridger, Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors, Paderborn University, 2010. date_created: 2019-07-10T11:10:58Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Soft Microprocessors with tightly coupled Application-Specific Coprocessors type: bachelorsthesis user_id: '3118' year: '2010' ... --- _id: '10657' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf citation: ama: Graf T. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University; 2010. apa: Graf, T. (2010). Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University. bibtex: '@book{Graf_2010, title={Parallelization of the UCT Algorithm on HPC-Clusters}, publisher={Paderborn University}, author={Graf, Tobias}, year={2010} }' chicago: Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010. ieee: T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010. mla: Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010. short: T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters, Paderborn University, 2010. date_created: 2019-07-10T11:13:33Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Parallelization of the UCT Algorithm on HPC-Clusters type: bachelorsthesis user_id: '3118' year: '2010' ... --- _id: '10683' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Kevin full_name: Englehart, Kevin last_name: Englehart - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Englehart K, Platzner M. Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE; 2010:6357-6360.' apa: 'Kaufmann, P., Englehart, K., & Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 6357–6360). IEEE.' bibtex: '@inproceedings{Kaufmann_Englehart_Platzner_2010, title={Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}, booktitle={International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}, publisher={IEEE}, author={Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}, year={2010}, pages={6357–6360} }' chicago: 'Kaufmann, Paul, Kevin Englehart, and Marco Platzner. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 6357–60. IEEE, 2010.' ieee: 'P. Kaufmann, K. Englehart, and M. Platzner, “Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms,” in International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2010, pp. 6357–6360.' mla: 'Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–60.' short: 'P. Kaufmann, K. Englehart, M. Platzner, in: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–6360.' date_created: 2019-07-10T11:27:27Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 6357-6360 publication: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) publisher: IEEE status: public title: 'Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms' type: conference user_id: '3118' year: '2010' ... --- _id: '10686' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Knieper T, Platzner M. A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC). IEEE; 2010:541-548.' apa: Kaufmann, P., Knieper, T., & Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) (pp. 541–548). IEEE. bibtex: '@inproceedings{Kaufmann_Knieper_Platzner_2010, title={A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}, booktitle={IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}, publisher={IEEE}, author={Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}, year={2010}, pages={541–548} }' chicago: Kaufmann, Paul, Tobias Knieper, and Marco Platzner. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), 541–48. IEEE, 2010. ieee: P. Kaufmann, T. Knieper, and M. Platzner, “A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers,” in IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), 2010, pp. 541–548. mla: Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–48. short: 'P. Kaufmann, T. Knieper, M. Platzner, in: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–548.' date_created: 2019-07-10T11:28:11Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 541-548 publication: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) publisher: IEEE status: public title: A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers type: conference user_id: '3118' year: '2010' ... --- _id: '10694' author: - first_name: Udo full_name: Kebschull, Udo last_name: Kebschull - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich citation: ama: Kebschull U, Platzner M, Teich J. Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques. 2010;4(3):157-158. doi:10.1049/iet-cdt.2010.9044 apa: Kebschull, U., Platzner, M., & Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques, 4(3), 157–158. https://doi.org/10.1049/iet-cdt.2010.9044 bibtex: '@article{Kebschull_Platzner_Teich_2010, title={Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}, volume={4}, DOI={10.1049/iet-cdt.2010.9044}, number={3}, journal={IET Computers Digital Techniques}, author={Kebschull, Udo and Platzner, Marco and Teich, Jürgen}, year={2010}, pages={157–158} }' chicago: 'Kebschull, Udo, Marco Platzner, and Jürgen Teich. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” IET Computers Digital Techniques 4, no. 3 (2010): 157–58. https://doi.org/10.1049/iet-cdt.2010.9044.' ieee: U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” IET Computers Digital Techniques, vol. 4, no. 3, pp. 157–158, 2010. mla: Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” IET Computers Digital Techniques, vol. 4, no. 3, 2010, pp. 157–58, doi:10.1049/iet-cdt.2010.9044. short: U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques 4 (2010) 157–158. date_created: 2019-07-10T11:30:01Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1049/iet-cdt.2010.9044 intvolume: ' 4' issue: '3' language: - iso: eng page: 157-158 publication: IET Computers Digital Techniques publication_identifier: issn: - 1751-8601 status: public title: Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial) type: journal_article user_id: '3118' volume: 4 year: '2010' ... --- _id: '10697' author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper citation: ama: Knieper T. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University; 2010. apa: Knieper, T. (2010). Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University. bibtex: '@book{Knieper_2010, title={Hybridization of Global Multi-Objective and Local Search Techniques}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2010} }' chicago: Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010. ieee: T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010. mla: Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010. short: T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques, Paderborn University, 2010. date_created: 2019-07-10T11:30:23Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Hybridization of Global Multi-Objective and Local Search Techniques type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10699' author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jim full_name: Torresen, Jim last_name: Torresen citation: ama: 'Knieper T, Kaufmann P, Glette K, Platzner M, Torresen J. Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 6274. LNCS. Springer; 2010:250-261.' apa: 'Knieper, T., Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2010). Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 6274, pp. 250–261). Springer.' bibtex: '@inproceedings{Knieper_Kaufmann_Glette_Platzner_Torresen_2010, series={LNCS}, title={Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture}, volume={6274}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Knieper, Tobias and Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2010}, pages={250–261}, collection={LNCS} }' chicago: 'Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner, and Jim Torresen. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 6274:250–61. LNCS. Springer, 2010.' ieee: 'T. Knieper, P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2010, vol. 6274, pp. 250–261.' mla: 'Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 6274, Springer, 2010, pp. 250–61.' short: 'T. Knieper, P. Kaufmann, K. Glette, M. Platzner, J. Torresen, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2010, pp. 250–261.' date_created: 2019-07-10T11:38:03Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 6274' language: - iso: eng page: 250-261 publication: IEEE Intl. Conf. on Evolvable Systems (ICES) publisher: Springer series_title: LNCS status: public title: 'Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture' type: conference user_id: '3118' volume: 6274 year: '2010' ... --- _id: '10704' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In: Platzner M, Teich J, Wehn N, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH; 2010:269-290. doi:10.1007/978-90-481-3485-4_13' apa: 'Lübbers, E., & Platzner, M. (2010). ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In M. Platzner, J. Teich, & N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications (pp. 269–290). Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4_13' bibtex: '@inbook{Lübbers_Platzner_2010, title={ReconOS: An Operating System for Dynamically Reconfigurable Hardware}, DOI={10.1007/978-90-481-3485-4_13}, booktitle={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, publisher={Springer-Verlag GmbH}, author={Lübbers, Enno and Platzner, Marco}, editor={Platzner, Marco and Teich, Jürgen and Wehn, NorbertEditors}, year={2010}, pages={269–290} }' chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” In Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner, Jürgen Teich, and Norbert Wehn, 269–90. Springer-Verlag GmbH, 2010. https://doi.org/10.1007/978-90-481-3485-4_13.' ieee: 'E. Lübbers and M. Platzner, “ReconOS: An Operating System for Dynamically Reconfigurable Hardware,” in Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, M. Platzner, J. Teich, and N. Wehn, Eds. Springer-Verlag GmbH, 2010, pp. 269–290.' mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner et al., Springer-Verlag GmbH, 2010, pp. 269–90, doi:10.1007/978-90-481-3485-4_13.' short: 'E. Lübbers, M. Platzner, in: M. Platzner, J. Teich, N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010, pp. 269–290.' date_created: 2019-07-10T11:41:18Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1007/978-90-481-3485-4_13 editor: - first_name: Marco full_name: Platzner, Marco last_name: Platzner - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich - first_name: Norbert full_name: Wehn, Norbert last_name: Wehn language: - iso: eng page: 269-290 publication: 'Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications' publisher: Springer-Verlag GmbH status: public title: 'ReconOS: An Operating System for Dynamically Reconfigurable Hardware' type: book_chapter user_id: '3118' year: '2010' ... --- _id: '10710' author: - first_name: Robert full_name: Meiche, Robert last_name: Meiche citation: ama: Meiche R. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University; 2010. apa: Meiche, R. (2010). FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University. bibtex: '@book{Meiche_2010, title={FPGA/CPU Multicore-Plattform für ReconOS/eCos}, publisher={Paderborn University}, author={Meiche, Robert}, year={2010} }' chicago: Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010. ieee: R. Meiche, FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University, 2010. mla: Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010. short: R. Meiche, FPGA/CPU Multicore-Plattform Für ReconOS/ECos, Paderborn University, 2010. date_created: 2019-07-10T11:43:35Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: FPGA/CPU Multicore-Plattform für ReconOS/eCos type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10717' author: - first_name: Manuel full_name: Niekamp, Manuel last_name: Niekamp citation: ama: Niekamp M. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University; 2010. apa: Niekamp, M. (2010). Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University. bibtex: '@book{Niekamp_2010, title={Transparente Hardwarebeschleunigung durch Shared Library Interposing}, publisher={Paderborn University}, author={Niekamp, Manuel}, year={2010} }' chicago: Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010. ieee: M. Niekamp, Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University, 2010. mla: Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010. short: M. Niekamp, Transparente Hardwarebeschleunigung Durch Shared Library Interposing, Paderborn University, 2010. date_created: 2019-07-10T11:48:28Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel title: Transparente Hardwarebeschleunigung durch Shared Library Interposing type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10731' author: - first_name: Bodo full_name: Runde, Bodo last_name: Runde citation: ama: Runde B. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University; 2010. apa: Runde, B. (2010). A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University. bibtex: '@book{Runde_2010, title={A Token-Ring Network-On-Chip for Message Passing in ReconOS}, publisher={Paderborn University}, author={Runde, Bodo}, year={2010} }' chicago: Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010. ieee: B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010. mla: Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010. short: B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS, Paderborn University, 2010. date_created: 2019-07-10T11:54:50Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: A Token-Ring Network-On-Chip for Message Passing in ReconOS type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10752' author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Wiersema T. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University; 2010. apa: Wiersema, T. (2010). Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University. bibtex: '@book{Wiersema_2010, title={Scheduling Support for Heterogeneous Hardware Accelerators under Linux}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2010} }' chicago: Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010. ieee: T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010. mla: Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010. short: T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux, Paderborn University, 2010. date_created: 2019-07-10T12:03:02Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel title: Scheduling Support for Heterogeneous Hardware Accelerators under Linux type: mastersthesis user_id: '3118' year: '2010' ... --- _id: '10763' citation: ama: 'Platzner M, Teich J, Wehn N, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH; 2010. doi:10.1007/978-90-481-3485-4' apa: 'Platzner, M., Teich, J., & Wehn, N. (Eds.). (2010). Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4' bibtex: '@book{Platzner_Teich_Wehn_2010, title={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, DOI={10.1007/978-90-481-3485-4}, publisher={Springer-Verlag GmbH}, year={2010} }' chicago: 'Platzner, Marco, Jürgen Teich, and Norbert Wehn, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010. https://doi.org/10.1007/978-90-481-3485-4.' ieee: 'M. Platzner, J. Teich, and N. Wehn, Eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010.' mla: 'Platzner, Marco, et al., editors. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010, doi:10.1007/978-90-481-3485-4.' short: 'M. Platzner, J. Teich, N. Wehn, eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010.' date_created: 2019-07-10T12:07:04Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1007/978-90-481-3485-4 editor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich - first_name: Norbert full_name: Wehn, Norbert last_name: Wehn language: - iso: eng publication_identifier: isbn: - '9048134846' publisher: Springer-Verlag GmbH status: public title: 'Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications' type: book_editor user_id: '3118' year: '2010' ... --- _id: '10776' author: - first_name: Mehrdad full_name: Khatir, Mehrdad last_name: Khatir - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Alireza full_name: Ejlali, Alireza last_name: Ejlali citation: ama: 'Khatir M, Ghasemzadeh Mohammadi H, Ejlali A. Sub-threshold charge recovery circuits. In: Computer Design (ICCD), 2010 IEEE International Conference On. IEEE; 2010:138-144. doi:10.1109/ICCD.2010.5647815' apa: Khatir, M., Ghasemzadeh Mohammadi, H., & Ejlali, A. (2010). Sub-threshold charge recovery circuits. In Computer Design (ICCD), 2010 IEEE International Conference on (pp. 138–144). IEEE. https://doi.org/10.1109/ICCD.2010.5647815 bibtex: '@inproceedings{Khatir_Ghasemzadeh Mohammadi_Ejlali_2010, title={Sub-threshold charge recovery circuits}, DOI={10.1109/ICCD.2010.5647815}, booktitle={Computer Design (ICCD), 2010 IEEE International Conference on}, publisher={IEEE}, author={Khatir, Mehrdad and Ghasemzadeh Mohammadi, Hassan and Ejlali, Alireza}, year={2010}, pages={138–144} }' chicago: Khatir, Mehrdad, Hassan Ghasemzadeh Mohammadi, and Alireza Ejlali. “Sub-Threshold Charge Recovery Circuits.” In Computer Design (ICCD), 2010 IEEE International Conference On, 138–44. IEEE, 2010. https://doi.org/10.1109/ICCD.2010.5647815. ieee: M. Khatir, H. Ghasemzadeh Mohammadi, and A. Ejlali, “Sub-threshold charge recovery circuits,” in Computer Design (ICCD), 2010 IEEE International Conference on, 2010, pp. 138–144. mla: Khatir, Mehrdad, et al. “Sub-Threshold Charge Recovery Circuits.” Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–44, doi:10.1109/ICCD.2010.5647815. short: 'M. Khatir, H. Ghasemzadeh Mohammadi, A. Ejlali, in: Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–144.' date_created: 2019-07-10T12:10:19Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/ICCD.2010.5647815 extern: '1' language: - iso: eng page: 138-144 publication: Computer Design (ICCD), 2010 IEEE International Conference on publisher: IEEE status: public title: Sub-threshold charge recovery circuits type: conference user_id: '3118' year: '2010' ... --- _id: '13640' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2010.' apa: 'Giefers, H., & Platzner, M. (2010). A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE.' bibtex: '@inproceedings{Giefers_Platzner_2010, title={A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier}, booktitle={Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }' chicago: 'Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2010.' ieee: 'H. Giefers and M. Platzner, “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), 2010.' mla: 'Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.' short: 'H. Giefers, M. Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.' date_created: 2019-10-04T22:31:38Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE status: public title: 'A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier' type: conference user_id: '398' year: '2010' ... --- _id: '13641' author: - first_name: Wilhelm full_name: Schäfer, Wilhelm last_name: Schäfer - first_name: Mauro full_name: Birattari, Mauro last_name: Birattari - first_name: Johannes full_name: Blömer, Johannes last_name: Blömer - first_name: Marco full_name: Dorigo, Marco last_name: Dorigo - first_name: Gregor full_name: Engels, Gregor last_name: Engels - first_name: Rehan full_name: O'Grady, Rehan last_name: O'Grady - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Franz-Josef full_name: Rammig, Franz-Josef last_name: Rammig - first_name: 'Wolfgang ' full_name: 'Reif, Wolfgang ' last_name: Reif - first_name: Ansgar full_name: Trächtler, Ansgar last_name: Trächtler citation: ama: 'Schäfer W, Birattari M, Blömer J, et al. Engineering Self-Coordinating Software Intensive Systems. In: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER). ; 2010:321-324.' apa: Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R., … Trächtler, A. (2010). Engineering Self-Coordinating Software Intensive Systems. In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) (pp. 321–324). bibtex: '@inproceedings{Schäfer_Birattari_Blömer_Dorigo_Engels_O’Grady_Platzner_Rammig_Reif_Trächtler_2010, title={Engineering Self-Coordinating Software Intensive Systems}, booktitle={Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)}, author={Schäfer, Wilhelm and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O’Grady, Rehan and Platzner, Marco and Rammig, Franz-Josef and Reif, Wolfgang and Trächtler, Ansgar}, year={2010}, pages={321–324} }' chicago: Schäfer, Wilhelm, Mauro Birattari, Johannes Blömer, Marco Dorigo, Gregor Engels, Rehan O’Grady, Marco Platzner, Franz-Josef Rammig, Wolfgang Reif, and Ansgar Trächtler. “Engineering Self-Coordinating Software Intensive Systems.” In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 321–24, 2010. ieee: W. Schäfer et al., “Engineering Self-Coordinating Software Intensive Systems,” in Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324. mla: Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–24. short: 'W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.' date_created: 2019-10-04T22:35:54Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng page: 321-324 publication: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) status: public title: Engineering Self-Coordinating Software Intensive Systems type: conference user_id: '398' year: '2010' ... --- _id: '13642' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.' apa: Giefers, H., & Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press. bibtex: '@inproceedings{Giefers_Platzner_2010, title={A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics}, booktitle={Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }' chicago: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010. ieee: H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010. mla: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010. short: 'H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.' date_created: 2019-10-04T22:37:54Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics type: conference user_id: '398' year: '2010' ... --- _id: '2223' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Ariane full_name: Keller, Ariane last_name: Keller - first_name: Bernhard full_name: Plattner, Bernhard last_name: Plattner citation: ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:225-231.' apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231. bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }' chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–31. CSREA Press, 2010. ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231. mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31. short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.' date_created: 2018-04-05T16:27:13Z date_updated: 2023-09-26T13:48:32Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 225-231 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware type: conference user_id: '15278' year: '2010' ... --- _id: '2216' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19' apa: Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19 bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={67–72} }' chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010. https://doi.org/10.1109/ReConFig.2010.19.' ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.' mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19. short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.' date_created: 2018-04-05T14:48:51Z date_updated: 2023-09-26T13:47:11Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2010.19 language: - iso: eng page: 67-72 place: Los Alamitos, CA, USA publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE Computer Society quality_controlled: '1' status: public title: Pruning the Design Space for Just-In-Time Processor Customization type: conference user_id: '15278' year: '2010' ... --- _id: '2224' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.' apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150. bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }' chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010. ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150. mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50. short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.' date_created: 2018-04-05T16:28:38Z date_updated: 2023-09-26T13:48:59Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 144-150 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: An Open Source Circuit Library with Benchmarking Facilities type: conference user_id: '15278' year: '2010' ... --- _id: '2220' author: - first_name: David full_name: Andrews, David last_name: Andrews - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.' apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.' bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }' chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165. CSREA Press, 2010.' ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.' mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.' short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.' date_created: 2018-04-05T14:57:07Z date_updated: 2023-09-26T13:47:33Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: '165' publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: 'Configurable Processor Architectures: History and Trends' type: conference user_id: '15278' year: '2010' ... --- _id: '2222' citation: ama: Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010. apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., & Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press. bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, year={2010} }' chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee, Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010. ieee: T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010. mla: Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010. short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010. date_created: 2018-04-05T15:00:49Z date_updated: 2023-09-26T13:48:00Z department: - _id: '27' - _id: '518' - _id: '78' editor: - first_name: Toomas P. full_name: Plaks, Toomas P. last_name: Plaks - first_name: David full_name: Andrews, David last_name: Andrews - first_name: Ronald full_name: DeMara, Ronald last_name: DeMara - first_name: Herman full_name: Lam, Herman last_name: Lam - first_name: Jooheung full_name: Lee, Jooheung last_name: Lee - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Greg full_name: Stitt, Greg last_name: Stitt language: - iso: eng publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) type: conference_editor user_id: '15278' year: '2010' ... --- _id: '2226' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Manuel full_name: Niekamp, Manuel last_name: Niekamp - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798' apa: Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798 bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}, DOI={10.1109/ASAP.2010.5540798}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }' chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798. ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.' mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798. short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.' date_created: 2018-04-05T16:39:34Z date_updated: 2023-09-26T13:49:21Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ASAP.2010.5540798 language: - iso: eng page: 65-72 publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publication_identifier: isbn: - 978-1-4244-6965-9 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators type: conference user_id: '15278' year: '2010' ... --- _id: '2206' author: - first_name: Ariane full_name: Keller, Ariane last_name: Keller - first_name: Bernhard full_name: Plattner, Bernhard last_name: Plattner - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341' apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341 bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }' chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341. ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.' mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341. short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.' date_created: 2018-04-04T09:36:16Z date_updated: 2023-09-26T13:51:00Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/GLOCOMW.2010.5700341 language: - iso: eng page: 372-376 publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) publication_identifier: isbn: - 978-1-4244-8864-3 publisher: IEEE quality_controlled: '1' status: public title: Reconfigurable Nodes for Future Networks type: conference user_id: '15278' year: '2010' ... --- _id: '2228' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Michael full_name: Kauschke, Michael last_name: Kauschke citation: ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). ; 2010.' apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }' chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010. ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010. mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010. short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.' date_created: 2018-04-05T16:43:04Z date_updated: 2023-09-26T13:50:04Z department: - _id: '27' - _id: '518' - _id: '78' editor: - first_name: Omar full_name: Hammami, Omar last_name: Hammami - first_name: Sandra full_name: Larrabee, Sandra last_name: Larrabee language: - iso: eng publication: Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) quality_controlled: '1' status: public title: Performance Estimation for the Exploration of CPU-Accelerator Architectures type: conference user_id: '15278' year: '2010' ... --- _id: '10639' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Michael full_name: Winkler, Michael last_name: Winkler citation: ama: 'Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In: Proc. Technically Assisted Rehabilitation (TAR). ; 2009.' apa: 'Boschmann, A., Kaufmann, P., Platzner, M., & Winkler, M. (2009). Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In Proc. Technically Assisted Rehabilitation (TAR).' bibtex: '@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009} }' chicago: 'Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” In Proc. Technically Assisted Rehabilitation (TAR), 2009.' ieee: 'A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets,” in Proc. Technically Assisted Rehabilitation (TAR), 2009.' mla: 'Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted Rehabilitation (TAR), 2009.' short: 'A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically Assisted Rehabilitation (TAR), 2009.' date_created: 2019-07-10T11:03:25Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Proc. Technically Assisted Rehabilitation (TAR) status: public title: 'Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets' type: conference user_id: '3118' year: '2009' ... --- _id: '10702' author: - first_name: Alexander full_name: Kostin, Alexander last_name: Kostin citation: ama: Kostin A. Evolvable Robot Controller. Paderborn University; 2009. apa: Kostin, A. (2009). Evolvable Robot Controller. Paderborn University. bibtex: '@book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn University}, author={Kostin, Alexander}, year={2009} }' chicago: Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009. ieee: A. Kostin, Evolvable Robot Controller. Paderborn University, 2009. mla: Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009. short: A. Kostin, Evolvable Robot Controller, Paderborn University, 2009. date_created: 2019-07-10T11:38:28Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Evolvable Robot Controller type: mastersthesis user_id: '3118' year: '2009' ... --- _id: '10703' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems. 2009;9(1):8:1-8:33. doi:10.1145/1596532.1596540' apa: 'Lübbers, E., & Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems, 9(1), 8:1-8:33. https://doi.org/10.1145/1596532.1596540' bibtex: '@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={10.1145/1596532.1596540}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }' chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems 9, no. 1 (2009): 8:1-8:33. https://doi.org/10.1145/1596532.1596540.' ieee: 'E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, pp. 8:1-8:33, 2009.' mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.' short: E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33. date_created: 2019-07-10T11:41:17Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1145/1596532.1596540 intvolume: ' 9' issue: '1' keyword: - Reconfigurable computing - multithreading - operating systems language: - iso: eng page: 8:1-8:33 publication: ACM Transactions on Embedded Computing Systems publication_identifier: issn: - 1539-9087 status: public title: 'ReconOS: Multithreaded Programming for Reconfigurable Computers' type: journal_article user_id: '3118' volume: 9 year: '2009' ... --- _id: '10746' author: - first_name: Martin full_name: Tofall, Martin last_name: Tofall citation: ama: Tofall M. Compiler for a Custom Instruction Set CPU. Paderborn University; 2009. apa: Tofall, M. (2009). Compiler for a Custom Instruction Set CPU. Paderborn University. bibtex: '@book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Tofall, Martin}, year={2009} }' chicago: Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009. ieee: M. Tofall, Compiler for a Custom Instruction Set CPU. Paderborn University, 2009. mla: Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009. short: M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University, 2009. date_created: 2019-07-10T12:01:52Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Compiler for a Custom Instruction Set CPU type: mastersthesis user_id: '3118' year: '2009' ... --- _id: '10749' author: - first_name: Alexander full_name: Warkentin, Alexander last_name: Warkentin citation: ama: Warkentin A. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University; 2009. apa: Warkentin, A. (2009). Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units. Paderborn University. bibtex: '@book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin, Alexander}, year={2009} }' chicago: Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009. ieee: A. Warkentin, Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009. mla: Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009. short: A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units, Paderborn University, 2009. date_created: 2019-07-10T12:02:58Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units type: mastersthesis user_id: '3118' year: '2009' ... --- _id: '10753' author: - first_name: Benedikt full_name: Wildenhain, Benedikt last_name: Wildenhain citation: ama: Wildenhain B. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University; 2009. apa: Wildenhain, B. (2009). Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University. bibtex: '@book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain, Benedikt}, year={2009} }' chicago: Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009. ieee: B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009. mla: Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009. short: B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009. date_created: 2019-07-10T12:05:17Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS type: bachelorsthesis user_id: '3118' year: '2009' ... --- _id: '10777' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Seyed Ghassem full_name: Miremadi, Seyed Ghassem last_name: Miremadi - first_name: Alireza full_name: Ejlali, Alireza last_name: Ejlali citation: ama: 'Ghasemzadeh Mohammadi H, Miremadi SG, Ejlali A. Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On. IEEE; 2009:252-255. doi:10.1109/PRDC.2009.69' apa: 'Ghasemzadeh Mohammadi, H., Miremadi, S. G., & Ejlali, A. (2009). Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on (pp. 252–255). IEEE. https://doi.org/10.1109/PRDC.2009.69' bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Miremadi_Ejlali_2009, title={Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}, DOI={10.1109/PRDC.2009.69}, booktitle={Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2009}, pages={252–255} }' chicago: 'Ghasemzadeh Mohammadi, Hassan, Seyed Ghassem Miremadi, and Alireza Ejlali. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, 252–55. IEEE, 2009. https://doi.org/10.1109/PRDC.2009.69.' ieee: 'H. Ghasemzadeh Mohammadi, S. G. Miremadi, and A. Ejlali, “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors,” in Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on, 2009, pp. 252–255.' mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–55, doi:10.1109/PRDC.2009.69.' short: 'H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.' date_created: 2019-07-10T12:11:34Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/PRDC.2009.69 extern: '1' language: - iso: eng page: 252-255 publication: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on publisher: IEEE status: public title: 'Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors' type: conference user_id: '3118' year: '2009' ... --- _id: '13632' author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer; 2009.' apa: Happe, M., Lübbers, E., & Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer. bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }' chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer, 2009. ieee: M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2009. mla: Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009. short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.' date_created: 2019-10-04T22:13:24Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC) publisher: Springer status: public title: A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms type: conference user_id: '398' year: '2009' ... --- _id: '13634' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS). ; 2009.' apa: 'Giefers, H., & Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS).' bibtex: '@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }' chicago: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.' ieee: 'H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh,” in Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.' mla: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.' short: 'H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.' date_created: 2019-10-04T22:16:01Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS) status: public title: 'Towards Models for Many-Cores: The Case for the Reconfigurable Mesh' type: conference user_id: '398' year: '2009' ... --- _id: '13635' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE; 2009.' apa: 'Giefers, H., & Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE.' bibtex: '@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }' chicago: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE, 2009.' ieee: 'H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores,” in Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, 2009.' mla: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.' short: 'H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.' date_created: 2019-10-04T22:17:57Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium publisher: IEEE status: public title: 'ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores' type: conference user_id: '398' year: '2009' ... --- _id: '13636' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable Systems. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.' apa: Lübbers, E., & Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE. bibtex: '@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2009} }' chicago: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009. ieee: E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable Systems,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009. mla: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009. short: 'E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.' date_created: 2019-10-04T22:20:12Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: 'Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ' publisher: IEEE status: public title: Cooperative Multithreading in Dynamically Reconfigurable Systems type: conference user_id: '398' year: '2009' ...