--- _id: '13637' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.' apa: Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE. bibtex: '@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }' chicago: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009. ieee: H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009. mla: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009. short: 'H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.' date_created: 2019-10-04T22:22:02Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: 'Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ' publisher: IEEE status: public title: Program-driven Fine-grained Power Management for the Reconfigurable Mesh type: conference user_id: '398' year: '2009' ... --- _id: '13638' author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645' apa: Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645 bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }' chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645. ieee: M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), 2009. mla: Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645. short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.' date_created: 2019-10-04T22:22:52Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpt.2009.5377645 language: - iso: eng publication: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT) publication_identifier: isbn: - '9781424443758' publication_status: published publisher: IEEE status: public title: An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning type: conference user_id: '398' year: '2009' ... --- _id: '13639' author: - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Uwe full_name: Kastens, Uwe last_name: Kastens - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.' apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.' bibtex: '@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }' chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2009.' ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.' mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.' short: 'S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.' date_created: 2019-10-04T22:25:10Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE status: public title: 'Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules' type: conference user_id: '398' year: '2009' ... --- _id: '2350' abstract: - lang: eng text: 'Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25' bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.' mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.' short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.' date_created: 2018-04-16T15:05:52Z date_updated: 2023-09-26T13:51:44Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FCCM.2009.25 keyword: - IMORC - interconnect - performance language: - iso: eng page: 275-278 publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) publication_identifier: isbn: - 978-1-4244-4450-2 publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing' type: conference user_id: '15278' year: '2009' ... --- _id: '2262' abstract: - lang: eng text: 'In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.' apa: 'Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.' bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }' chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.' ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.' mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.' short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.' date_created: 2018-04-06T15:18:24Z date_updated: 2023-09-26T13:53:11Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - EvoCache - evolvable hardware - computer architecture language: - iso: eng page: 11-18 place: Los Alamitos, CA, USA publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'EvoCaches: Application-specific Adaptation of Cache Mapping' type: conference user_id: '15278' year: '2009' ... --- _id: '2238' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32' apa: Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32 bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }' chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.' ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.' mla: Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32. short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.' date_created: 2018-04-05T17:11:28Z date_updated: 2023-09-26T13:52:32Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2009.32 keyword: - IMORC - graphics language: - iso: eng page: 119-124 place: Los Alamitos, CA, USA publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) publication_identifier: isbn: - 978-0-7695-3917-1 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 type: conference user_id: '15278' year: '2009' ... --- _id: '2261' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.' apa: Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344. bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }' chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009. ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344. mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44. short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.' date_created: 2018-04-06T15:15:47Z date_updated: 2023-09-26T13:52:52Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - IMORC - NOC - KNN - accelerator language: - iso: eng page: 338-344 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - 978-1-4244-3892-1 issn: - 1946-1488 publisher: IEEE quality_controlled: '1' status: public title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure type: conference user_id: '15278' year: '2009' ... --- _id: '2263' abstract: - lang: eng text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.' apa: 'Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.' bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }' chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.' ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.' mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.' short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.' date_created: 2018-04-06T15:19:51Z date_updated: 2023-09-26T13:53:30Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 319-322 place: USA publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-101-5 publisher: CSREA Press quality_controlled: '1' status: public title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX' type: conference user_id: '15278' year: '2009' ... --- _id: '2358' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Stefan full_name: Lietsch, Stefan last_name: Lietsch - first_name: Kris full_name: Thielemans, Kris last_name: Thielemans citation: ama: 'Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198' apa: Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198 bibtex: '@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }' chicago: Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198. ieee: T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference Record (NSS), 2008, pp. 4161–4168. mla: Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198. short: 'T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–4168.' date_created: 2018-04-17T10:59:40Z date_updated: 2022-01-06T06:55:57Z department: - _id: '27' - _id: '78' doi: 10.1109/NSSMIC.2008.4774198 page: 4161-4168 publication: IEEE Nuclear Science Symposium Conference Record (NSS) publisher: IEEE status: public title: A method for OSEM PET reconstruction on parallel architectures using STIR type: conference user_id: '24135' year: '2008' ... --- _id: '2365' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Sven full_name: Döhre, Sven last_name: Döhre - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Ulf full_name: Lorenz, Ulf last_name: Lorenz - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Andre full_name: Send, Andre last_name: Send - first_name: Alexander full_name: Warkentin, Alexander last_name: Warkentin citation: ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.' apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.' bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }' chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.' ieee: 'M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.' mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.' short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.' date_created: 2018-04-17T11:34:35Z date_updated: 2022-01-06T06:55:58Z department: - _id: '27' - _id: '78' page: 245-251 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-064-7 publisher: CSREA Press status: public title: 'The GOmputer: Accelerating GO with FPGAs' type: conference user_id: '24135' year: '2008' ... --- _id: '10628' alternative_title: - Effects of Pattern Matching Algorithms on Long-term Electromyography Signals author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann citation: ama: Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University; 2008. apa: Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University. bibtex: '@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }' chicago: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. ieee: A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. mla: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. short: A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen, Paderborn University, 2008. date_created: 2019-07-10T09:40:26Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10641' alternative_title: - Self-optimizing Cache Controller author: - first_name: Daniel full_name: Breitlauch, Daniel last_name: Breitlauch citation: ama: Breitlauch D. Selbstoptimierender Cache-Kontroller. Paderborn University; 2008. apa: Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn University. bibtex: '@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }' chicago: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. ieee: D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. mla: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. short: D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008. date_created: 2019-07-10T11:03:42Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Selbstoptimierender Cache-Kontroller type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10644' alternative_title: - Distributed Simulation of mobile Robots using EyeSim author: - first_name: Toni full_name: Ceylan, Toni last_name: Ceylan - first_name: Coni full_name: Yalcin, Coni last_name: Yalcin citation: ama: Ceylan T, Yalcin C. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University; 2008. apa: Ceylan, T., & Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University. bibtex: '@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }' chicago: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008. ieee: T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University, 2008. mla: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008. short: T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008. date_created: 2019-07-10T11:03:45Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Verteilte Simulation von mobilen Robotern mit EyeSim type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10653' author: - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Thiemo full_name: Gruber, Thiemo last_name: Gruber - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Bernhard full_name: Sick, Bernhard last_name: Sick - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: IEEE Adaptive Hardware and Systems (AHS). IEEE; 2008:32-39.' apa: Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., & Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp. 32–39). IEEE. bibtex: '@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }' chicago: Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” In IEEE Adaptive Hardware and Systems (AHS), 32–39. IEEE, 2008. ieee: K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS), 2008, pp. 32–39. mla: Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39. short: 'K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.' date_created: 2019-07-10T11:13:13Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 32-39 publication: IEEE Adaptive Hardware and Systems (AHS) publisher: IEEE status: public title: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control type: conference user_id: '3118' year: '2008' ... --- _id: '10656' author: - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 5216. LNCS. Springer; 2008:22-33.' apa: Glette, K., Torresen, J., Kaufmann, P., & Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer. bibtex: '@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={22–33}, collection={LNCS} }' chicago: Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 5216:22–33. LNCS. Springer, 2008. ieee: K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2008, vol. 5216, pp. 22–33. mla: Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 5216, Springer, 2008, pp. 22–33. short: 'K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33.' date_created: 2019-07-10T11:13:31Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 5216' language: - iso: eng page: 22-33 publication: IEEE Intl. Conf. on Evolvable Systems (ICES) publisher: Springer series_title: LNCS status: public title: A Comparison of Evolvable Hardware Architectures for Classification Tasks type: conference user_id: '3118' volume: 5216 year: '2008' ... --- _id: '10669' author: - first_name: Markus full_name: Happe, Markus last_name: Happe citation: ama: Happe M. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University; 2008. apa: Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University. bibtex: '@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }' chicago: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. ieee: M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. mla: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. short: M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008. date_created: 2019-07-10T11:15:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern type: mastersthesis user_id: '3118' year: '2008' ... --- _id: '10690' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann citation: ama: Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008. apa: Torresen, J., Glette, K., Platzner, M., & Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). bibtex: '@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }' chicago: Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008. ieee: J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008. mla: Torresen, Jim, et al. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008. short: J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008). date_created: 2019-07-10T11:29:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng status: public title: Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS) type: preprint user_id: '398' year: '2008' ... --- _id: '10691' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO). ACM Press; 2008:1219-1226.' apa: Kaufmann, P., & Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press. bibtex: '@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }' chicago: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), 1219–26. ACM Press, 2008. ieee: P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), 2008, pp. 1219–1226. mla: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–26. short: 'P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.' date_created: 2019-07-10T11:29:57Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 1219 - 1226 publication: Genetic and Evolutionary Computation (GECCO) publisher: ACM Press status: public title: Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming type: conference user_id: '3118' year: '2008' ... --- _id: '10696' alternative_title: - Multi-objective Optimizer IBEA for Digital Logic Design author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper citation: ama: Knieper T. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University; 2008. apa: Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University. bibtex: '@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }' chicago: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008. ieee: T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008. mla: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008. short: T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008. date_created: 2019-07-10T11:30:22Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10698' author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper - first_name: Bertrand full_name: Defo, Bertrand last_name: Defo - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: Biologically Inspired Collaborative Computing (BICC). Vol 268. IFIP International Federation for Information Processing. Springer; 2008:2313-222.' apa: Knieper, T., Defo, B., Kaufmann, P., & Platzner, M. (2008). On Robust Evolution of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC) (Vol. 268, pp. 2313–222). Springer. bibtex: '@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={2313–222}, collection={IFIP International Federation for Information Processing} }' chicago: Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In Biologically Inspired Collaborative Computing (BICC), 268:2313–222. IFIP International Federation for Information Processing. Springer, 2008. ieee: T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC), 2008, vol. 268, pp. 2313–222. mla: Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” Biologically Inspired Collaborative Computing (BICC), vol. 268, Springer, 2008, pp. 2313–222. short: 'T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.' date_created: 2019-07-10T11:38:02Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 268' language: - iso: eng page: 2313-222 publication: Biologically Inspired Collaborative Computing (BICC) publisher: Springer series_title: IFIP International Federation for Information Processing status: public title: On Robust Evolution of Digital Hardware type: conference user_id: '3118' volume: 268 year: '2008' ... --- _id: '10718' author: - first_name: Jörg full_name: Niklas, Jörg last_name: Niklas citation: ama: Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University; 2008. apa: Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University. bibtex: '@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }' chicago: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008. ieee: J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008. mla: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008. short: J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008. date_created: 2019-07-10T11:48:29Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10721' author: - first_name: Marco full_name: Östermann, Marco last_name: Östermann citation: ama: Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University; 2008. apa: Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University. bibtex: '@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }' chicago: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. ieee: M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. mla: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. short: M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008. date_created: 2019-07-10T11:52:51Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Raytracing on a Custom Instruction Set CPU type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10751' author: - first_name: Nico full_name: Westerheide, Nico last_name: Westerheide citation: ama: Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University; 2008. apa: Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University. bibtex: '@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }' chicago: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008. ieee: N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008. mla: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008. short: N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008. date_created: 2019-07-10T12:03:01Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Design and Evaluation of MicroBlaze Multi-core Architectures type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10778' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Hamed full_name: Tabkhi, Hamed last_name: Tabkhi - first_name: Seyed Ghassem full_name: Miremadi, Seyed Ghassem last_name: Miremadi - first_name: Alireza full_name: Ejlali, Alireza last_name: Ejlali citation: ama: 'Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497' apa: Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497 bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={10.1109/ICM.2008.5393497}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }' chicago: Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In 2008 International Conference on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497. ieee: H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447. mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497. short: 'H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.' date_created: 2019-07-10T12:11:35Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/ICM.2008.5393497 extern: '1' language: - iso: eng page: 444-447 publication: 2008 International Conference on Microelectronics publisher: IEEE status: public title: A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic type: conference user_id: '3118' year: '2008' ... --- _id: '13629' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE; 2008.' apa: Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE. bibtex: '@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }' chicago: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE, 2008. ieee: H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008. mla: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008. short: 'H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.' date_created: 2019-10-04T22:05:22Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) publisher: IEEE status: public title: Realizing Reconfigurable Mesh Algorithms on Softcore Arrays type: conference user_id: '398' year: '2008' ... --- _id: '13630' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008.' apa: Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press. bibtex: '@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }' chicago: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2008. ieee: E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008. mla: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008. short: 'E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.' date_created: 2019-10-04T22:07:14Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Communication and Synchronization in Multithreaded Reconfigurable Computing Systems type: conference user_id: '398' year: '2008' ... --- _id: '13631' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901' apa: Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901 bibtex: '@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={10.1109/fpl.2008.4629901}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }' chicago: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901. ieee: E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), 2008. mla: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901. short: 'E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.' date_created: 2019-10-04T22:07:43Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2008.4629901 language: - iso: eng publication: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424419609' publication_status: published publisher: IEEE status: public title: A portable abstraction layer for hardware threads type: conference user_id: '398' year: '2008' ... --- _id: '2364' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Robert full_name: Meiche, Robert last_name: Meiche - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.' apa: Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251. bibtex: '@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }' chicago: Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008. ieee: T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251. mla: Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51. short: 'T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.' date_created: 2018-04-17T11:33:32Z date_updated: 2023-09-26T13:54:24Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 245-251 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-064-7 publisher: CSREA Press quality_controlled: '1' status: public title: A Hardware Accelerator for k-th Nearest Neighbor Thinning type: conference user_id: '15278' year: '2008' ... --- _id: '2372' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008.' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).' bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.' mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' short: 'T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' date_created: 2018-04-17T12:05:28Z date_updated: 2023-09-26T13:55:51Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - IMORC - IP core - interconnect language: - iso: eng publication: Many-core and Reconfigurable Supercomputing Conference (MRSC) quality_controlled: '1' status: public title: 'IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers' type: conference user_id: '15278' year: '2008' ... --- _id: '6508' abstract: - lang: eng text: 'In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework''s modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73' apa: 'Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73' bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={10.1109/ahs.2007.73}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }' chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.' ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK, 2007, pp. 447–454.' mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.' short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.' conference: end_date: 2007-08-08 location: Edinburgh, UK name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) start_date: 2007-08-05 date_created: 2019-01-08T09:52:43Z date_updated: 2022-01-06T07:03:08Z department: - _id: '78' doi: 10.1109/ahs.2007.73 keyword: - integrated circuit design - hardware evolution - evolutionary hardware design - evolutionary optimizers - hash functions - preengineered circuits - Hardware - Circuits - Design optimization - Visualization - Genetic programming - Genetic mutations - Clustering algorithms - Biological cells - Field programmable gate arrays - Routing language: - iso: eng page: 447-454 publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) publication_identifier: isbn: - 076952866X - '9780769528663' publication_status: published publisher: IEEE status: public title: 'MOVES: A Modular Framework for Hardware Evolution' type: conference user_id: '3118' year: '2007' ... --- _id: '10623' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel citation: ama: Beisel T. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University; 2007. apa: Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University. bibtex: '@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }' chicago: Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007. ieee: T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007. mla: Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007. short: T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007. date_created: 2019-07-10T09:36:57Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10625' author: - first_name: Neil full_name: Bergmann, Neil last_name: Bergmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich citation: ama: Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405 apa: Bergmann, N., Platzner, M., & Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems, 2007, 1–2. https://doi.org/10.1155/2007/28405 bibtex: '@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }' chicago: 'Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems 2007 (2007): 1–2. https://doi.org/10.1155/2007/28405.' ieee: N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” {EURASIP} Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007. mla: Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405. short: N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2. date_created: 2019-07-10T09:40:11Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' doi: 10.1155/2007/28405 intvolume: ' 2007' language: - iso: eng page: 1-2 publication: '{EURASIP} Journal on Embedded Systems' publisher: Springer Science+Business Media status: public title: Dynamically Reconfigurable Architectures (editorial) type: journal_article user_id: '398' volume: 2007 year: '2007' ... --- _id: '10643' author: - first_name: Toni full_name: Ceylan, Toni last_name: Ceylan - first_name: Coni full_name: Yalcin, Coni last_name: Yalcin citation: ama: Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007. apa: Ceylan, T., & Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University. bibtex: '@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }' chicago: Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007. ieee: T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007. mla: Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007. short: T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007. date_created: 2019-07-10T11:03:44Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Distributed Simulation of mobile Robots using EyeSim type: bachelorsthesis user_id: '3118' year: '2007' ... --- _id: '10646' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186 apa: Danne, K., Mühlenbernd, R., & Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302. https://doi.org/10.1049/iet-cdt:20060186 bibtex: '@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }' chicago: 'Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques 1, no. 4 (2007): 295–302. https://doi.org/10.1049/iet-cdt:20060186.' ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007. mla: Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186. short: K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302. date_created: 2019-07-10T11:10:54Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1049/iet-cdt:20060186 intvolume: ' 1' issue: '4' keyword: - reconfigurable architectures - resource allocation - device reconfiguration time - dynamic hardware reconfiguration - dynamically reconfigurable hardware - light-weight runtime system - merge server distribute load - periodic real-time tasks - runtime system overheads - schedulability analysis - scheduling technique - server-based execution - synthesis tool flow language: - iso: eng page: 295-302 publication: IET Computers Digital Techniques publication_identifier: issn: - 1751-8601 status: public title: Server-based execution of periodic tasks on dynamically reconfigurable hardware type: journal_article user_id: '3118' volume: 1 year: '2007' ... --- _id: '10647' author: - first_name: Bertrand full_name: Defo, Bertrand last_name: Defo citation: ama: Defo B. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University; 2007. apa: Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University. bibtex: '@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }' chicago: Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. ieee: B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. mla: Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. short: B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007. date_created: 2019-07-10T11:10:55Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10648' author: - first_name: Sven full_name: Döhre, Sven last_name: Döhre citation: ama: Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007. apa: Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University. bibtex: '@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }' chicago: Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007. ieee: S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007. mla: Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007. short: S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007. date_created: 2019-07-10T11:10:56Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10689' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In: Architecture of Computing Systems (ARCS). Vol 4415. LNCS. Springer; 2007:199-208.' apa: 'Kaufmann, P., & Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.' bibtex: '@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }' chicago: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” In Architecture of Computing Systems (ARCS), 4415:199–208. LNCS. Springer, 2007.' ieee: 'P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208.' mla: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” Architecture of Computing Systems (ARCS), vol. 4415, Springer, 2007, pp. 199–208.' short: 'P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208.' date_created: 2019-07-10T11:29:03Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 4415' language: - iso: eng page: 199-208 publication: Architecture of Computing Systems (ARCS) publisher: Springer series_title: LNCS status: public title: 'Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution' type: conference user_id: '3118' volume: 4415 year: '2007' ... --- _id: '10709' alternative_title: - k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving Mechanism Acceleration author: - first_name: Robert full_name: Meiche, Robert last_name: Meiche citation: ama: Meiche R. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University; 2007. apa: Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University. bibtex: '@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }' chicago: Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. ieee: R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. mla: Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. short: R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007. date_created: 2019-07-10T11:43:33Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen type: bachelorsthesis user_id: '3118' year: '2007' ... --- _id: '10728' author: - first_name: Waldemar full_name: Reisch, Waldemar last_name: Reisch citation: ama: Reisch W. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University; 2007. apa: Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University. bibtex: '@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }' chicago: Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. ieee: W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. mla: Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. short: W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007. date_created: 2019-07-10T11:54:46Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10729' author: - first_name: Eike full_name: Rethmeier, Eike last_name: Rethmeier citation: ama: Rethmeier E. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University; 2007. apa: Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University. bibtex: '@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }' chicago: Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007. ieee: E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007. mla: Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007. short: E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007. date_created: 2019-07-10T11:54:47Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10735' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756.' apa: 'Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.' bibtex: '@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances in Parallel Computing} }' chicago: 'Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 15:749–56. Advances in Parallel Computing. IOS Press, 2007.' ieee: 'T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.' mla: 'Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), vol. 15, IOS Press, 2007, pp. 749–56.' short: 'T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.' date_created: 2019-07-10T11:58:09Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' intvolume: ' 15' language: - iso: eng page: 749-756 publication: 'Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)' publisher: IOS Press series_title: Advances in Parallel Computing status: public title: Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster type: conference user_id: '398' volume: 15 year: '2007' ... --- _id: '13627' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable Mesh Model. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380623' apa: Giefers, H., & Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380623 bibtex: '@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation Based on the Reconfigurable Mesh Model}, DOI={10.1109/fpl.2007.4380623}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2007} }' chicago: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380623. ieee: H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable Mesh Model,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007. mla: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380623. short: 'H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:57:25Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380623 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: A Many-Core Implementation Based on the Reconfigurable Mesh Model type: conference user_id: '398' year: '2007' ... --- _id: '13628' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686' apa: 'Lübbers, E., & Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380686' bibtex: '@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }' chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380686.' ieee: 'E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.' mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.' short: 'E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:58:35Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380686 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: 'ReconOS: An RTOS Supporting Hard-and Software Threads' type: conference user_id: '398' year: '2007' ... --- _id: '2401' abstract: - lang: eng text: ' This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit''s performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344' apa: Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344 bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }' chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344. ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348. mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344. short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.' date_created: 2018-04-17T13:43:21Z date_updated: 2022-01-06T06:56:05Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2006.270344 keyword: - temporal partitioning - retiming - ILP page: 345-348 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: Optimal Temporal Partitioning based on Slowdown and Retiming type: conference user_id: '24135' year: '2006' ... --- _id: '10688' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.' apa: Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). bibtex: '@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }' chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. short: 'P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.' date_created: 2019-07-10T11:28:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) status: public title: Multi-objective Intrinsic Hardware Evolution type: conference user_id: '3118' year: '2006' ... --- _id: '10716' author: - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd citation: ama: Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006. apa: Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University. bibtex: '@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }' chicago: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. ieee: R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006. mla: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. short: R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006. date_created: 2019-07-10T11:48:27Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks type: bachelorsthesis user_id: '3118' year: '2006' ... --- _id: '13624' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.' apa: Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE. bibtex: '@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006. ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006. mla: Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006. short: 'K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.' date_created: 2019-10-04T21:48:42Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE status: public title: Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions type: conference user_id: '398' year: '2006' ... --- _id: '13625' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.' apa: Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). bibtex: '@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. ieee: K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. mla: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. short: 'K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.' date_created: 2019-10-04T21:51:29Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) status: public title: An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices type: conference user_id: '398' year: '2006' ... --- _id: '13626' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.' apa: Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press. bibtex: '@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006. ieee: K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006. mla: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006. short: 'K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.' date_created: 2019-10-04T21:53:12Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) publisher: IEEE CS Press status: public title: Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware type: conference user_id: '398' year: '2006' ... --- _id: '2411' abstract: - lang: eng text: ' This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69' apa: Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69 bibtex: '@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }' chicago: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69. ieee: C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218. mla: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.' date_created: 2018-04-17T14:34:03Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1109/ASAP.2005.69 keyword: - Zippy page: 213-218 publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publisher: IEEE Computer Society status: public title: Zippy – A coarse-grained reconfigurable array with support for hardware virtualization type: conference user_id: '24135' year: '2005' ... --- _id: '2412' abstract: - lang: eng text: ' Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.' author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004 apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004 bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }' chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.' ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005. mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004. short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73. date_created: 2018-04-17T14:36:10Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2004.06.004 intvolume: ' 29' issue: 2-3 keyword: - FPGA - reconfigurable computing - co-simulation - Zippy page: 63-73 publication: Microprocessors and Microsystems publisher: Elsevier status: public title: System-level performance evaluation of reconfigurable processors type: journal_article user_id: '24135' volume: 29 year: '2005' ... --- _id: '13621' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720' apa: Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720 bibtex: '@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={10.1109/wises.2005.1438720}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. https://doi.org/10.1109/wises.2005.1438720. ieee: K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. mla: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005, doi:10.1109/wises.2005.1438720. short: 'K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.' date_created: 2019-10-04T21:38:53Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/wises.2005.1438720 language: - iso: eng publication: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) publication_identifier: isbn: - '3902463031' publication_status: published status: public title: Periodic real-time scheduling for FPGA computers type: conference user_id: '398' year: '2005' ... --- _id: '13622' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.' apa: Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS). bibtex: '@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. ieee: K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005. mla: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. short: 'K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.' date_created: 2019-10-04T21:42:02Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) status: public title: Memory-demanding Periodic Real-time Applications on FPGA Computers type: conference user_id: '398' year: '2005' ... --- _id: '13623' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787' apa: Danne, K., & Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press. https://doi.org/10.1109/fpl.2005.1515787 bibtex: '@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press, 2005. https://doi.org/10.1109/fpl.2005.1515787. ieee: K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), 2005. mla: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787. short: 'K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.' date_created: 2019-10-04T21:42:46Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2005.1515787 language: - iso: eng publication: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '0780393627' publication_status: published publisher: IEEE CS Press status: public title: A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware type: conference user_id: '398' year: '2005' ... --- _id: '2415' abstract: - lang: eng text: 'In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.' apa: Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press. bibtex: '@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }' chicago: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004. ieee: C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69. mla: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.' date_created: 2018-04-17T14:45:57Z date_updated: 2022-01-06T06:56:08Z department: - _id: '518' - _id: '78' keyword: - hardware virtualization page: 63-69 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Virtualization of Hardware – Introduction and Survey type: conference user_id: '24135' year: '2004' ... --- _id: '10742' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99' apa: 'Steiger, C., Walder, H., & Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers, 53(11), 1393–1407. https://doi.org/10.1109/tc.2004.99' bibtex: '@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }' chicago: 'Steiger, Christoph, Herbert Walder, and Marco Platzner. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers 53, no. 11 (2004): 1393–1407. https://doi.org/10.1109/tc.2004.99.' ieee: 'C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” {IEEE} Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.' mla: 'Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.' short: C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers 53 (2004) 1393–1407. date_created: 2019-07-10T12:00:43Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/tc.2004.99 intvolume: ' 53' issue: '11' language: - iso: eng page: 1393-1407 publication: '{IEEE} Transactions on Computers' status: public title: 'Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks' type: journal_article user_id: '3118' volume: 53 year: '2004' ... --- _id: '13618' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84' apa: 'Walder, H., & Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-30117-2_84' bibtex: '@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }' chicago: 'Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 831–35. Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84.' ieee: H. Walder and M. Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835. mla: Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84. short: 'H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.' date_created: 2019-10-04T21:28:56Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-30117-2_84 extern: '1' language: - iso: eng page: 831-835 place: Berlin, Heidelberg publication: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540229896' - '9783540301172' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer status: public title: A Runtime Environment for Reconfigurable Hardware Operating Systems type: conference user_id: '398' year: '2004' ... --- _id: '13619' author: - first_name: Hebert full_name: Walder, Hebert last_name: Walder - first_name: Samuel full_name: Nobs, Samuel last_name: Nobs - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.' apa: 'Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.' bibtex: '@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }' chicago: 'Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.' ieee: 'H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.' mla: 'Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' short: 'H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' date_created: 2019-10-04T21:31:54Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng publication: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems' type: conference user_id: '398' year: '2004' ... --- _id: '13620' author: - first_name: Matthias full_name: Dyer, Matthias last_name: Dyer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31' apa: Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31 bibtex: '@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }' chicago: Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31. ieee: M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004. mla: Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31. short: 'M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.' date_created: 2019-10-04T21:32:57Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fccm.2004.31 language: - iso: eng publication: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) publication_identifier: isbn: - '0769522300' publication_status: published publisher: IEEE CS Press status: public title: Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine type: conference user_id: '398' year: '2004' ... --- _id: '2418' abstract: - lang: eng text: ' This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system''s firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system''s firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755' apa: Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755 bibtex: '@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }' chicago: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755. ieee: C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259. mla: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.' date_created: 2018-04-17T15:03:34Z date_updated: 2022-01-06T06:56:09Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2003.1275755 keyword: - coprocessor - DIMM - memory bus - FPGA - high performance computing page: 252-259 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: TKDM – A Reconfigurable Co-processor in a PC's Memory Slot type: conference user_id: '24135' year: '2003' ... --- _id: '2419' abstract: - lang: eng text: 'Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Jan full_name: Beutel, Jan last_name: Beutel - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele - first_name: Gerhard full_name: Tröster, Gerhard last_name: Tröster citation: ama: Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x bibtex: '@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }' chicago: 'Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.' ieee: C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003. mla: Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x. short: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308. date_created: 2018-04-17T15:04:47Z date_updated: 2022-01-06T06:56:09Z department: - _id: '518' - _id: '78' doi: 10.1007/s00779-003-0243-x extern: '1' intvolume: ' 7' issue: '5' language: - iso: eng page: 299-308 publication: Personal and Ubiquitous Computing publisher: Springer status: public title: The Case for Reconfigurable Hardware in Wearable Computing type: journal_article user_id: '398' volume: 7 year: '2003' ... --- _id: '2420' abstract: - lang: eng text: ' This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592 apa: Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592 bibtex: '@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }' chicago: 'Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.' ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003. mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592. short: C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129. date_created: 2018-04-17T15:10:00Z date_updated: 2022-01-06T06:56:10Z department: - _id: '518' - _id: '78' doi: 10.1023/a:1024443416592 extern: '1' intvolume: ' 26' issue: '2' keyword: - reconfigurable computing - instance-specific acceleration - minimum covering language: - iso: eng page: 109-129 publication: Journal of Supercomputing publication_identifier: issn: - 0920-8542 publisher: Kluwer Academic Publishers status: public title: Instance-Specific Accelerators for Minimum Covering type: journal_article user_id: '398' volume: 26 year: '2003' ... --- _id: '2421' abstract: - lang: eng text: In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load. author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007' apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007 bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007. ieee: R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160. mla: Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007. short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.' date_created: 2018-04-17T15:11:25Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1007/b12007 intvolume: ' 2778' keyword: - Zippy - multi-context - FPGA page: 151-160 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: Springer series_title: Lecture Notes in Computer Science (LNCS) status: public title: Virtualizing Hardware with Multi-Context Reconfigurable Arrays type: conference user_id: '24135' volume: 2778 year: '2003' ... --- _id: '2422' abstract: - lang: eng text: Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs. author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.' apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press. bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }' chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003. ieee: R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180. mla: Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80. short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.' date_created: 2018-04-17T15:12:56Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' keyword: - Zippy - co-simulation page: 174-180 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-932415-05-X publisher: CSREA Press status: public title: Co-simulation of a Hybrid Multi-Context Architecture type: conference user_id: '24135' year: '2003' ... --- _id: '13612' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622' apa: Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622 bibtex: '@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }' chicago: Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622. ieee: H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295. mla: Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622. short: 'H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295.' date_created: 2019-10-04T21:15:31Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/date.2003.1253622 extern: '1' language: - iso: eng page: 290-295 publication: Proceedings Design, Automation and Test in Europe Conference (DATE) publication_identifier: isbn: - '0769518702' publication_status: published publisher: IEEE CS Press status: public title: Online scheduling for block-partitioned reconfigurable devices type: conference user_id: '398' year: '2003' ... --- _id: '13613' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329' apa: 'Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329' bibtex: '@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }' chicago: 'Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329.' ieee: 'H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.' mla: 'Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.' short: 'H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.' date_created: 2019-10-04T21:17:07Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/ipdps.2003.1213329 extern: '1' language: - iso: eng publication: Proceedings International Parallel and Distributed Processing Symposium publication_identifier: isbn: - '0769519261' publication_status: published publisher: IEEE CS Press status: public title: 'Fast online task placement on FPGAs: free space partitioning and 2D-hashing' type: conference user_id: '398' year: '2003' ... --- _id: '13614' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.' apa: 'Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.' bibtex: '@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }' chicago: 'Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.' ieee: 'H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.' mla: 'Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.' short: 'H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.' date_created: 2019-10-04T21:20:30Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 284-287 publication: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations' type: conference user_id: '398' year: '2003' ... --- _id: '13615' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56' apa: 'Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56' bibtex: '@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }' chicago: 'Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.' ieee: C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584. mla: Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56. short: 'C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.' date_created: 2019-10-04T21:20:41Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-45234-8_56 extern: '1' language: - iso: eng page: 575-584 place: Berlin, Heidelberg publication: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540408222' - '9783540452348' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer status: public title: Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices type: conference user_id: '398' year: '2003' ... --- _id: '13617' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269' apa: Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press. https://doi.org/10.1109/real.2003.1253269 bibtex: '@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }' chicago: Steiger, Christoph, Herbert Walder, Marco Platzner, and Lothar Thiele. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 252–235. IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269. ieee: C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235. mla: Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269. short: 'C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.' date_created: 2019-10-04T21:22:53Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/real.2003.1253269 language: - iso: eng page: 252-235 publication: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) publication_identifier: isbn: - '0769520448' publication_status: published publisher: IEEE CS Press status: public title: Online scheduling and placement of real-time tasks to partially reconfigurable devices type: conference user_id: '398' year: '2003' ... --- _id: '2423' abstract: - lang: eng text: 'Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Jan full_name: Beutel, Jan last_name: Beutel - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250' apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250 bibtex: '@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }' chicago: Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250. ieee: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222. mla: Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250. short: 'C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.' date_created: 2018-04-17T15:13:50Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1109/ISWC.2002.1167250 keyword: - wearable computing page: 215-222 publication: Proc. Int. Symp. on Wearable Computers (ISWC) publication_identifier: isbn: - 0-7695-1816-8 publisher: IEEE Computer Society status: public title: Reconfigurable Hardware in Wearable Computing Nodes type: conference user_id: '24135' year: '2002' ... --- _id: '2424' abstract: - lang: eng text: ' Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ' author: - first_name: Matthias full_name: Dyer, Matthias last_name: Dyer - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5' apa: Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5 bibtex: '@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5. ieee: M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301. mla: Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5. short: 'M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.' date_created: 2018-04-17T15:14:39Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1007/3-540-46117-5 intvolume: ' 2438' keyword: - partial reconfiguration page: 292-301 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: Springer series_title: Lecture Notes in Computer Science (LNCS) status: public title: Partially Reconfigurable Cores for Xilinx Virtex type: conference user_id: '24135' volume: 2438 year: '2002' ... --- _id: '2425' abstract: - lang: eng text: ' We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671' apa: Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671 bibtex: '@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }' chicago: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671. ieee: C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172. mla: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671. short: 'C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.' date_created: 2018-04-17T15:15:44Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1109/FPGA.2002.1106671 page: 163-172 publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE Computer Society status: public title: Custom Computing Machines for the Set Covering Problem type: conference user_id: '24135' year: '2002' ... --- _id: '10651' author: - first_name: Michael full_name: Eisenring, Michael last_name: Eisenring - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946 apa: Eisenring, M., & Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159. https://doi.org/10.1023/a:1013627403946 bibtex: '@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }' chicago: 'Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing 21, no. 2 (2002): 145–59. https://doi.org/10.1023/a:1013627403946.' ieee: M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002. mla: Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.” The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946. short: M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159. date_created: 2019-07-10T11:13:11Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1023/a:1013627403946 extern: '1' intvolume: ' 21' issue: '2' language: - iso: eng page: 145-159 publication: The Journal of Supercomputing publisher: Kluwer Academic Publishers status: public title: A Framework for Run-time Reconfigurable Systems type: journal_article user_id: '398' volume: 21 year: '2002' ... --- _id: '13611' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.' apa: 'Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.' bibtex: '@inproceedings{Walder_Platzner_2002, title={Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}, booktitle={Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2002}, pages={24–30} }' chicago: 'Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 24–30. CSREA Press, 2002.' ieee: 'H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.' mla: 'Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.' short: 'H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.' date_created: 2019-10-04T21:13:46Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 24-30 publication: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform' type: conference user_id: '398' year: '2002' ... --- _id: '2428' abstract: - lang: eng text: ' In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.' apa: Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press. bibtex: '@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }' chicago: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001. ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91. mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.' date_created: 2018-04-17T15:39:17Z date_updated: 2022-01-06T06:56:17Z department: - _id: '518' - _id: '78' keyword: - minimum covering - accelerator - funding-sundance page: 85-91 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Instance-Specific Accelerators for Minimum Covering type: conference user_id: '24135' year: '2001' ... --- _id: '2432' abstract: - lang: eng text: In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core. author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele - first_name: Gerhard full_name: Tröster, Gerhard last_name: Tröster citation: ama: 'Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376' apa: 'Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376' bibtex: '@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={10.1117/12.434376}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }' chicago: 'Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.' ieee: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.' mla: 'Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.' short: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.' date_created: 2018-04-17T15:51:39Z date_updated: 2022-01-06T06:56:17Z department: - _id: '518' - _id: '78' doi: 10.1117/12.434376 intvolume: ' 4525' keyword: - benchmark page: 135-146 publication: 'Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III' series_title: Proc. SPIE status: public title: 'Reconfigurable Processors for Handhelds and Wearables: Application Analysis' type: conference user_id: '24135' volume: 4525 year: '2001' ... --- _id: '10713' author: - first_name: Oskar full_name: Mencer, Oskar last_name: Mencer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Martin full_name: Morf, Martin last_name: Morf - first_name: Michael full_name: J. Flynn, Michael last_name: J. Flynn citation: ama: Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835 apa: Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835 bibtex: '@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }' chicago: 'Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9, no. 1 (2001): 205–10. https://doi.org/10.1109/92.920835.' ieee: O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, pp. 205–210, 2001. mla: Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835. short: O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210. date_created: 2019-07-10T11:47:42Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/92.920835 extern: '1' intvolume: ' 9' issue: '1' language: - iso: eng page: 205-210 publication: '{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems' status: public title: Object-oriented domain specific compilers for programming FPGAs type: journal_article user_id: '398' volume: 9 year: '2001' ... --- _id: '13463' author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001. apa: Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1). bibtex: '@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors}, publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler, Rolf and Platzner, Marco}, year={2001} }' chicago: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001. ieee: R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001. mla: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001. short: R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001. date_created: 2019-09-30T09:27:00Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' extern: '1' language: - iso: eng publisher: TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1) status: public title: Dynamically Reconfigurable Processors type: misc user_id: '398' year: '2001' ... --- _id: '6507' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322 apa: Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322 bibtex: '@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={10.1109/2.839322}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }' chicago: 'Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.' ieee: M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000. mla: Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.” Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322. short: M. Platzner, Computer 33 (2000) 58–60. date_created: 2019-01-08T09:45:03Z date_updated: 2022-01-06T07:03:08Z department: - _id: '78' - _id: '34' - _id: '7' doi: 10.1109/2.839322 extern: '1' intvolume: ' 33' issue: '4' language: - iso: eng page: 58-60 publication: Computer publication_identifier: issn: - 0018-9162 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Reconfigurable accelerators for combinatorial problems type: journal_article user_id: '398' volume: 33 year: '2000' ... --- _id: '10606' author: - first_name: Michael full_name: Eisenring, Michael last_name: Eisenring - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496 apa: Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496 bibtex: '@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496}, journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }' chicago: 'Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.' ieee: M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital Techniques, vol. 147, pp. 159–165, 2000. mla: Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496. short: M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques 147 (2000) 159–165. date_created: 2019-07-10T09:22:58Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' doi: 10.1049/ip-cdt:20000496 extern: '1' intvolume: ' 147' language: - iso: eng page: 159-165 publication: IEE Proceedings -- Computers & Digital Techniques publisher: IET status: public title: Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems type: journal_article user_id: '398' volume: 147 year: '2000' ... --- _id: '10725' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: 'Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68. doi:10.1109/5254.850829' apa: 'Platzner, M., Rinner, B., & Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems, 15(2), 62–68. https://doi.org/10.1109/5254.850829' bibtex: '@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative simulation: a specialized computer architecture for QSim}, volume={15}, DOI={10.1109/5254.850829}, number={2}, journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\&} Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={2000}, pages={62–68} }' chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” IEEE Intelligent Systems 15, no. 2 (2000): 62–68. https://doi.org/10.1109/5254.850829.' ieee: 'M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.' mla: 'Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.” IEEE Intelligent Systems, vol. 15, no. 2, Institute of Electrical {\&} Electronics Engineers ({IEEE}), 2000, pp. 62–68, doi:10.1109/5254.850829.' short: M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68. date_created: 2019-07-10T11:54:17Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/5254.850829 extern: '1' intvolume: ' 15' issue: '2' language: - iso: eng page: 62-68 publication: IEEE Intelligent Systems publisher: Institute of Electrical {\&} Electronics Engineers ({IEEE}) status: public title: 'Toward embedded qualitative simulation: a specialized computer architecture for QSim' type: journal_article user_id: '398' volume: 15 year: '2000' ... --- _id: '13609' author: - first_name: Michael H. full_name: Eisenring, Michael H. last_name: Eisenring - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.' apa: Eisenring, M. H., & Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press. bibtex: '@inproceedings{Eisenring_Platzner_2000, title={An Implementation Framework for Run-time Reconfigurable Systems}, booktitle={Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)}, publisher={CSREA Press}, author={Eisenring, Michael H. and Platzner, Marco}, year={2000}, pages={151–157} }' chicago: Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 151–57. CSREA Press, 2000. ieee: M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time Reconfigurable Systems,” in Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 2000, pp. 151–157. mla: Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–57. short: 'M.H. Eisenring, M. Platzner, in: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–157.' date_created: 2019-10-04T21:05:39Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 151-157 publication: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) publisher: CSREA Press status: public title: An Implementation Framework for Run-time Reconfigurable Systems type: conference user_id: '398' year: '2000' ... --- _id: '13610' author: - first_name: Michael full_name: Eisenring, Michael last_name: Eisenring - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL). Springer; 2000:565-574.' apa: Eisenring, M., & Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer. bibtex: '@inproceedings{Eisenring_Platzner_2000, title={Optimization of Run-time Reconfigurable Embedded Systems}, booktitle={Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={565–574} }' chicago: Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 565–74. Springer, 2000. ieee: M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded Systems,” in Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 2000, pp. 565–574. mla: Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–74. short: 'M. Eisenring, M. Platzner, in: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–574.' date_created: 2019-10-04T21:09:09Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 565-574 publication: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) publisher: Springer status: public title: Optimization of Run-time Reconfigurable Embedded Systems type: conference user_id: '398' year: '2000' ... --- _id: '13607' author: - first_name: Oskar full_name: Mencer, Oskar last_name: Mencer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press; 1999. doi:10.1109/hicss.1999.772883' apa: Mencer, O., & Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press. https://doi.org/10.1109/hicss.1999.772883 bibtex: '@inproceedings{Mencer_Platzner_1999, title={Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment}, DOI={10.1109/hicss.1999.772883}, booktitle={Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32)}, publisher={IEEE CS Press}, author={Mencer, Oskar and Platzner, Marco}, year={1999} }' chicago: Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press, 1999. https://doi.org/10.1109/hicss.1999.772883. ieee: O. Mencer and M. Platzner, “Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment,” in Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), 1999. mla: Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.” Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999, doi:10.1109/hicss.1999.772883. short: 'O. Mencer, M. Platzner, in: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999.' date_created: 2019-10-04T20:59:20Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/hicss.1999.772883 extern: '1' language: - iso: eng publication: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32) publication_identifier: isbn: - '0769500013' publication_status: published publisher: IEEE CS Press status: public title: Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment type: conference user_id: '398' year: '1999' ... --- _id: '13608' author: - first_name: Michael full_name: Eisenring, Michael last_name: Eisenring - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214. doi:10.1007/978-3-540-48302-1_21' apa: Eisenring, M., Platzner, M., & Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer. https://doi.org/10.1007/978-3-540-48302-1_21 bibtex: '@inproceedings{Eisenring_Platzner_Thiele_1999, series={LCS}, title={Communication Synthesis for Reconfigurable Embedded Systems}, volume={1673}, DOI={10.1007/978-3-540-48302-1_21}, booktitle={Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael and Platzner, Marco and Thiele, Lothar}, year={1999}, pages={205–214}, collection={LCS} }' chicago: Eisenring, Michael, Marco Platzner, and Lothar Thiele. “Communication Synthesis for Reconfigurable Embedded Systems.” In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), 1673:205–14. LCS. Springer, 1999. https://doi.org/10.1007/978-3-540-48302-1_21. ieee: M. Eisenring, M. Platzner, and L. Thiele, “Communication Synthesis for Reconfigurable Embedded Systems,” in Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), 1999, vol. 1673, pp. 205–214. mla: Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded Systems.” Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), vol. 1673, Springer, 1999, pp. 205–14, doi:10.1007/978-3-540-48302-1_21. short: 'M. Eisenring, M. Platzner, L. Thiele, in: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 1999, pp. 205–214.' date_created: 2019-10-04T21:01:05Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-48302-1_21 extern: '1' intvolume: ' 1673' language: - iso: eng page: 205-214 publication: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540664574' - '9783540483021' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer series_title: LCS status: public title: Communication Synthesis for Reconfigurable Embedded Systems type: conference user_id: '398' volume: 1673 year: '1999' ... --- _id: '10607' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Platzner M. Reconfigurable Computer Architectures. e&i Elektrotechnik und Informationstechnik. 1998;115:143-148. apa: Platzner, M. (1998). Reconfigurable Computer Architectures. E&i Elektrotechnik Und Informationstechnik, 115, 143–148. bibtex: '@article{Platzner_1998, title={Reconfigurable Computer Architectures}, volume={115}, journal={e&i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco}, year={1998}, pages={143–148} }' chicago: 'Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik Und Informationstechnik 115 (1998): 143–48.' ieee: M. Platzner, “Reconfigurable Computer Architectures,” e&i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998. mla: Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik Und Informationstechnik, vol. 115, Springer, 1998, pp. 143–48. short: M. Platzner, E&i Elektrotechnik Und Informationstechnik 115 (1998) 143–148. date_created: 2019-07-10T09:22:59Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' extern: '1' intvolume: ' 115' language: - iso: eng page: 143-148 publication: e&i Elektrotechnik und Informationstechnik publisher: Springer status: public title: Reconfigurable Computer Architectures type: journal_article user_id: '398' volume: 115 year: '1998' ... --- _id: '10608' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner citation: ama: Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications. 1998;5:106-116. apa: Platzner, M., & Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications, 5, 106–116. bibtex: '@article{Platzner_Rinner_1998, title={Design and Implementation of a Parallel Constraint Satisfaction Algorithm}, volume={5}, journal={International Journal of Computers & Their Applications}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1998}, pages={106–116} }' chicago: 'Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers & Their Applications 5 (1998): 106–16.' ieee: M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers & Their Applications, vol. 5, pp. 106–116, 1998. mla: Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers & Their Applications, vol. 5, ISCA, 1998, pp. 106–16. short: M. Platzner, B. Rinner, International Journal of Computers & Their Applications 5 (1998) 106–116. date_created: 2019-07-10T09:23:00Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' extern: '1' intvolume: ' 5' language: - iso: eng page: 106-116 publication: International Journal of Computers & Their Applications publisher: ISCA status: public title: Design and Implementation of a Parallel Constraint Satisfaction Algorithm type: journal_article user_id: '398' volume: 5 year: '1998' ... --- _id: '13464' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities; 1998:106-107. apa: Platzner, M., Rinner, B., & Weiss, R. (1998). A Distributed Computer Architecture for Fast Qualitative Simulation (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities. bibtex: '@book{Platzner_Rinner_Weiss_1998, title={A Distributed Computer Architecture for Fast Qualitative Simulation }, publisher={Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1998}, pages={106–107} }' chicago: Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998. ieee: M. Platzner, B. Rinner, and R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–107. mla: Platzner, Marco, et al. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–07. short: M. Platzner, B. Rinner, R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation , Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998. date_created: 2019-09-30T09:33:27Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' language: - iso: eng page: 106-107 publisher: Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe's leading Universities status: public title: 'A Distributed Computer Architecture for Fast Qualitative Simulation ' type: misc user_id: '398' year: '1998' ... --- _id: '13606' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: 'Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:10.1007/bfb0055234' apa: 'Platzner, M., & De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 69–78). Berlin, Heidelberg: Springer . https://doi.org/10.1007/bfb0055234' bibtex: '@inproceedings{Platzner_De Micheli_1998, place={Berlin, Heidelberg}, series={LNCS}, title={Acceleration of satisfiability algorithms by reconfigurable hardware}, DOI={10.1007/bfb0055234}, booktitle={Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={Springer }, author={Platzner, Marco and De Micheli, Giovanni}, year={1998}, pages={69–78}, collection={LNCS} }' chicago: 'Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , 69–78. LNCS. Berlin, Heidelberg: Springer , 1998. https://doi.org/10.1007/bfb0055234.' ieee: M. Platzner and G. De Micheli, “Acceleration of satisfiability algorithms by reconfigurable hardware,” in Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , 1998, pp. 69–78. mla: Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.” Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , 1998, pp. 69–78, doi:10.1007/bfb0055234. short: 'M. Platzner, G. De Micheli, in: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , Berlin, Heidelberg, 1998, pp. 69–78.' date_created: 2019-10-04T20:46:34Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/bfb0055234 extern: '1' language: - iso: eng page: 69-78 place: Berlin, Heidelberg publication: 'Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) ' publication_identifier: isbn: - '9783540649489' - '9783540680666' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: 'Springer ' series_title: LNCS status: public title: Acceleration of satisfiability algorithms by reconfigurable hardware type: conference user_id: '398' year: '1998' ... --- _id: '10609' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. e & i Elektrotechnik und Informationstechnik. 1997;114:13-18. apa: Platzner, M., Rinner, B., & Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. E & i Elektrotechnik Und Informationstechnik, 114, 13–18. bibtex: '@article{Platzner_Rinner_Weiss_1997, title={A Computer Architecture to Support Qualitative Simulation in Industrial Applications}, volume={114}, journal={e & i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={13–18} }' chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E & i Elektrotechnik Und Informationstechnik 114 (1997): 13–18.' ieee: M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e & i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997. mla: Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E & i Elektrotechnik Und Informationstechnik, vol. 114, Springer, 1997, pp. 13–18. short: M. Platzner, B. Rinner, R. Weiss, E & i Elektrotechnik Und Informationstechnik 114 (1997) 13–18. date_created: 2019-07-10T09:23:09Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' extern: '1' intvolume: ' 114' language: - iso: eng page: 13-18 publication: e & i Elektrotechnik und Informationstechnik publisher: Springer status: public title: A Computer Architecture to Support Qualitative Simulation in Industrial Applications type: journal_article user_id: '398' volume: 114 year: '1997' ... --- _id: '10724' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6 apa: Platzner, M., Rinner, B., & Weiss, R. (1997). Parallel qualitative simulation. Simulation Practice and Theory, 5(7–8), 623–638. https://doi.org/10.1016/s0928-4869(97)00008-6 bibtex: '@article{Platzner_Rinner_Weiss_1997, title={Parallel qualitative simulation}, volume={5}, DOI={10.1016/s0928-4869(97)00008-6}, number={7–8}, journal={Simulation Practice and Theory}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={623–638} }' chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative Simulation.” Simulation Practice and Theory 5, no. 7–8 (1997): 623–38. https://doi.org/10.1016/s0928-4869(97)00008-6.' ieee: M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997. mla: Platzner, Marco, et al. “Parallel Qualitative Simulation.” Simulation Practice and Theory, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:10.1016/s0928-4869(97)00008-6. short: M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997) 623–638. date_created: 2019-07-10T11:54:16Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1016/s0928-4869(97)00008-6 extern: '1' intvolume: ' 5' issue: 7-8 language: - iso: eng page: 623-638 publication: Simulation Practice and Theory publisher: Elsevier status: public title: Parallel qualitative simulation type: journal_article user_id: '398' volume: 5 year: '1997' ... --- _id: '13603' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Liliane full_name: Peters, Liliane last_name: Peters citation: ama: 'Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing. Vol 3166. ; 1997.' apa: 'Platzner, M., & Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).' bibtex: '@inproceedings{Platzner_Peters_1997, title={Fast Signature Segmentation on a Multi-DSP Architecture}, volume={3166}, booktitle={Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing}, author={Platzner, Marco and Peters, Liliane}, year={1997} }' chicago: 'Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, Vol. 3166, 1997.' ieee: 'M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,” in Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997, vol. 3166.' mla: 'Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, vol. 3166, 1997.' short: 'M. Platzner, L. Peters, in: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997.' date_created: 2019-10-04T20:40:55Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' intvolume: ' 3166' language: - iso: eng publication: 'Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing' status: public title: Fast Signature Segmentation on a Multi-DSP Architecture type: conference user_id: '398' volume: 3166 year: '1997' ... --- _id: '13604' author: - first_name: Thomas full_name: Röwekamp, Thomas last_name: Röwekamp - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: 'Liliane ' full_name: 'Peters, Liliane ' last_name: Peters citation: ama: 'Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1997:829-833.' apa: 'Röwekamp, T., Platzner, M., & Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) (pp. 829–833).' bibtex: '@inproceedings{Röwekamp_Platzner_Peters_1997, title={Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP}, booktitle={Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT)}, author={Röwekamp, Thomas and Platzner, Marco and Peters, Liliane }, year={1997}, pages={829–833} }' chicago: 'Röwekamp, Thomas, Marco Platzner, and Liliane Peters. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 829–33, 1997.' ieee: 'T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–833.' mla: 'Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–33.' short: 'T. Röwekamp, M. Platzner, L. Peters, in: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–833.' date_created: 2019-10-04T20:43:29Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 829-833 publication: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) status: public title: 'Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP' type: conference user_id: '398' year: '1997' ... --- _id: '13602' author: - first_name: Erich full_name: Lind, Erich last_name: Lind - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: 'Bernhard ' full_name: 'Rinner, Bernhard ' last_name: Rinner citation: ama: 'Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1996.' apa: Lind, E., Platzner, M., & Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT). bibtex: '@inproceedings{Lind_Platzner_Rinner_1996, title={A Multi-DSP System with Dynamically Reconfigurable Processors}, booktitle={Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT)}, author={Lind, Erich and Platzner, Marco and Rinner, Bernhard }, year={1996} }' chicago: Lind, Erich, Marco Platzner, and Bernhard Rinner. “A Multi-DSP System with Dynamically Reconfigurable Processors.” In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996. ieee: E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically Reconfigurable Processors,” in Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996. mla: Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.” Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996. short: 'E. Lind, M. Platzner, B. Rinner, in: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.' date_created: 2019-10-04T20:37:59Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng publication: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT) status: public title: A Multi-DSP System with Dynamically Reconfigurable Processors type: conference user_id: '398' year: '1996' ... --- _id: '10610' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. JUCS Journal of Universal Computer Science. 1995;12:811-820. apa: Platzner, M., Rinner, B., & Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal Computer Science, 12, 811–820. bibtex: '@article{Platzner_Rinner_Weiss_1995, title={Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation}, volume={12}, journal={J.UCS Journal of Universal Computer Science}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1995}, pages={811–820} }' chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science 12 (1995): 811–20.' ieee: M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995. mla: Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science, vol. 12, Springer, 1995, pp. 811–20. short: M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science 12 (1995) 811–820. date_created: 2019-07-10T09:23:10Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' extern: '1' intvolume: ' 12' language: - iso: eng page: 811-820 publication: J.UCS Journal of Universal Computer Science publisher: Springer status: public title: Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation type: journal_article user_id: '398' volume: 12 year: '1995' ... --- _id: '13469' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: 'Reinhold ' full_name: 'Weiss, Reinhold ' last_name: Weiss citation: ama: 'Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing . IEEE CS Press; 1995:311-318.' apa: Platzner, M., Rinner, B., & Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (pp. 311–318). IEEE CS Press. bibtex: '@inproceedings{Platzner_Rinner_Weiss_1995, title={A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs}, booktitle={Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing }, publisher={IEEE CS Press}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold }, year={1995}, pages={311–318} }' chicago: Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 311–18. IEEE CS Press, 1995. ieee: M. Platzner, B. Rinner, and R. Weiss, “A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs,” in Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 1995, pp. 311–318. mla: Platzner, Marco, et al. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–18. short: 'M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–318.' date_created: 2019-09-30T10:56:45Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' extern: '1' language: - iso: eng page: 311-318 publication: 'Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing ' publisher: IEEE CS Press status: public title: A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs type: conference user_id: '398' year: '1995' ... --- _id: '13470' author: - first_name: Eugen full_name: Brenner, Eugen last_name: Brenner - first_name: Robert full_name: Ginthör-Kalcsics, Robert last_name: Ginthör-Kalcsics - first_name: Robert full_name: Hranitzky, Robert last_name: Hranitzky - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: 'Bernhard ' full_name: 'Rinner, Bernhard ' last_name: Rinner - first_name: 'Christian ' full_name: 'Steger, Christian ' last_name: Steger - first_name: Reinhold full_name: Weiss, Reinhold last_name: Weiss citation: ama: 'Brenner E, Ginthör-Kalcsics R, Hranitzky R, et al. High-Performance Simulators Based on Multi-TMS320C40. In: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference. ; 1995.' apa: Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., & Weiss, R. (1995). High-Performance Simulators Based on Multi-TMS320C40. In Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference. bibtex: '@inproceedings{Brenner_Ginthör-Kalcsics_Hranitzky_Platzner_Rinner_Steger_Weiss_1995, title={High-Performance Simulators Based on Multi-TMS320C40}, booktitle={Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference}, author={Brenner, Eugen and Ginthör-Kalcsics, Robert and Hranitzky, Robert and Platzner, Marco and Rinner, Bernhard and Steger, Christian and Weiss, Reinhold}, year={1995} }' chicago: Brenner, Eugen, Robert Ginthör-Kalcsics, Robert Hranitzky, Marco Platzner, Bernhard Rinner, Christian Steger, and Reinhold Weiss. “High-Performance Simulators Based on Multi-TMS320C40.” In Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995. ieee: E. Brenner et al., “High-Performance Simulators Based on Multi-TMS320C40,” in Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995. mla: Brenner, Eugen, et al. “High-Performance Simulators Based on Multi-TMS320C40.” Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995. short: 'E. Brenner, R. Ginthör-Kalcsics, R. Hranitzky, M. Platzner, B. Rinner, C. Steger, R. Weiss, in: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995.' conference: name: Robert Ginthör-Kalcsics date_created: 2019-09-30T11:02:15Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference status: public title: High-Performance Simulators Based on Multi-TMS320C40 type: conference user_id: '398' year: '1995' ... --- _id: '13471' author: - first_name: Gerald full_name: Friedl, Gerald last_name: Friedl - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner citation: ama: 'Friedl G, Platzner M, Rinner B. A Special-Purpose Coprocessor for Qualitative Simulation. In: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing. Springer International Publishing; 1995:695-698.' apa: Friedl, G., Platzner, M., & Rinner, B. (1995). A Special-Purpose Coprocessor for Qualitative Simulation. In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing (pp. 695–698). Springer International Publishing. bibtex: '@inproceedings{Friedl_Platzner_Rinner_1995, title={A Special-Purpose Coprocessor for Qualitative Simulation}, booktitle={Proceedings of the EURO-PAR’95 International Conference on Parallel Processing}, publisher={Springer International Publishing}, author={Friedl, Gerald and Platzner, Marco and Rinner, Bernhard}, year={1995}, pages={695–698} }' chicago: Friedl, Gerald, Marco Platzner, and Bernhard Rinner. “A Special-Purpose Coprocessor for Qualitative Simulation.” In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 695–98. Springer International Publishing, 1995. ieee: G. Friedl, M. Platzner, and B. Rinner, “A Special-Purpose Coprocessor for Qualitative Simulation,” in Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 1995, pp. 695–698. mla: Friedl, Gerald, et al. “A Special-Purpose Coprocessor for Qualitative Simulation.” Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–98. short: 'G. Friedl, M. Platzner, B. Rinner, in: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–698.' date_created: 2019-09-30T11:15:06Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' extern: '1' language: - iso: eng page: 695-698 publication: Proceedings of the EURO-PAR'95 International Conference on Parallel Processing publisher: Springer International Publishing status: public title: A Special-Purpose Coprocessor for Qualitative Simulation type: conference user_id: '398' year: '1995' ... --- _id: '13472' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: 'Reinhold ' full_name: 'Weiss, Reinhold ' last_name: Weiss citation: ama: 'Platzner M, Rinner B, Weiss R. Parallel Qualitative Simulation. In: Proceedings of the EUROSIM Congress. Elsevier; 1995:231-236.' apa: Platzner, M., Rinner, B., & Weiss, R. (1995). Parallel Qualitative Simulation. In Proceedings of the EUROSIM Congress (pp. 231–236). Elsevier. bibtex: '@inproceedings{Platzner_Rinner_Weiss_1995, title={Parallel Qualitative Simulation}, booktitle={Proceedings of the EUROSIM Congress}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold }, year={1995}, pages={231–236} }' chicago: Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative Simulation.” In Proceedings of the EUROSIM Congress, 231–36. Elsevier, 1995. ieee: M. Platzner, B. Rinner, and R. Weiss, “Parallel Qualitative Simulation,” in Proceedings of the EUROSIM Congress, 1995, pp. 231–236. mla: Platzner, Marco, et al. “Parallel Qualitative Simulation.” Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–36. short: 'M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–236.' date_created: 2019-09-30T11:16:45Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' extern: '1' language: - iso: eng page: 231-236 publication: Proceedings of the EUROSIM Congress publisher: Elsevier status: public title: Parallel Qualitative Simulation type: conference user_id: '398' year: '1995' ... --- _id: '13473' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner citation: ama: 'Platzner M, Rinner B. Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems. ISCA; 1995:494-501.' apa: Platzner, M., & Rinner, B. (1995). Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems (pp. 494–501). ISCA. bibtex: '@inproceedings{Platzner_Rinner_1995, title={Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture}, booktitle={Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1995}, pages={494–501} }' chicago: Platzner, Marco, and Bernhard Rinner. “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture.” In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, 494–501. ISCA, 1995. ieee: M. Platzner and B. Rinner, “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture,” in Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, 1995, pp. 494–501. mla: Platzner, Marco, and Bernhard Rinner. “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture.” Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501. short: 'M. Platzner, B. Rinner, in: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501.' date_created: 2019-09-30T11:19:05Z date_updated: 2022-01-06T06:51:36Z department: - _id: '78' extern: '1' language: - iso: eng page: 494-501 publication: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems publisher: ISCA status: public title: Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture type: conference user_id: '398' year: '1995' ...