--- _id: '10735' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756.' apa: 'Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.' bibtex: '@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances in Parallel Computing} }' chicago: 'Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 15:749–56. Advances in Parallel Computing. IOS Press, 2007.' ieee: 'T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.' mla: 'Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), vol. 15, IOS Press, 2007, pp. 749–56.' short: 'T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.' date_created: 2019-07-10T11:58:09Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' intvolume: ' 15' language: - iso: eng page: 749-756 publication: 'Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)' publisher: IOS Press series_title: Advances in Parallel Computing status: public title: Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster type: conference user_id: '398' volume: 15 year: '2007' ... --- _id: '13627' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable Mesh Model. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380623' apa: Giefers, H., & Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380623 bibtex: '@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation Based on the Reconfigurable Mesh Model}, DOI={10.1109/fpl.2007.4380623}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2007} }' chicago: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380623. ieee: H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable Mesh Model,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007. mla: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380623. short: 'H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:57:25Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380623 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: A Many-Core Implementation Based on the Reconfigurable Mesh Model type: conference user_id: '398' year: '2007' ... --- _id: '13628' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686' apa: 'Lübbers, E., & Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380686' bibtex: '@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }' chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380686.' ieee: 'E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.' mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.' short: 'E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:58:35Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380686 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: 'ReconOS: An RTOS Supporting Hard-and Software Threads' type: conference user_id: '398' year: '2007' ... --- _id: '2401' abstract: - lang: eng text: ' This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit''s performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344' apa: Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344 bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }' chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344. ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348. mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344. short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.' date_created: 2018-04-17T13:43:21Z date_updated: 2022-01-06T06:56:05Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2006.270344 keyword: - temporal partitioning - retiming - ILP page: 345-348 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: Optimal Temporal Partitioning based on Slowdown and Retiming type: conference user_id: '24135' year: '2006' ... --- _id: '10688' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.' apa: Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). bibtex: '@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }' chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. short: 'P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.' date_created: 2019-07-10T11:28:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) status: public title: Multi-objective Intrinsic Hardware Evolution type: conference user_id: '3118' year: '2006' ... --- _id: '10716' author: - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd citation: ama: Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006. apa: Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University. bibtex: '@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }' chicago: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. ieee: R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006. mla: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. short: R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006. date_created: 2019-07-10T11:48:27Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks type: bachelorsthesis user_id: '3118' year: '2006' ... --- _id: '13624' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.' apa: Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE. bibtex: '@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006. ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006. mla: Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006. short: 'K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.' date_created: 2019-10-04T21:48:42Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE status: public title: Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions type: conference user_id: '398' year: '2006' ... --- _id: '13625' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.' apa: Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). bibtex: '@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. ieee: K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. mla: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. short: 'K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.' date_created: 2019-10-04T21:51:29Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) status: public title: An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices type: conference user_id: '398' year: '2006' ... --- _id: '13626' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.' apa: Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press. bibtex: '@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006. ieee: K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006. mla: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006. short: 'K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.' date_created: 2019-10-04T21:53:12Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) publisher: IEEE CS Press status: public title: Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware type: conference user_id: '398' year: '2006' ... --- _id: '2411' abstract: - lang: eng text: ' This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69' apa: Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69 bibtex: '@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }' chicago: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69. ieee: C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218. mla: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.' date_created: 2018-04-17T14:34:03Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1109/ASAP.2005.69 keyword: - Zippy page: 213-218 publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publisher: IEEE Computer Society status: public title: Zippy – A coarse-grained reconfigurable array with support for hardware virtualization type: conference user_id: '24135' year: '2005' ... --- _id: '2412' abstract: - lang: eng text: ' Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.' author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004 apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004 bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }' chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.' ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005. mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004. short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73. date_created: 2018-04-17T14:36:10Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2004.06.004 intvolume: ' 29' issue: 2-3 keyword: - FPGA - reconfigurable computing - co-simulation - Zippy page: 63-73 publication: Microprocessors and Microsystems publisher: Elsevier status: public title: System-level performance evaluation of reconfigurable processors type: journal_article user_id: '24135' volume: 29 year: '2005' ... --- _id: '13621' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720' apa: Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720 bibtex: '@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={10.1109/wises.2005.1438720}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. https://doi.org/10.1109/wises.2005.1438720. ieee: K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. mla: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005, doi:10.1109/wises.2005.1438720. short: 'K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.' date_created: 2019-10-04T21:38:53Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/wises.2005.1438720 language: - iso: eng publication: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) publication_identifier: isbn: - '3902463031' publication_status: published status: public title: Periodic real-time scheduling for FPGA computers type: conference user_id: '398' year: '2005' ... --- _id: '13622' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.' apa: Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS). bibtex: '@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. ieee: K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005. mla: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. short: 'K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.' date_created: 2019-10-04T21:42:02Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) status: public title: Memory-demanding Periodic Real-time Applications on FPGA Computers type: conference user_id: '398' year: '2005' ... --- _id: '13623' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787' apa: Danne, K., & Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press. https://doi.org/10.1109/fpl.2005.1515787 bibtex: '@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press, 2005. https://doi.org/10.1109/fpl.2005.1515787. ieee: K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), 2005. mla: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787. short: 'K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.' date_created: 2019-10-04T21:42:46Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2005.1515787 language: - iso: eng publication: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '0780393627' publication_status: published publisher: IEEE CS Press status: public title: A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware type: conference user_id: '398' year: '2005' ... --- _id: '2415' abstract: - lang: eng text: 'In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.' apa: Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press. bibtex: '@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }' chicago: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004. ieee: C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69. mla: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.' date_created: 2018-04-17T14:45:57Z date_updated: 2022-01-06T06:56:08Z department: - _id: '518' - _id: '78' keyword: - hardware virtualization page: 63-69 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Virtualization of Hardware – Introduction and Survey type: conference user_id: '24135' year: '2004' ... --- _id: '10742' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99' apa: 'Steiger, C., Walder, H., & Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers, 53(11), 1393–1407. https://doi.org/10.1109/tc.2004.99' bibtex: '@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }' chicago: 'Steiger, Christoph, Herbert Walder, and Marco Platzner. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers 53, no. 11 (2004): 1393–1407. https://doi.org/10.1109/tc.2004.99.' ieee: 'C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” {IEEE} Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.' mla: 'Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.' short: C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers 53 (2004) 1393–1407. date_created: 2019-07-10T12:00:43Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/tc.2004.99 intvolume: ' 53' issue: '11' language: - iso: eng page: 1393-1407 publication: '{IEEE} Transactions on Computers' status: public title: 'Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks' type: journal_article user_id: '3118' volume: 53 year: '2004' ... --- _id: '13618' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84' apa: 'Walder, H., & Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-30117-2_84' bibtex: '@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }' chicago: 'Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 831–35. Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84.' ieee: H. Walder and M. Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835. mla: Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84. short: 'H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.' date_created: 2019-10-04T21:28:56Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-30117-2_84 extern: '1' language: - iso: eng page: 831-835 place: Berlin, Heidelberg publication: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540229896' - '9783540301172' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer status: public title: A Runtime Environment for Reconfigurable Hardware Operating Systems type: conference user_id: '398' year: '2004' ... --- _id: '13619' author: - first_name: Hebert full_name: Walder, Hebert last_name: Walder - first_name: Samuel full_name: Nobs, Samuel last_name: Nobs - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.' apa: 'Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.' bibtex: '@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }' chicago: 'Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.' ieee: 'H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.' mla: 'Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' short: 'H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' date_created: 2019-10-04T21:31:54Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng publication: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems' type: conference user_id: '398' year: '2004' ... --- _id: '13620' author: - first_name: Matthias full_name: Dyer, Matthias last_name: Dyer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31' apa: Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31 bibtex: '@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }' chicago: Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31. ieee: M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004. mla: Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31. short: 'M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.' date_created: 2019-10-04T21:32:57Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fccm.2004.31 language: - iso: eng publication: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) publication_identifier: isbn: - '0769522300' publication_status: published publisher: IEEE CS Press status: public title: Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine type: conference user_id: '398' year: '2004' ... --- _id: '2418' abstract: - lang: eng text: ' This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system''s firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system''s firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755' apa: Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755 bibtex: '@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }' chicago: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755. ieee: C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259. mla: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.' date_created: 2018-04-17T15:03:34Z date_updated: 2022-01-06T06:56:09Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2003.1275755 keyword: - coprocessor - DIMM - memory bus - FPGA - high performance computing page: 252-259 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: TKDM – A Reconfigurable Co-processor in a PC's Memory Slot type: conference user_id: '24135' year: '2003' ...