--- _id: '2412' abstract: - lang: eng text: ' Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.' author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004 apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004 bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }' chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.' ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005. mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004. short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73. date_created: 2018-04-17T14:36:10Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2004.06.004 intvolume: ' 29' issue: 2-3 keyword: - FPGA - reconfigurable computing - co-simulation - Zippy page: 63-73 publication: Microprocessors and Microsystems publisher: Elsevier status: public title: System-level performance evaluation of reconfigurable processors type: journal_article user_id: '24135' volume: 29 year: '2005' ... --- _id: '13621' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720' apa: Danne, K., & Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). https://doi.org/10.1109/wises.2005.1438720 bibtex: '@inproceedings{Danne_Platzner_2005, title={Periodic real-time scheduling for FPGA computers}, DOI={10.1109/wises.2005.1438720}, booktitle={Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. https://doi.org/10.1109/wises.2005.1438720. ieee: K. Danne and M. Platzner, “Periodic real-time scheduling for FPGA computers,” in Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005. mla: Danne, Klaus, and Marco Platzner. “Periodic Real-Time Scheduling for FPGA Computers.” Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005, doi:10.1109/wises.2005.1438720. short: 'K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.' date_created: 2019-10-04T21:38:53Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/wises.2005.1438720 language: - iso: eng publication: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES) publication_identifier: isbn: - '3902463031' publication_status: published status: public title: Periodic real-time scheduling for FPGA computers type: conference user_id: '398' year: '2005' ... --- _id: '13622' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.' apa: Danne, K., & Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS). bibtex: '@inproceedings{Danne_Platzner_2005, title={Memory-demanding Periodic Real-time Applications on FPGA Computers}, booktitle={Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. ieee: K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005. mla: Danne, Klaus, and Marco Platzner. “Memory-Demanding Periodic Real-Time Applications on FPGA Computers.” Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005. short: 'K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.' date_created: 2019-10-04T21:42:02Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS) status: public title: Memory-demanding Periodic Real-time Applications on FPGA Computers type: conference user_id: '398' year: '2005' ... --- _id: '13623' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787' apa: Danne, K., & Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press. https://doi.org/10.1109/fpl.2005.1515787 bibtex: '@inproceedings{Danne_Platzner_2005, title={A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}, DOI={10.1109/fpl.2005.1515787}, booktitle={Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2005} }' chicago: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press, 2005. https://doi.org/10.1109/fpl.2005.1515787. ieee: K. Danne and M. Platzner, “A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware,” in Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), 2005. mla: Danne, Klaus, and Marco Platzner. “A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.” Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005, doi:10.1109/fpl.2005.1515787. short: 'K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.' date_created: 2019-10-04T21:42:46Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2005.1515787 language: - iso: eng publication: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '0780393627' publication_status: published publisher: IEEE CS Press status: public title: A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware type: conference user_id: '398' year: '2005' ... --- _id: '2415' abstract: - lang: eng text: 'In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.' apa: Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press. bibtex: '@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }' chicago: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004. ieee: C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69. mla: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.' date_created: 2018-04-17T14:45:57Z date_updated: 2022-01-06T06:56:08Z department: - _id: '518' - _id: '78' keyword: - hardware virtualization page: 63-69 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Virtualization of Hardware – Introduction and Survey type: conference user_id: '24135' year: '2004' ... --- _id: '10742' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99' apa: 'Steiger, C., Walder, H., & Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers, 53(11), 1393–1407. https://doi.org/10.1109/tc.2004.99' bibtex: '@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }' chicago: 'Steiger, Christoph, Herbert Walder, and Marco Platzner. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers 53, no. 11 (2004): 1393–1407. https://doi.org/10.1109/tc.2004.99.' ieee: 'C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” {IEEE} Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004.' mla: 'Steiger, Christoph, et al. “Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.” {IEEE} Transactions on Computers, vol. 53, no. 11, 2004, pp. 1393–407, doi:10.1109/tc.2004.99.' short: C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers 53 (2004) 1393–1407. date_created: 2019-07-10T12:00:43Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/tc.2004.99 intvolume: ' 53' issue: '11' language: - iso: eng page: 1393-1407 publication: '{IEEE} Transactions on Computers' status: public title: 'Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks' type: journal_article user_id: '3118' volume: 53 year: '2004' ... --- _id: '13618' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84' apa: 'Walder, H., & Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-30117-2_84' bibtex: '@inproceedings{Walder_Platzner_2004, place={Berlin, Heidelberg}, title={A Runtime Environment for Reconfigurable Hardware Operating Systems}, DOI={10.1007/978-3-540-30117-2_84}, booktitle={Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Walder, Herbert and Platzner, Marco}, year={2004}, pages={831–835} }' chicago: 'Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 831–35. Berlin, Heidelberg: Springer, 2004. https://doi.org/10.1007/978-3-540-30117-2_84.' ieee: H. Walder and M. Platzner, “A Runtime Environment for Reconfigurable Hardware Operating Systems,” in Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), 2004, pp. 831–835. mla: Walder, Herbert, and Marco Platzner. “A Runtime Environment for Reconfigurable Hardware Operating Systems.” Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2004, pp. 831–35, doi:10.1007/978-3-540-30117-2_84. short: 'H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.' date_created: 2019-10-04T21:28:56Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-30117-2_84 extern: '1' language: - iso: eng page: 831-835 place: Berlin, Heidelberg publication: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540229896' - '9783540301172' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer status: public title: A Runtime Environment for Reconfigurable Hardware Operating Systems type: conference user_id: '398' year: '2004' ... --- _id: '13619' author: - first_name: Hebert full_name: Walder, Hebert last_name: Walder - first_name: Samuel full_name: Nobs, Samuel last_name: Nobs - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.' apa: 'Walder, H., Nobs, S., & Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.' bibtex: '@inproceedings{Walder_Nobs_Platzner_2004, title={XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}, booktitle={Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Hebert and Nobs, Samuel and Platzner, Marco}, year={2004} }' chicago: 'Walder, Hebert, Samuel Nobs, and Marco Platzner. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2004.' ieee: 'H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.' mla: 'Walder, Hebert, et al. “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems.” Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' short: 'H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.' date_created: 2019-10-04T21:31:54Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng publication: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems' type: conference user_id: '398' year: '2004' ... --- _id: '13620' author: - first_name: Matthias full_name: Dyer, Matthias last_name: Dyer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31' apa: Dyer, M., Platzner, M., & Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press. https://doi.org/10.1109/fccm.2004.31 bibtex: '@inproceedings{Dyer_Platzner_Thiele_2004, title={Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}, DOI={10.1109/fccm.2004.31}, booktitle={Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE CS Press}, author={Dyer, Matthias and Platzner, Marco and Thiele, Lothar}, year={2004} }' chicago: Dyer, Matthias, Marco Platzner, and Lothar Thiele. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press, 2004. https://doi.org/10.1109/fccm.2004.31. ieee: M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004. mla: Dyer, Matthias, et al. “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.” Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004, doi:10.1109/fccm.2004.31. short: 'M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.' date_created: 2019-10-04T21:32:57Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fccm.2004.31 language: - iso: eng publication: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) publication_identifier: isbn: - '0769522300' publication_status: published publisher: IEEE CS Press status: public title: Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine type: conference user_id: '398' year: '2004' ... --- _id: '2418' abstract: - lang: eng text: ' This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system''s firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system''s firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755' apa: Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755 bibtex: '@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }' chicago: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755. ieee: C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259. mla: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.' date_created: 2018-04-17T15:03:34Z date_updated: 2022-01-06T06:56:09Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2003.1275755 keyword: - coprocessor - DIMM - memory bus - FPGA - high performance computing page: 252-259 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: TKDM – A Reconfigurable Co-processor in a PC's Memory Slot type: conference user_id: '24135' year: '2003' ... --- _id: '2419' abstract: - lang: eng text: 'Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Jan full_name: Beutel, Jan last_name: Beutel - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele - first_name: Gerhard full_name: Tröster, Gerhard last_name: Tröster citation: ama: Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x bibtex: '@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }' chicago: 'Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.' ieee: C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003. mla: Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x. short: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308. date_created: 2018-04-17T15:04:47Z date_updated: 2022-01-06T06:56:09Z department: - _id: '518' - _id: '78' doi: 10.1007/s00779-003-0243-x extern: '1' intvolume: ' 7' issue: '5' language: - iso: eng page: 299-308 publication: Personal and Ubiquitous Computing publisher: Springer status: public title: The Case for Reconfigurable Hardware in Wearable Computing type: journal_article user_id: '398' volume: 7 year: '2003' ... --- _id: '2420' abstract: - lang: eng text: ' This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592 apa: Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592 bibtex: '@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }' chicago: 'Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592.' ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003. mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592. short: C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129. date_created: 2018-04-17T15:10:00Z date_updated: 2022-01-06T06:56:10Z department: - _id: '518' - _id: '78' doi: 10.1023/a:1024443416592 extern: '1' intvolume: ' 26' issue: '2' keyword: - reconfigurable computing - instance-specific acceleration - minimum covering language: - iso: eng page: 109-129 publication: Journal of Supercomputing publication_identifier: issn: - 0920-8542 publisher: Kluwer Academic Publishers status: public title: Instance-Specific Accelerators for Minimum Covering type: journal_article user_id: '398' volume: 26 year: '2003' ... --- _id: '2421' abstract: - lang: eng text: In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load. author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007' apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007 bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007. ieee: R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160. mla: Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007. short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.' date_created: 2018-04-17T15:11:25Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1007/b12007 intvolume: ' 2778' keyword: - Zippy - multi-context - FPGA page: 151-160 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: Springer series_title: Lecture Notes in Computer Science (LNCS) status: public title: Virtualizing Hardware with Multi-Context Reconfigurable Arrays type: conference user_id: '24135' volume: 2778 year: '2003' ... --- _id: '2422' abstract: - lang: eng text: Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs. author: - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.' apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press. bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }' chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003. ieee: R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180. mla: Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80. short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.' date_created: 2018-04-17T15:12:56Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' keyword: - Zippy - co-simulation page: 174-180 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-932415-05-X publisher: CSREA Press status: public title: Co-simulation of a Hybrid Multi-Context Architecture type: conference user_id: '24135' year: '2003' ... --- _id: '13612' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622' apa: Walder, H., & Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press. https://doi.org/10.1109/date.2003.1253622 bibtex: '@inproceedings{Walder_Platzner_2003, title={Online scheduling for block-partitioned reconfigurable devices}, DOI={10.1109/date.2003.1253622}, booktitle={Proceedings Design, Automation and Test in Europe Conference (DATE)}, publisher={IEEE CS Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={290–295} }' chicago: Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” In Proceedings Design, Automation and Test in Europe Conference (DATE), 290–95. IEEE CS Press, 2003. https://doi.org/10.1109/date.2003.1253622. ieee: H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295. mla: Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.” Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622. short: 'H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295.' date_created: 2019-10-04T21:15:31Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/date.2003.1253622 extern: '1' language: - iso: eng page: 290-295 publication: Proceedings Design, Automation and Test in Europe Conference (DATE) publication_identifier: isbn: - '0769518702' publication_status: published publisher: IEEE CS Press status: public title: Online scheduling for block-partitioned reconfigurable devices type: conference user_id: '398' year: '2003' ... --- _id: '13613' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329' apa: 'Walder, H., Steiger, C., & Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press. https://doi.org/10.1109/ipdps.2003.1213329' bibtex: '@inproceedings{Walder_Steiger_Platzner_2003, title={Fast online task placement on FPGAs: free space partitioning and 2D-hashing}, DOI={10.1109/ipdps.2003.1213329}, booktitle={Proceedings International Parallel and Distributed Processing Symposium}, publisher={IEEE CS Press}, author={Walder, Herbert and Steiger, Christoph and Platzner, Marco}, year={2003} }' chicago: 'Walder, Herbert, Christoph Steiger, and Marco Platzner. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press, 2003. https://doi.org/10.1109/ipdps.2003.1213329.' ieee: 'H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.' mla: 'Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.” Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.' short: 'H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.' date_created: 2019-10-04T21:17:07Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/ipdps.2003.1213329 extern: '1' language: - iso: eng publication: Proceedings International Parallel and Distributed Processing Symposium publication_identifier: isbn: - '0769519261' publication_status: published publisher: IEEE CS Press status: public title: 'Fast online task placement on FPGAs: free space partitioning and 2D-hashing' type: conference user_id: '398' year: '2003' ... --- _id: '13614' author: - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.' apa: 'Walder, H., & Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.' bibtex: '@inproceedings{Walder_Platzner_2003, title={Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}, booktitle={Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Walder, Herbert and Platzner, Marco}, year={2003}, pages={284–287} }' chicago: 'Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 284–87. CSREA Press, 2003.' ieee: 'H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.' mla: 'Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.' short: 'H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.' date_created: 2019-10-04T21:20:30Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' extern: '1' language: - iso: eng page: 284-287 publication: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: 'Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations' type: conference user_id: '398' year: '2003' ... --- _id: '13615' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56' apa: 'Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56' bibtex: '@inproceedings{Steiger_Walder_Platzner_2003, place={Berlin, Heidelberg}, title={Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}, DOI={10.1007/978-3-540-45234-8_56}, booktitle={Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2003}, pages={575–584} }' chicago: 'Steiger, Christoph, Herbert Walder, and Marco Platzner. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 575–84. Berlin, Heidelberg: Springer, 2003. https://doi.org/10.1007/978-3-540-45234-8_56.' ieee: C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584. mla: Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56. short: 'C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.' date_created: 2019-10-04T21:20:41Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1007/978-3-540-45234-8_56 extern: '1' language: - iso: eng page: 575-584 place: Berlin, Heidelberg publication: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9783540408222' - '9783540452348' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer status: public title: Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices type: conference user_id: '398' year: '2003' ... --- _id: '13617' author: - first_name: Christoph full_name: Steiger, Christoph last_name: Steiger - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269' apa: Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press. https://doi.org/10.1109/real.2003.1253269 bibtex: '@inproceedings{Steiger_Walder_Platzner_Thiele_2003, title={Online scheduling and placement of real-time tasks to partially reconfigurable devices}, DOI={10.1109/real.2003.1253269}, booktitle={Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}, publisher={IEEE CS Press}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}, year={2003}, pages={252–235} }' chicago: Steiger, Christoph, Herbert Walder, Marco Platzner, and Lothar Thiele. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 252–235. IEEE CS Press, 2003. https://doi.org/10.1109/real.2003.1253269. ieee: C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235. mla: Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.” Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269. short: 'C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.' date_created: 2019-10-04T21:22:53Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/real.2003.1253269 language: - iso: eng page: 252-235 publication: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) publication_identifier: isbn: - '0769520448' publication_status: published publisher: IEEE CS Press status: public title: Online scheduling and placement of real-time tasks to partially reconfigurable devices type: conference user_id: '398' year: '2003' ... --- _id: '2423' abstract: - lang: eng text: 'Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Rolf full_name: Enzler, Rolf last_name: Enzler - first_name: Herbert full_name: Walder, Herbert last_name: Walder - first_name: Jan full_name: Beutel, Jan last_name: Beutel - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250' apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250 bibtex: '@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }' chicago: Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250. ieee: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222. mla: Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250. short: 'C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.' date_created: 2018-04-17T15:13:50Z date_updated: 2022-01-06T06:56:13Z department: - _id: '518' - _id: '78' doi: 10.1109/ISWC.2002.1167250 keyword: - wearable computing page: 215-222 publication: Proc. Int. Symp. on Wearable Computers (ISWC) publication_identifier: isbn: - 0-7695-1816-8 publisher: IEEE Computer Society status: public title: Reconfigurable Hardware in Wearable Computing Nodes type: conference user_id: '24135' year: '2002' ...