--- _id: '16363' author: - first_name: Tim full_name: Hansmeier, Tim id: '49992' last_name: Hansmeier orcid: 0000-0003-1377-3339 - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York, NY, United States: Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968' apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126). New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968' bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}, DOI={10.1145/3377929.3389968}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126} }' chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 125–26. New York, NY, United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3389968.' ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.' mla: 'Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125–26, doi:10.1145/3377929.3389968.' short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.' conference: end_date: 2020-07-12 location: Cancún, Mexico name: The Genetic and Evolutionary Computation Conference (GECCO 2020) start_date: 2020-07-08 date_created: 2020-04-02T10:07:10Z date_updated: 2022-01-06T06:52:49Z department: - _id: '78' doi: 10.1145/3377929.3389968 language: - iso: eng page: 125-126 place: New York, NY, United States project: - _id: '4' name: SFB 901 - Project Area C - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subproject C2 publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation Conference Companion' publication_identifier: isbn: - 978-1-4503-7127-8 publication_status: published publisher: Association for Computing Machinery (ACM) status: public title: Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold type: conference user_id: '477' year: '2020' ... --- _id: '20838' author: - first_name: Achim full_name: Lösch, Achim last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012' apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012' bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012}, booktitle={2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }' chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.' ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.' mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.' short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020.' date_created: 2020-12-23T09:07:11Z date_updated: 2023-01-03T22:07:12Z department: - _id: '78' doi: 10.1109/ipdpsw50202.2020.00012 language: - iso: eng publication: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) publication_identifier: isbn: - '9781728174457' publication_status: published status: public title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes' type: conference user_id: '398' year: '2020' ... --- _id: '21433' abstract: - lang: eng text: "Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands." author: - first_name: Felix P. full_name: Jentzsch, Felix P. last_name: Jentzsch citation: ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture.; 2020. apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020} }' chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020. ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020. mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture. 2020. short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020. date_created: 2021-03-10T07:09:14Z date_updated: 2023-07-09T17:12:52Z department: - _id: '78' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ' - _id: '82' name: 'SFB 901 - T: SFB 901 - Project Area T' - _id: '83' name: 'SFB 901 - T1: SFB 901 -Subproject T1' status: public supervisor: - first_name: Christian full_name: Lienen, Christian id: '60323' last_name: Lienen - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture type: mastersthesis user_id: '398' year: '2020' ... --- _id: '3585' abstract: - lang: eng text: Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003' apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003' bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019): 277–90. https://doi.org/10.1016/j.microrel.2019.04.003.' ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.' mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.' short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability 99 (2019) 277–290. date_created: 2018-07-20T14:08:49Z date_updated: 2022-01-06T06:59:25Z department: - _id: '78' doi: 10.1016/j.microrel.2019.04.003 intvolume: ' 99' keyword: - Approximate Computing - Framework - Pareto Front - Accuracy language: - iso: eng page: 277-290 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Microelectronics Reliability publication_identifier: issn: - 0026-2714 publication_status: published publisher: Elsevier status: public title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation' type: journal_article user_id: '49051' volume: 99 year: '2019' ... --- _id: '16853' abstract: - lang: eng text: State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Matthias full_name: Artmann, Matthias last_name: Artmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).' apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).' bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }' chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.' ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .' mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).' short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.). date_created: 2020-04-25T08:02:07Z date_updated: 2022-01-06T06:52:57Z ddc: - '006' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: witschen date_created: 2020-04-25T08:00:35Z date_updated: 2020-04-25T08:00:35Z file_id: '16854' file_name: AxC19_paper_3.pdf file_size: 152806 relation: main_file success: 1 file_date_updated: 2020-04-25T08:00:35Z has_accepted_license: '1' keyword: - Approximate computing - parameter selection - search space exploration - verification - circuit synthesis language: - iso: eng page: '2' project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Fourth Workshop on Approximate Computing (AxC 2019) publication_status: accepted status: public title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits' type: preprint user_id: '49051' year: '2019' ... --- _id: '10577' abstract: - lang: eng text: "State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution.\r\n\r\nIn this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing." author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Matthias full_name: Artmann, Matthias last_name: Artmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19. New York, NY, USA: ACM; 2019. doi:10.1145/3299874.3317998' apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19. New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998' bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, DOI={10.1145/3299874.3317998}, booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }' chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.' ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.' mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.' short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, New York, NY, USA, 2019.' conference: end_date: 2019-05-11 location: Tysons Corner, VA, USA name: ACM Great Lakes Symposium on VLSI (GLSVLSI) start_date: 2019-05-09 date_created: 2019-07-08T15:13:10Z date_updated: 2022-01-06T06:50:45Z department: - _id: '78' doi: 10.1145/3299874.3317998 keyword: - Approximate computing - design automation - parameter selection - circuit synthesis language: - iso: eng place: New York, NY, USA project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19 publication_identifier: isbn: - '9781450362528' publication_status: published publisher: ACM status: public title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits' type: conference user_id: '49051' year: '2019' ... --- _id: '11950' abstract: - lang: eng text: Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels. author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Georg full_name: Thombansen, Georg last_name: Thombansen - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Florian full_name: Kraus, Florian last_name: Kraus - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004 apa: Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., & Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric signal processing. Journal of Parallel and Distributed Computing, 123, 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004 bibtex: '@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based acceleration of robust high density myoelectric signal processing}, volume={123}, DOI={10.1016/j.jpdc.2018.07.004}, journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier}, author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen, Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89} }' chicago: 'Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen, Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing 123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.' ieee: A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019. mla: Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing, vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004. short: A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner, Journal of Parallel and Distributed Computing 123 (2019) 77–89. date_created: 2019-07-12T13:13:55Z date_updated: 2022-01-06T06:51:13Z department: - _id: '78' doi: 10.1016/j.jpdc.2018.07.004 intvolume: ' 123' keyword: - High density electromyography - FPGA acceleration - Medical signal processing - Pattern recognition - Prosthetics language: - iso: eng page: 77-89 publication: Journal of Parallel and Distributed Computing publication_identifier: issn: - 0743-7315 publication_status: published publisher: Elsevier status: public title: Zynq-based acceleration of robust high density myoelectric signal processing type: journal_article user_id: '398' volume: 123 year: '2019' ... --- _id: '12967' abstract: - lang: eng text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. author: - first_name: Tim full_name: Hansmeier, Tim id: '49992' last_name: Hansmeier orcid: 0000-0003-1377-3339 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Md Jubaer Hossain full_name: Pantho, Md Jubaer Hossain last_name: Pantho - first_name: David full_name: Andrews, David last_name: Andrews citation: ama: Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y apa: Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of Signal Processing Systems, 91(11), 1259–1272. https://doi.org/10.1007/s11265-018-1435-y bibtex: '@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}, volume={91}, DOI={10.1007/s11265-018-1435-y}, number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019}, pages={1259–1272} }' chicago: 'Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019): 1259–72. https://doi.org/10.1007/s11265-018-1435-y.' ieee: T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019. mla: Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems, vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y. short: T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing Systems 91 (2019) 1259–1272. date_created: 2019-08-26T13:41:57Z date_updated: 2022-01-06T06:51:27Z department: - _id: '78' doi: 10.1007/s11265-018-1435-y intvolume: ' 91' issue: '11' language: - iso: eng page: 1259 - 1272 publication: Journal of Signal Processing Systems publication_identifier: issn: - 1939-8018 - 1939-8115 publication_status: published status: public title: An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology type: journal_article user_id: '49992' volume: 91 year: '2019' ... --- _id: '15422' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In: World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer; 2019.' apa: Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In World Congress on Nature and Biologically Inspired Computing (NaBIC). Springer. bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and Biologically Inspired Computing}, title={Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances in Nature and Biologically Inspired Computing} }' chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically Inspired Computing. Springer, 2019. ieee: N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019. mla: Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019. short: 'N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.' date_created: 2019-12-30T13:55:49Z date_updated: 2022-01-06T06:52:25Z department: - _id: '78' language: - iso: eng publication: World Congress on Nature and Biologically Inspired Computing (NaBIC) publisher: Springer series_title: Advances in Nature and Biologically Inspired Computing status: public title: Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor type: conference user_id: '398' year: '2019' ... --- _id: '15883' author: - first_name: Shankar full_name: Kumar Jeyakumar, Shankar last_name: Kumar Jeyakumar citation: ama: Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded Platforms.; 2019. apa: Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine on embedded platforms. bibtex: '@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019} }' chicago: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms, 2019. ieee: S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019. mla: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms. 2019. short: S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded Platforms, 2019. date_created: 2020-02-11T16:43:38Z date_updated: 2022-01-06T06:52:39Z department: - _id: '78' language: - iso: eng status: public supervisor: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi title: Incremental learning with Support Vector Machine on embedded platforms type: mastersthesis user_id: '61186' year: '2019' ... --- _id: '15920' abstract: - lang: eng text: "Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs.\r\nThis master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis." author: - first_name: Monica full_name: Keerthipati, Monica last_name: Keerthipati citation: ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn; 2019. apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn. bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati, Monica}, year={2019} }' chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking, Universität Paderborn, 2019. date_created: 2020-02-17T12:03:40Z date_updated: 2022-01-06T06:52:41Z department: - _id: '78' language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publisher: Universität Paderborn status: public supervisor: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking type: mastersthesis user_id: '477' year: '2019' ... --- _id: '14831' author: - first_name: Nithin S. full_name: Sabu, Nithin S. last_name: Sabu citation: ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University; 2019. apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University. bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019} }' chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019. ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019. mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019. short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets, Paderborn University, 2019. date_created: 2019-11-06T12:06:09Z date_updated: 2022-01-06T06:52:07Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Stefan full_name: Böttcher, Stefan last_name: Böttcher - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema title: FPGA Acceleration of String Search Techniques in Huge Data Sets type: mastersthesis user_id: '3118' year: '2019' ... --- _id: '15946' author: - first_name: Jinay full_name: Mehta, Jinay last_name: Mehta citation: ama: "Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recon\U0010FC03gurable System-on-Chip.; 2019." apa: "Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip." bibtex: "@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip}, author={Mehta, Jinay}, year={2019} }" chicago: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recon\U0010FC03gurable System-on-Chip, 2019." ieee: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip. 2019." mla: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recon\U0010FC03gurable System-on-Chip. 2019." short: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Recon\U0010FC03gurable System-on-Chip, 2019." date_created: 2020-02-20T14:47:12Z date_updated: 2022-01-06T06:52:41Z department: - _id: '78' language: - iso: eng status: public supervisor: - first_name: Marco full_name: Platzner, Marco last_name: Platzner title: "Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip" type: mastersthesis user_id: '398' year: '2019' ... --- _id: '14546' author: - first_name: Tim full_name: Hansmeier, Tim id: '49992' last_name: Hansmeier orcid: 0000-0003-1377-3339 citation: ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn; 2019. apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn. bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }' chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019. ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019. mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019. short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers, Universität Paderborn, 2019. date_created: 2019-11-05T14:32:46Z date_updated: 2022-01-06T06:52:02Z department: - _id: '78' - _id: '34' - _id: '7' language: - iso: eng project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '4' name: SFB 901 - Project Area C - _id: '1' name: SFB 901 publisher: Universität Paderborn status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers type: mastersthesis user_id: '477' year: '2019' ... --- _id: '31067' author: - first_name: Zakarya full_name: Guettatfi, Zakarya last_name: Guettatfi - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Omar full_name: Kermia, Omar last_name: Kermia - first_name: Abdelhakim full_name: Khouas, Abdelhakim last_name: Khouas citation: ama: 'Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027' apa: Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw.2019.00027 bibtex: '@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027}, booktitle={2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner, Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }' chicago: Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.” In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027. ieee: 'Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.' mla: Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027. short: 'Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.' date_created: 2022-05-05T07:42:26Z date_updated: 2022-05-05T07:43:29Z department: - _id: '78' doi: 10.1109/ipdpsw.2019.00027 language: - iso: eng publication: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) publication_status: published publisher: IEEE status: public title: An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware type: conference user_id: '398' year: '2019' ... --- _id: '9913' abstract: - lang: eng text: Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10' apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson, A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing (Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10 bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10}, booktitle={Applied Reconfigurable Computing}, publisher={Springer International Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in Computer Science} }' chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10.' ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.' mla: Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36, doi:10.1007/978-3-030-17227-5_10. short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch, R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International Publishing, Cham, 2019, pp. 127–136.' conference: end_date: 2019-04-11 location: Darmstadt, Germany name: 15th International Symposium on Applied Reconfigurable Computing (ARC 2019) start_date: 2019-04-09 date_created: 2019-05-22T07:36:05Z date_updated: 2023-05-15T08:13:37Z ddc: - '000' department: - _id: '78' doi: 10.1007/978-3-030-17227-5_10 editor: - first_name: Christian full_name: Hochberger, Christian last_name: Hochberger - first_name: Brent full_name: Nelson, Brent last_name: Nelson - first_name: Andreas full_name: Koch, Andreas last_name: Koch - first_name: Roger full_name: Woods, Roger last_name: Woods - first_name: Pedro full_name: Diniz, Pedro last_name: Diniz file: - access_level: closed content_type: application/pdf creator: qazi date_created: 2023-05-11T09:12:33Z date_updated: 2023-05-11T09:12:33Z file_id: '44749' file_name: 978-3-030-17227-5_10.pdf file_size: 661354 relation: main_file success: 1 file_date_updated: 2023-05-11T09:12:33Z has_accepted_license: '1' intvolume: ' 11444' language: - iso: eng main_file_link: - open_access: '1' oa: '1' page: 127-136 place: Cham project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication: Applied Reconfigurable Computing publication_identifier: isbn: - 978-3-030-17227-5 publication_status: published publisher: Springer International Publishing series_title: Lecture Notes in Computer Science status: public title: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan type: conference user_id: '72764' volume: 11444 year: '2019' ... --- _id: '15874' author: - first_name: Christian full_name: Lienen, Christian id: '60323' last_name: Lienen citation: ama: Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn apa: Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn. bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian} }' chicago: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn, n.d. ieee: C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn. mla: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn. short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with ReconOS, Universität Paderborn, n.d. date_created: 2020-02-11T10:22:06Z date_updated: 2023-07-31T11:58:50Z ddc: - '004' department: - _id: '78' file: - access_level: open_access content_type: application/pdf creator: clienen date_created: 2020-07-01T11:46:49Z date_updated: 2021-02-13T16:46:58Z file_id: '17351' file_name: thesis_main.pdf file_size: 5920668 relation: main_file file_date_updated: 2021-02-13T16:46:58Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '83' name: 'SFB 901 - T1: SFB 901 -Subproject T1' - _id: '82' name: 'SFB 901 - T: SFB 901 - Project Area T' - _id: '1' grant_number: '160364472' name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ' publication_status: submitted publisher: Universität Paderborn status: public supervisor: - first_name: Lennart full_name: Clausing, Lennart id: '74287' last_name: Clausing orcid: 0000-0003-3789-6034 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 title: Implementing a Real-time System on a Platform FPGA operated with ReconOS type: mastersthesis user_id: '60323' year: '2019' ... --- _id: '12871' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w apa: Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w bibtex: '@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }' chicago: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w. ieee: 'M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.' mla: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w. short: M. Platzner, C. Plessl, Informatik Spektrum (2019). date_created: 2019-07-22T12:42:44Z date_updated: 2023-09-26T11:45:57Z ddc: - '004' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/s00287-019-01187-w file: - access_level: open_access content_type: application/pdf creator: plessl date_created: 2019-07-22T12:45:02Z date_updated: 2019-07-22T12:45:02Z file_id: '12872' file_name: plessl19_informatik_spektrum.pdf file_size: 248360 relation: main_file file_date_updated: 2019-07-22T12:45:02Z has_accepted_license: '1' language: - iso: ger oa: '1' publication: Informatik Spektrum publication_identifier: issn: - 0170-6012 - 1432-122X publication_status: published quality_controlled: '1' status: public title: FPGAs im Rechenzentrum type: journal_article user_id: '15278' year: '2019' ... --- _id: '52478' author: - first_name: Jinay D full_name: Mehta, Jinay D last_name: Mehta citation: ama: Mehta JD. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip.; 2019. apa: Mehta, J. D. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. bibtex: '@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D}, year={2019} }' chicago: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip, 2019. ieee: J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. 2019. mla: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip. 2019. short: J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip, 2019. date_created: 2024-03-11T15:57:13Z date_updated: 2024-03-11T15:57:39Z department: - _id: '78' language: - iso: eng status: public supervisor: - first_name: Lennart full_name: Clausing, Lennart id: '74287' last_name: Clausing orcid: 0000-0003-3789-6034 title: Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip type: mastersthesis user_id: '74287' year: '2019' ... --- _id: '3362' abstract: - lang: eng text: Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Alex full_name: Wiens, Alex last_name: Wiens - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In: Proceedings of the International Conference on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6' apa: 'Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In Proceedings of the International Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6' bibtex: '@inproceedings{Lösch_Wiens_Platzner_2018, place={Cham}, series={Lecture Notes in Computer Science}, title={Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}, volume={10793}, DOI={10.1007/978-3-319-77610-1_6}, booktitle={Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}, publisher={Springer International Publishing}, author={Lösch, Achim and Wiens, Alex and Platzner, Marco}, year={2018}, pages={73–84}, collection={Lecture Notes in Computer Science} }' chicago: 'Lösch, Achim, Alex Wiens, and Marco Platzner. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.” In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 10793:73–84. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-77610-1_6.' ieee: 'A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes,” in Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793, pp. 73–84.' mla: 'Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.” Proceedings of the International Conference on Architecture of Computing Systems (ARCS), vol. 10793, Springer International Publishing, 2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.' short: 'A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference on Architecture of Computing Systems (ARCS), Springer International Publishing, Cham, 2018, pp. 73–84.' date_created: 2018-06-26T13:47:52Z date_updated: 2022-01-06T06:59:13Z ddc: - '040' department: - _id: '78' doi: 10.1007/978-3-319-77610-1_6 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-06-26T13:58:28Z date_updated: 2018-06-26T13:58:28Z file_id: '3363' file_name: loesch2017_arcs.pdf file_size: 1114026 relation: main_file success: 1 file_date_updated: 2018-06-26T13:58:28Z has_accepted_license: '1' intvolume: ' 10793' page: 73-84 place: Cham project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '4' name: SFB 901 - Project Area C - _id: '1' name: SFB 901 publication: Proceedings of the International Conference on Architecture of Computing Systems (ARCS) publication_identifier: isbn: - '9783319776095' - '9783319776101' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer International Publishing series_title: Lecture Notes in Computer Science status: public title: 'Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes' type: conference user_id: '477' volume: 10793 year: '2018' ...