--- _id: '10631' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Strahinja full_name: Dosen, Strahinja last_name: Dosen - first_name: Andreas full_name: Werner, Andreas last_name: Werner - first_name: Ali full_name: Raies, Ali last_name: Raies - first_name: Dario full_name: Farina, Dario last_name: Farina citation: ama: 'Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016.' apa: Boschmann, A., Dosen, S., Werner, A., Raies, A., & Farina, D. (2016). A novel immersive augmented reality system for prosthesis training and assessment. In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). bibtex: '@inproceedings{Boschmann_Dosen_Werner_Raies_Farina_2016, title={A novel immersive augmented reality system for prosthesis training and assessment}, booktitle={Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)}, author={Boschmann, Alexander and Dosen, Strahinja and Werner, Andreas and Raies, Ali and Farina, Dario}, year={2016} }' chicago: Boschmann, Alexander, Strahinja Dosen, Andreas Werner, Ali Raies, and Dario Farina. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016. ieee: A. Boschmann, S. Dosen, A. Werner, A. Raies, and D. Farina, “A novel immersive augmented reality system for prosthesis training and assessment,” in Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016. mla: Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016. short: 'A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.' date_created: 2019-07-10T11:02:57Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' publication: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI) status: public title: A novel immersive augmented reality system for prosthesis training and assessment type: conference user_id: '3118' year: '2016' ... --- _id: '10661' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62. doi:10.1016/j.tcs.2016.06.029 apa: Graf, T., & Platzner, M. (2016). Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science, 644, 53–62. https://doi.org/10.1016/j.tcs.2016.06.029 bibtex: '@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }' chicago: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science 644 (2016): 53–62. https://doi.org/10.1016/j.tcs.2016.06.029.' ieee: T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016. mla: Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029. short: T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62. date_created: 2019-07-10T11:14:43Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1016/j.tcs.2016.06.029 intvolume: ' 644' language: - iso: eng page: 53-62 publication: Journal Theoretical Computer Science publisher: Elsevier status: public title: Adaptive playouts for online learning of policies during Monte Carlo Tree Search type: journal_article user_id: '3118' volume: 644 year: '2016' ... --- _id: '10695' author: - first_name: Jens full_name: Horstmann, Jens last_name: Horstmann citation: ama: Horstmann J. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University; 2016. apa: Horstmann, J. (2016). Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University. bibtex: '@book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }' chicago: Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016. ieee: J. Horstmann, Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University, 2016. mla: Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016. short: J. Horstmann, Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs, Paderborn University, 2016. date_created: 2019-07-10T11:30:20Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Beschleunigte Simulation elektrischer Stromnetze mit GPUs type: bachelorsthesis user_id: '3118' year: '2016' ... --- _id: '10705' author: - first_name: Chenjie full_name: Ma, Chenjie last_name: Ma - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: J.-Christian full_name: Töbermann, J.-Christian last_name: Töbermann - first_name: Martin full_name: Braun, Martin last_name: Braun citation: ama: Ma C, Kaufmann P, Töbermann J-C, Braun M. Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy. 2016;87((part 2)):946-953. doi:10.1016/j.renene.2015.07.083 apa: Ma, C., Kaufmann, P., Töbermann, J.-C., & Braun, M. (2016). Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy, 87((part 2)), 946–953. https://doi.org/10.1016/j.renene.2015.07.083 bibtex: '@article{Ma_Kaufmann_Töbermann_Braun_2016, title={Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}, volume={87}, DOI={10.1016/j.renene.2015.07.083}, number={(part 2)}, journal={Renewable Energy}, publisher={Elsevier}, author={Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}, year={2016}, pages={946–953} }' chicago: 'Ma, Chenjie, Paul Kaufmann, J.-Christian Töbermann, and Martin Braun. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy 87, no. (part 2) (2016): 946–53. https://doi.org/10.1016/j.renene.2015.07.083.' ieee: C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016. mla: Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.” Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083. short: C. Ma, P. Kaufmann, J.-C. Töbermann, M. Braun, Renewable Energy 87 (2016) 946–953. date_created: 2019-07-10T11:42:59Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1016/j.renene.2015.07.083 intvolume: ' 87' issue: (part 2) language: - iso: eng page: 946-953 publication: Renewable Energy publisher: Elsevier status: public title: Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control type: journal_article user_id: '3118' volume: 87 year: '2016' ... --- _id: '10706' author: - first_name: Vignesh full_name: Makeswaran, Vignesh last_name: Makeswaran citation: ama: Makeswaran V. Operating System Support for Reconfigurable Cache. Paderborn University; 2016. apa: Makeswaran, V. (2016). Operating System Support for Reconfigurable Cache. Paderborn University. bibtex: '@book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }' chicago: Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016. ieee: V. Makeswaran, Operating System Support for Reconfigurable Cache. Paderborn University, 2016. mla: Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016. short: V. Makeswaran, Operating System Support for Reconfigurable Cache, Paderborn University, 2016. date_created: 2019-07-10T11:43:30Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Operating System Support for Reconfigurable Cache type: mastersthesis user_id: '3118' year: '2016' ... --- _id: '10707' author: - first_name: Ishraq full_name: Ibne Ashraf, Ishraq last_name: Ibne Ashraf citation: ama: Ibne Ashraf I. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University; 2016. apa: Ibne Ashraf, I. (2016). Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University. bibtex: '@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }' chicago: Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016. ieee: I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016. mla: Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016. short: I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform, Paderborn University, 2016. date_created: 2019-07-10T11:43:31Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Private/Shared Data Classification and Implementation for a Multi-Softcore Platform type: mastersthesis user_id: '3118' year: '2016' ... --- _id: '10712' author: - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193' apa: 'Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193' bibtex: '@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={10.1109/ReConFig.2016.7857193}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }' chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 1–8. ReConFig, 2016. https://doi.org/10.1109/ReConFig.2016.7857193.' ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on, 2016, pp. 1–8.' mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.' short: 'S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.' date_created: 2019-07-10T11:47:25Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/ReConFig.2016.7857193 language: - iso: eng page: 1-8 publication: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on series_title: ReConFig status: public title: 'Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level' type: conference user_id: '3118' year: '2016' ... --- _id: '10755' author: - first_name: Marco full_name: Schmidt, Marco last_name: Schmidt citation: ama: Schmidt M. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University; 2016. apa: Schmidt, M. (2016). Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University. bibtex: '@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }' chicago: Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016. ieee: M. Schmidt, Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University, 2016. mla: Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016. short: M. Schmidt, Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung, Paderborn University, 2016. date_created: 2019-07-10T12:05:20Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung type: bachelorsthesis user_id: '3118' year: '2016' ... --- _id: '10758' author: - first_name: Giovanni full_name: Squillero, Giovanni last_name: Squillero - first_name: Paolo full_name: Burelli, Paolo last_name: Burelli - first_name: Antonio full_name: M. Mora, Antonio last_name: M. Mora - first_name: Alexandros full_name: Agapitos, Alexandros last_name: Agapitos - first_name: William full_name: S. Bush, William last_name: S. Bush - first_name: Stefano full_name: Cagnoni, Stefano last_name: Cagnoni - first_name: Carlos full_name: Cotta, Carlos last_name: Cotta - first_name: Ivanoe full_name: De Falco, Ivanoe last_name: De Falco - first_name: Antonio full_name: Della Cioppa, Antonio last_name: Della Cioppa - first_name: Federico full_name: Divina, Federico last_name: Divina - first_name: A.E. full_name: Eiben, A.E. last_name: Eiben - first_name: Anna full_name: I. Esparcia-Alc{\'a}zar, Anna last_name: I. Esparcia-Alc{\'a}zar - first_name: Francisco full_name: Fern{\'a}ndez de Vega, Francisco last_name: Fern{\'a}ndez de Vega - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Evert full_name: Haasdijk, Evert last_name: Haasdijk - first_name: J. full_name: Ignacio Hidalgo, J. last_name: Ignacio Hidalgo - first_name: Michael full_name: Kampouridis, Michael last_name: Kampouridis - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Michalis full_name: Mavrovouniotis, Michalis last_name: Mavrovouniotis - first_name: Trung full_name: Thanh Nguyen, Trung last_name: Thanh Nguyen - first_name: Robert full_name: Schaefer, Robert last_name: Schaefer - first_name: Kevin full_name: Sim, Kevin last_name: Sim - first_name: Ernesto full_name: Tarantino, Ernesto last_name: Tarantino - first_name: Neil full_name: Urquhart, Neil last_name: Urquhart - first_name: Mengjie full_name: Zhang (editors), Mengjie last_name: Zhang (editors) citation: ama: Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol 9597. Springer; 2016. apa: Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2016). Applications of Evolutionary Computation - 19th European Conference, EvoApplications (Vol. 9597). Springer. bibtex: '@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2016, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 19th European Conference, EvoApplications}, volume={9597}, publisher={Springer}, author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2016}, collection={Lecture Notes in Computer Science} }' chicago: Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597. Lecture Notes in Computer Science. Springer, 2016. ieee: G. Squillero et al., Applications of Evolutionary Computation - 19th European Conference, EvoApplications, vol. 9597. Springer, 2016. mla: Squillero, Giovanni, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597, Springer, 2016. short: G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\’a}zar, F. Fern{\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 19th European Conference, EvoApplications, Springer, 2016. date_created: 2019-07-10T12:06:36Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' intvolume: ' 9597' publisher: Springer series_title: Lecture Notes in Computer Science status: public title: Applications of Evolutionary Computation - 19th European Conference, EvoApplications type: book user_id: '3118' volume: 9597 year: '2016' ... --- _id: '10766' author: - first_name: Ines full_name: Ghribi, Ines last_name: Ghribi - first_name: Riadh full_name: Ben Abdallah, Riadh last_name: Ben Abdallah - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.' apa: 'Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In Proceedings of the 30th European Simulation and Modelling Conference (ESM).' bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }' chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.' ieee: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.' mla: 'Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.' short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.' date_created: 2019-07-10T12:07:54Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 30th European Simulation and Modelling Conference (ESM) status: public title: 'RCo-Design: New Visual Environment for Reconfigurable Embedded Systems' type: conference user_id: '3118' year: '2016' ... --- _id: '10768' author: - first_name: Ines full_name: Ghribi, Ines last_name: Ghribi - first_name: Riadh full_name: Ben Abdallah, Riadh last_name: Ben Abdallah - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.' apa: Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195). bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={New Co-design Methodology for Real-time Embedded Systems}, booktitle={Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}, pages={185–195} }' chicago: Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Co-Design Methodology for Real-Time Embedded Systems.” In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 185–95, 2016. ieee: I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195. mla: Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95. short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.' date_created: 2019-07-10T12:07:56Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng page: 185-195 publication: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) status: public title: New Co-design Methodology for Real-time Embedded Systems type: conference user_id: '3118' year: '2016' ... --- _id: '10769' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908 apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016). Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908 bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }' chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.' ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016. mla: Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908. short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1. date_created: 2019-07-10T12:08:14Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/TCAD.2016.2547908 extern: '1' issue: '99' language: - iso: eng page: 1-1 publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publisher: IEEE status: public title: Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation type: journal_article user_id: '3118' volume: PP year: '2016' ... --- _id: '10781' author: - first_name: Sven full_name: Hermansen, Sven last_name: Hermansen citation: ama: Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016. apa: Hermansen, S. (2016). Custom Memory Controller for ReconOS. Paderborn University. bibtex: '@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }' chicago: Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016. ieee: S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016. mla: Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016. short: S. Hermansen, Custom Memory Controller for ReconOS, Paderborn University, 2016. date_created: 2019-07-10T12:13:16Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Custom Memory Controller for ReconOS type: bachelorsthesis user_id: '3118' year: '2016' ... --- _id: '12972' abstract: - lang: eng text: Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering. citation: ama: 'Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0' apa: 'Lewis, P. R., Platzner, M., Rinner, B., Tørresen, J., & Yao, X. (Eds.). (2016). Self-aware Computing Systems: An Engineering Approach. Cham: Springer. https://doi.org/10.1007/978-3-319-39675-0' bibtex: '@book{Lewis_Platzner_Rinner_Tørresen_Yao_2016, place={Cham}, title={Self-aware Computing Systems: An Engineering Approach}, DOI={10.1007/978-3-319-39675-0}, publisher={Springer}, year={2016} }' chicago: 'Lewis, Peter R., Marco Platzner, Bernhard Rinner, Jim Tørresen, and Xin Yao, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer, 2016. https://doi.org/10.1007/978-3-319-39675-0.' ieee: 'P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.' mla: 'Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.' short: 'P.R. Lewis, M. Platzner, B. Rinner, J. Tørresen, X. Yao, eds., Self-Aware Computing Systems: An Engineering Approach, Springer, Cham, 2016.' date_created: 2019-08-27T13:39:43Z date_updated: 2022-01-06T06:51:27Z department: - _id: '78' doi: 10.1007/978-3-319-39675-0 editor: - first_name: Peter R. full_name: Lewis, Peter R. last_name: Lewis - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Bernhard full_name: Rinner, Bernhard last_name: Rinner - first_name: Jim full_name: Tørresen, Jim last_name: Tørresen - first_name: Xin full_name: Yao, Xin last_name: Yao language: - iso: eng place: Cham publication_identifier: isbn: - '9783319396743' - '9783319396750' issn: - 1619-7127 publication_status: published publisher: Springer status: public title: 'Self-aware Computing Systems: An Engineering Approach' type: book_editor user_id: '398' year: '2016' ... --- _id: '15873' author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Georg full_name: Thombansen, Georg last_name: Thombansen - first_name: Florian full_name: Kraus, Florian last_name: Kraus - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312' apa: 'Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312' bibtex: '@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={10.1109/reconfig.2015.7393312}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }' chicago: Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312. ieee: A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016. mla: Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312. short: 'A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.' conference: location: Mexiko City, Mexiko name: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) date_created: 2020-02-11T07:48:56Z date_updated: 2022-01-06T06:52:38Z department: - _id: '78' doi: 10.1109/reconfig.2015.7393312 keyword: - Electromyography - Feature extraction - Delays - Hardware Pattern recognition - Prosthetics - High definition video language: - iso: eng publication: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) publication_identifier: isbn: - '9781467394062' publication_status: published publisher: IEEE status: public title: FPGA-based acceleration of high density myoelectric signal processing type: conference user_id: '49051' year: '2016' ... --- _id: '13151' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.' apa: Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games. bibtex: '@inproceedings{Graf_Platzner_2016, title={Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}, booktitle={Computer and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }' chicago: Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” In Computer and Games, 2016. ieee: T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016. mla: Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016. short: 'T. Graf, M. Platzner, in: Computer and Games, 2016.' date_created: 2019-09-09T09:01:09Z date_updated: 2022-01-06T06:51:29Z department: - _id: '78' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Computer and Games status: public title: Using Deep Convolutional Neural Networks in Monte Carlo Tree Search type: conference user_id: '398' year: '2016' ... --- _id: '13152' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.' apa: Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games. bibtex: '@inproceedings{Graf_Platzner_2016, title={Monte-Carlo Simulation Balancing Revisited}, booktitle={IEEE Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2016} }' chicago: Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” In IEEE Computational Intelligence and Games, 2016. ieee: T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016. mla: Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016. short: 'T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016.' date_created: 2019-09-09T09:06:39Z date_updated: 2022-01-06T06:51:29Z department: - _id: '78' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: IEEE Computational Intelligence and Games status: public title: Monte-Carlo Simulation Balancing Revisited type: conference user_id: '398' year: '2016' ... --- _id: '132' abstract: - lang: eng text: Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910' apa: Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910 bibtex: '@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }' chicago: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910. ieee: T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8. mla: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910. short: 'T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.' date_created: 2017-10-17T12:41:17Z date_updated: 2022-01-06T06:51:30Z ddc: - '040' department: - _id: '78' doi: 10.1109/ReCoSoC.2016.7533910 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:02:30Z date_updated: 2018-03-21T13:02:30Z file_id: '1562' file_name: 132-07533910.pdf file_size: 911171 relation: main_file success: 1 file_date_updated: 2018-03-21T13:02:30Z has_accepted_license: '1' language: - iso: eng page: 1--8 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) status: public title: Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware type: conference user_id: '477' year: '2016' ... --- _id: '29' abstract: - lang: eng text: In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers citation: ama: 'Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13' apa: Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13 bibtex: '@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }' chicago: 'Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.' ieee: 'A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.' mla: Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13. short: 'A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.' date_created: 2017-07-26T15:07:06Z date_updated: 2023-09-26T13:25:38Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-26408-0_13 editor: - first_name: Dirk full_name: Koch, Dirk last_name: Koch - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Daniel full_name: Ziener, Daniel last_name: Ziener language: - iso: eng page: 227-244 place: Cham project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: FPGAs for Software Programmers publication_identifier: isbn: - 978-3-319-26406-6 - 978-3-319-26408-0 publication_status: published publisher: Springer International Publishing quality_controlled: '1' status: public title: ReconOS type: book_chapter user_id: '15278' year: '2016' ... --- _id: '156' abstract: - lang: eng text: Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8' apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8 bibtex: '@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }' chicago: 'Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.' ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.' mla: Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8. short: 'A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.' date_created: 2017-10-17T12:41:22Z date_updated: 2023-09-26T13:27:44Z ddc: - '040' department: - _id: '518' - _id: '27' - _id: '78' doi: 10.1007/978-3-319-39675-0_8 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T13:20:32Z date_updated: 2018-11-14T13:20:32Z file_id: '5613' file_name: chapter8.pdf file_size: 833054 relation: main_file success: 1 file_date_updated: 2018-11-14T13:20:32Z has_accepted_license: '1' language: - iso: eng page: 145-165 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Self-aware Computing Systems publisher: Springer International Publishing quality_controlled: '1' series_title: Natural Computing Series (NCS) status: public title: Self-aware Compute Nodes type: book_chapter user_id: '15278' year: '2016' ... --- _id: '168' abstract: - lang: eng text: The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.' apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917. bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }' chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016. ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917. mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17. short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.' date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:27:00Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:41:55Z date_updated: 2018-03-21T12:41:55Z file_id: '1541' file_name: 168-07459438.pdf file_size: 261356 relation: main_file success: 1 file_date_updated: 2018-03-21T12:41:55Z has_accepted_license: '1' language: - iso: eng page: 912-917 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center type: conference user_id: '15278' year: '2016' ... --- _id: '269' abstract: - lang: eng text: Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Sen full_name: Wu, Sen last_name: Wu - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32' apa: Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32 bibtex: '@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }' chicago: Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32. ieee: T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372. mla: Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32. short: 'T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.' date_created: 2017-10-17T12:41:44Z date_updated: 2022-01-06T06:57:30Z ddc: - '040' department: - _id: '78' doi: 10.1007/978-3-319-16214-0_32 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T09:32:42Z date_updated: 2018-03-21T09:32:42Z file_id: '1477' file_name: 269-paper_53.pdf file_size: 344309 relation: main_file success: 1 file_date_updated: 2018-03-21T09:32:42Z has_accepted_license: '1' language: - iso: eng page: 365--372 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the International Symposium in Reconfigurable Computing (ARC) series_title: LNCS status: public title: On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach type: conference user_id: '477' year: '2015' ... --- _id: '3364' author: - first_name: Christoph full_name: Knorr, Christoph last_name: Knorr citation: ama: Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015. apa: Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn. bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }' chicago: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015. ieee: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015. mla: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015. short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten, Universität Paderborn, 2015. date_created: 2018-06-26T14:06:07Z date_updated: 2022-01-06T06:59:13Z department: - _id: '78' language: - iso: ger project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C publisher: Universität Paderborn status: public supervisor: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten type: bachelorsthesis user_id: '477' year: '2015' ... --- _id: '1772' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Xin full_name: Yao, Xin last_name: Yao citation: ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205 apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205 bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }' chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.' ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015. mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205. short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20. date_created: 2018-03-23T14:06:12Z date_updated: 2022-01-06T06:53:19Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MC.2015.205 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:47:45Z date_updated: 2018-11-02T15:47:45Z file_id: '5313' file_name: 07163237.pdf file_size: 5605009 relation: main_file success: 1 file_date_updated: 2018-11-02T15:47:45Z has_accepted_license: '1' intvolume: ' 48' issue: '7' keyword: - self-awareness - self-expression language: - iso: eng page: 18-20 project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: IEEE Computer publisher: IEEE Computer Society status: public title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction type: journal_article user_id: '16153' volume: 48 year: '2015' ... --- _id: '10615' author: - first_name: Abdullah Fathi full_name: Ahmed, Abdullah Fathi last_name: Ahmed citation: ama: Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015. apa: Ahmed, A. F. (2015). Self-Optimizing Organic Cache. Paderborn University. bibtex: '@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }' chicago: Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015. ieee: A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015. mla: Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015. short: A.F. Ahmed, Self-Optimizing Organic Cache, Paderborn University, 2015. date_created: 2019-07-10T09:25:13Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Self-Optimizing Organic Cache type: mastersthesis user_id: '3118' year: '2015' ... --- _id: '10624' abstract: - lang: eng text: "The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies." author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel citation: ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.' apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.' bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }' chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015. short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015. date_created: 2019-07-10T09:36:58Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' - _id: '27' - _id: '518' language: - iso: eng page: '183' place: Berlin project: - _id: '30' grant_number: 01|H11004 name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication_identifier: isbn: - 978-3-8325-4155-2 publisher: Logos Verlag Berlin GmbH status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing type: dissertation user_id: '3118' year: '2015' ... --- _id: '10668' author: - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann citation: ama: Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015. apa: Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University. bibtex: '@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }' chicago: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015. ieee: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015. mla: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015. short: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn University, 2015. date_created: 2019-07-10T11:15:13Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Evolution of Heat Flow Prediction Models for FPGA Devices type: mastersthesis user_id: '3118' year: '2015' ... --- _id: '10671' author: - first_name: Christian full_name: Haupt, Christian last_name: Haupt citation: ama: Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015. apa: Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University. bibtex: '@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }' chicago: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015. ieee: C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015. mla: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015. short: C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn University, 2015. date_created: 2019-07-10T11:17:57Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann title: Computer Vision basierte Klassifikation von HD EMG Signalen type: mastersthesis user_id: '3118' year: '2015' ... --- _id: '10673' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Abdullah Fathi full_name: Ahmed, Abdullah Fathi last_name: Ahmed - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178' apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178 bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }' chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178. ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7. mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178. short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.' date_created: 2019-07-10T11:18:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/AHS.2015.7231178 keyword: - cache storage - field programmable gate arrays - multiprocessing systems - parallel architectures - reconfigurable architectures - FPGA - dynamic reconfiguration - evolvable cache mapping - many-core architecture - memory-to-cache address mapping function - microarchitectural optimization - multicore architecture - nature-inspired optimization - parallelization degrees - processor - reconfigurable cache mapping - reconfigurable computing - Field programmable gate arrays - Software - Tuning language: - iso: eng page: 1-7 project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) status: public title: Microarchitectural optimization by means of reconfigurable and evolvable cache mappings type: conference user_id: '3118' year: '2015' ... --- _id: '10693' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Cong full_name: Shen, Cong last_name: Shen citation: ama: 'Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.' apa: Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM. bibtex: '@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann, Paul and Shen, Cong}, year={2015}, pages={409–416} }' chicago: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic and Evolutionary Computation (GECCO), 409–16. ACM, 2015. ieee: P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416. mla: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16. short: 'P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.' date_created: 2019-07-10T11:30:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' page: 409-416 publication: Genetic and Evolutionary Computation (GECCO) publisher: ACM status: public title: Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing type: conference user_id: '3118' year: '2015' ... --- _id: '10711' author: - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153' apa: Meisner, S., & Platzner, M. (2015). Comparison of thread signatures for error detection in hybrid multi-cores. In Field Programmable Technology (FPT), 2015 International Conference on (pp. 212–215). https://doi.org/10.1109/FPT.2015.7393153 bibtex: '@inproceedings{Meisner_Platzner_2015, series={FPT}, title={Comparison of thread signatures for error detection in hybrid multi-cores}, DOI={10.1109/FPT.2015.7393153}, booktitle={Field Programmable Technology (FPT), 2015 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2015}, pages={212–215}, collection={FPT} }' chicago: Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” In Field Programmable Technology (FPT), 2015 International Conference On, 212–15. FPT, 2015. https://doi.org/10.1109/FPT.2015.7393153. ieee: S. Meisner and M. Platzner, “Comparison of thread signatures for error detection in hybrid multi-cores,” in Field Programmable Technology (FPT), 2015 International Conference on, 2015, pp. 212–215. mla: Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.” Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153. short: 'S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215.' date_created: 2019-07-10T11:47:24Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/FPT.2015.7393153 language: - iso: eng page: 212-215 publication: Field Programmable Technology (FPT), 2015 International Conference on series_title: FPT status: public title: Comparison of thread signatures for error detection in hybrid multi-cores type: conference user_id: '3118' year: '2015' ... --- _id: '10714' author: - first_name: Roland full_name: Meißner, Roland last_name: Meißner citation: ama: Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015. apa: Meißner, R. (2015). Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn. bibtex: '@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }' chicago: Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015. ieee: R. Meißner, Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn, 2015. mla: Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015. short: R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs, Universität Paderborn, 2015. date_created: 2019-07-10T11:48:25Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publisher: Universität Paderborn status: public supervisor: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema title: Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs type: bachelorsthesis user_id: '477' year: '2015' ... --- _id: '10726' author: - first_name: Thorbjörn full_name: Posewsky, Thorbjörn last_name: Posewsky citation: ama: Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015. apa: Posewsky, T. (2015). Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University. bibtex: '@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }' chicago: Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015. ieee: T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015. mla: Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015. short: T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform, Paderborn University, 2015. date_created: 2019-07-10T11:54:44Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Acceleration of Artificial Neural Networks on a Zynq Platform type: mastersthesis user_id: '3118' year: '2015' ... --- _id: '10757' author: - first_name: Antonio full_name: M. Mora, Antonio last_name: M. Mora - first_name: Giovanni full_name: Squillero, Giovanni last_name: Squillero - first_name: Alexandros full_name: Agapitos, Alexandros last_name: Agapitos - first_name: Paolo full_name: Burelli, Paolo last_name: Burelli - first_name: William full_name: S. Bush, William last_name: S. Bush - first_name: Stefano full_name: Cagnoni, Stefano last_name: Cagnoni - first_name: Carlos full_name: Cotta, Carlos last_name: Cotta - first_name: Ivanoe full_name: De Falco, Ivanoe last_name: De Falco - first_name: Antonio full_name: Della Cioppa, Antonio last_name: Della Cioppa - first_name: Federico full_name: Divina, Federico last_name: Divina - first_name: A.E. full_name: Eiben, A.E. last_name: Eiben - first_name: Anna full_name: I. Esparcia-Alc{\'a}zar, Anna last_name: I. Esparcia-Alc{\'a}zar - first_name: Francisco full_name: Fern{\'a}ndez de Vega, Francisco last_name: Fern{\'a}ndez de Vega - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Evert full_name: Haasdijk, Evert last_name: Haasdijk - first_name: J. full_name: Ignacio Hidalgo, J. last_name: Ignacio Hidalgo - first_name: Michael full_name: Kampouridis, Michael last_name: Kampouridis - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Michalis full_name: Mavrovouniotis, Michalis last_name: Mavrovouniotis - first_name: Trung full_name: Thanh Nguyen, Trung last_name: Thanh Nguyen - first_name: Robert full_name: Schaefer, Robert last_name: Schaefer - first_name: Kevin full_name: Sim, Kevin last_name: Sim - first_name: Ernesto full_name: Tarantino, Ernesto last_name: Tarantino - first_name: Neil full_name: Urquhart, Neil last_name: Urquhart - first_name: Mengjie full_name: Zhang (editors), Mengjie last_name: Zhang (editors) citation: ama: 'M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.' apa: 'M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni, S., … Zhang (editors), M. (2015). Applications of Evolutionary Computation - 18th European Conference, EvoApplications (Vol. 9028). Copenhagen, Denmark: Springer.' bibtex: '@book{M. Mora_Squillero_Agapitos_Burelli_S. Bush_Cagnoni_Cotta_De Falco_Della Cioppa_Divina_et al._2015, place={Copenhagen, Denmark}, series={Lecture Notes in Computer Science}, title={Applications of Evolutionary Computation - 18th European Conference, EvoApplications}, volume={9028}, publisher={Springer}, author={M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2015}, collection={Lecture Notes in Computer Science} }' chicago: 'M. Mora, Antonio, Giovanni Squillero, Alexandros Agapitos, Paolo Burelli, William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028. Lecture Notes in Computer Science. Copenhagen, Denmark: Springer, 2015.' ieee: 'A. M. Mora et al., Applications of Evolutionary Computation - 18th European Conference, EvoApplications, vol. 9028. Copenhagen, Denmark: Springer, 2015.' mla: M. Mora, Antonio, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028, Springer, 2015. short: A. M. Mora, G. Squillero, A. Agapitos, P. Burelli, W. S. Bush, S. Cagnoni, C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\’a}zar, F. Fern{\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis, P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino, N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 18th European Conference, EvoApplications, Springer, Copenhagen, Denmark, 2015. date_created: 2019-07-10T12:06:35Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' intvolume: ' 9028' place: Copenhagen, Denmark publisher: Springer series_title: Lecture Notes in Computer Science status: public title: Applications of Evolutionary Computation - 18th European Conference, EvoApplications type: book user_id: '3118' volume: 9028 year: '2015' ... --- _id: '10765' author: - first_name: Philip full_name: H.W. Leong, Philip last_name: H.W. Leong - first_name: Hideharu full_name: Amano, Hideharu last_name: Amano - first_name: Jason full_name: Anderson, Jason last_name: Anderson - first_name: Koen full_name: Bertels, Koen last_name: Bertels - first_name: Jo\~ao full_name: M.P. Cardoso, Jo\~ao last_name: M.P. Cardoso - first_name: Oliver full_name: Diessel, Oliver last_name: Diessel - first_name: Guy full_name: Gogniat, Guy last_name: Gogniat - first_name: Mike full_name: Hutton, Mike last_name: Hutton - first_name: JunKyu full_name: Lee, JunKyu last_name: Lee - first_name: Wayne full_name: Luk, Wayne last_name: Luk - first_name: Patrick full_name: Lysaght, Patrick last_name: Lysaght - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Viktor full_name: K. Prasanna, Viktor last_name: K. Prasanna - first_name: Tero full_name: Rissa, Tero last_name: Rissa - first_name: Cristina full_name: Silvano, Cristina last_name: Silvano - first_name: Hayden full_name: So, Hayden last_name: So - first_name: Yu full_name: Wang, Yu last_name: Wang citation: ama: 'H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747' apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1–3). Imperial College. https://doi.org/10.1109/FPL.2015.7293747 bibtex: '@inproceedings{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2015, title={Significant papers from the first 25 years of the FPL conference}, DOI={10.1109/FPL.2015.7293747}, booktitle={Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2015}, pages={1–3} }' chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~ao M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “Significant Papers from the First 25 Years of the FPL Conference.” In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 1–3. Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293747. ieee: P. H.W. Leong et al., “Significant papers from the first 25 years of the FPL conference,” in Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–3. mla: H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.” Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3, doi:10.1109/FPL.2015.7293747. short: 'P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3.' date_created: 2019-07-10T12:07:53Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/FPL.2015.7293747 language: - iso: eng page: 1-3 publication: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) publisher: Imperial College status: public title: Significant papers from the first 25 years of the FPL conference type: conference user_id: '3118' year: '2015' ... --- _id: '10767' author: - first_name: Ines full_name: Ghribi, Ines last_name: Ghribi - first_name: Riadh full_name: Ben Abdallah, Riadh last_name: Ben Abdallah - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.' apa: Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In Proceedings of the 29th European Simulation and Modelling Conference (ESM). bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2015, title={New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}, booktitle={Proceedings of the 29th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2015} }' chicago: Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” In Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015. ieee: I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,” in Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015. mla: Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015. short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.' date_created: 2019-07-10T12:07:55Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 29th European Simulation and Modelling Conference (ESM) status: public title: New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software type: conference user_id: '3118' year: '2015' ... --- _id: '10770' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359 apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126. https://doi.org/10.1109/TNANO.2015.2482359 bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }' chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology 14, no. 6 (2015): 1117–26. https://doi.org/10.1109/TNANO.2015.2482359.' ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015. mla: Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359. short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126. date_created: 2019-07-10T12:08:15Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/TNANO.2015.2482359 extern: '1' intvolume: ' 14' issue: '6' language: - iso: eng page: 1117-1126 publication: IEEE Transactions on Nanotechnology publisher: IEEE status: public title: From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires type: journal_article user_id: '3118' volume: 14 year: '2015' ... --- _id: '10771' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Jian full_name: Zhang, Jian last_name: Zhang - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli - first_name: Eduardo full_name: Sanchez, Eduardo last_name: Sanchez - first_name: Matteo Sonza full_name: Reorda, Matteo Sonza last_name: Reorda citation: ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13' apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13 bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015, title={On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}, DOI={10.1109/ISVLSI.2015.13}, booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}, year={2015}, pages={491–496} }' chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” In 2015 IEEE Computer Society Annual Symposium on VLSI, 491–96. IEEE, 2015. https://doi.org/10.1109/ISVLSI.2015.13. ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 491–496. mla: Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.” 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13. short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496.' date_created: 2019-07-10T12:08:16Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/ISVLSI.2015.13 extern: '1' language: - iso: eng page: 491-496 publication: 2015 IEEE Computer Society Annual Symposium on VLSI publisher: IEEE status: public title: On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors type: conference user_id: '3118' year: '2015' ... --- _id: '10772' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Pierre-Emmanuel full_name: Gaillardon, Pierre-Emmanuel last_name: Gaillardon - first_name: Giovanni full_name: De Micheli, Giovanni last_name: De Micheli citation: ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428' apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition (pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428 bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault modeling in controllable polarity silicon nanowire circuits}, DOI={10.7873/DATE.2015.0428}, booktitle={Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={453–458} }' chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” In Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, 453–58. EDA Consortium, 2015. https://doi.org/10.7873/DATE.2015.0428. ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling in controllable polarity silicon nanowire circuits,” in Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, 2015, pp. 453–458. mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.” Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453–58, doi:10.7873/DATE.2015.0428. short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453–458.' date_created: 2019-07-10T12:08:17Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.7873/DATE.2015.0428 extern: '1' language: - iso: eng page: 453-458 publication: Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition publisher: EDA Consortium status: public title: Fault modeling in controllable polarity silicon nanowire circuits type: conference user_id: '3118' year: '2015' ... --- _id: '10779' author: - first_name: Zakarya full_name: Guettatfi, Zakarya last_name: Guettatfi - first_name: Omar full_name: Kermia, Omar last_name: Kermia - first_name: Abdelhakim full_name: Khouas, Abdelhakim last_name: Khouas citation: ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994' apa: Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994 bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }' chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293994. ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015. mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994. short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.' date_created: 2019-07-10T12:11:36Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/FPL.2015.7293994 extern: '1' keyword: - embedded systems - field programmable gate arrays - operating systems (computers) - scheduling - μC/OS-II - FPGAs - OS foundation - SafeRTOS - Xenomai - chip utilization ration - complex time constraints - embedded systems - hard real-time hardware task allocation - hard real-time hardware task scheduling - hardware-software real-time operating systems - partially reconfigurable field-programmable gate arrays - resource constraints - safety-critical RTOS - Field programmable gate arrays - Hardware - Job shop scheduling - Real-time systems - Shape - Software language: - iso: eng publication: 25th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: issn: - 1946-147X publisher: Imperial College status: public title: Over effective hard real-time hardware tasks scheduling and allocation type: conference user_id: '398' year: '2015' ... --- _id: '13153' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1' apa: 'Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing. https://doi.org/10.1007/978-3-319-27992-3_1' bibtex: '@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}, DOI={10.1007/978-3-319-27992-3_1}, booktitle={Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015}, pages={1–11} }' chicago: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 1–11. Springer International Publishing, 2015. https://doi.org/10.1007/978-3-319-27992-3_1.' ieee: 'T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 2015, pp. 1–11.' mla: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.” Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.' short: 'T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11.' date_created: 2019-09-09T09:07:46Z date_updated: 2022-01-06T06:51:29Z department: - _id: '78' doi: 10.1007/978-3-319-27992-3_1 language: - iso: eng page: 1-11 project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 'Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers' publisher: Springer International Publishing status: public title: Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning type: conference user_id: '40778' year: '2015' ... --- _id: '296' abstract: - lang: eng text: FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. article_number: '859425' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425 apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425 bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.' mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425. short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015). date_created: 2017-10-17T12:41:49Z date_updated: 2023-09-26T13:29:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2015/859425 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:47:56Z date_updated: 2018-03-20T07:47:56Z file_id: '1444' file_name: 296-859425.pdf file_size: 2993898 relation: main_file success: 1 file_date_updated: 2018-03-20T07:47:56Z has_accepted_license: '1' intvolume: ' 2015' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: International Journal of Reconfigurable Computing (IJRC) publisher: Hindawi quality_controlled: '1' status: public title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study type: journal_article user_id: '15278' volume: 2015 year: '2015' ... --- _id: '303' abstract: - lang: eng text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.' apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }' chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015. mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.' date_created: 2017-10-17T12:41:51Z date_updated: 2023-09-26T13:29:59Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' external_id: arxiv: - '1412.3906' file: - access_level: open_access content_type: application/pdf creator: florida date_created: 2018-03-20T07:46:46Z date_updated: 2019-08-01T09:10:44Z file_id: '1442' file_name: 303-plessl15_adapt.pdf file_size: 1176620 relation: main_file file_date_updated: 2019-08-01T09:10:44Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) quality_controlled: '1' status: public title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores type: conference user_id: '15278' year: '2015' ... --- _id: '1773' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: J. full_name: T. Anderson, J. last_name: T. Anderson - first_name: A. full_name: Borga, A. last_name: Borga - first_name: H. full_name: Boterenbrood, H. last_name: Boterenbrood - first_name: H. full_name: Chen, H. last_name: Chen - first_name: K. full_name: Chen, K. last_name: Chen - first_name: G. full_name: Drake, G. last_name: Drake - first_name: D. full_name: Francis, D. last_name: Francis - first_name: B. full_name: Gorini, B. last_name: Gorini - first_name: F. full_name: Lanni, F. last_name: Lanni - first_name: Giovanna full_name: Lehmann-Miotto, Giovanna last_name: Lehmann-Miotto - first_name: L. full_name: Levinson, L. last_name: Levinson - first_name: J. full_name: Narevicius, J. last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A. full_name: Roich, A. last_name: Roich - first_name: S. full_name: Ryu, S. last_name: Ryu - first_name: F. full_name: P. Schreuder, F. last_name: P. Schreuder - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J. full_name: Vermeulen, J. last_name: Vermeulen - first_name: J. full_name: Zhang, J. last_name: Zhang citation: ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824' apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824 bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }' chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824. ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.' mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824. short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.' date_created: 2018-03-23T14:09:33Z date_updated: 2023-09-26T13:31:01Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/2675743.2771824 language: - iso: eng publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) publisher: ACM quality_controlled: '1' status: public title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm type: conference user_id: '15278' year: '2015' ... --- _id: '1768' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Peter J. full_name: Schreier, Peter J. last_name: Schreier citation: ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z' apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z' bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }' chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.' ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.' mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.' short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399. date_created: 2018-03-23T13:58:34Z date_updated: 2023-09-26T13:30:22Z department: - _id: '27' - _id: '518' - _id: '263' - _id: '78' doi: 10.1007/s00287-015-0911-z issue: '5' keyword: - approximate computing - survey language: - iso: eng page: 396-399 publication: Informatik Spektrum publisher: Springer quality_controlled: '1' status: public title: 'Aktuelles Schlagwort: Approximate Computing' type: journal_article user_id: '15278' year: '2015' ... --- _id: '238' abstract: - lang: eng text: In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124' apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124 bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }' chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124. ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.' mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124. short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.' date_created: 2017-10-17T12:41:38Z date_updated: 2023-09-26T13:31:44Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.7873/DATE.2015.1124 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T10:29:49Z date_updated: 2018-03-21T10:29:49Z file_id: '1500' file_name: 238-plessl15_date.pdf file_size: 380552 relation: main_file success: 1 file_date_updated: 2018-03-21T10:29:49Z has_accepted_license: '1' language: - iso: eng page: 1078-1083 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Transparent offloading of computational hotspots from binary code to Xeon Phi type: conference user_id: '15278' year: '2015' ... --- _id: '347' abstract: - lang: eng text: Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead. author: - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30' apa: 'Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio, J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer. https://doi.org/10.1007/978-3-319-05960-0_30' bibtex: '@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}, DOI={10.1007/978-3-319-05960-0_30}, booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner, Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture Notes in Computer Science} }' chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels, 283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.' ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.' mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.' short: 'S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.' date_created: 2017-10-17T12:41:59Z date_updated: 2022-01-06T06:59:18Z ddc: - '040' department: - _id: '78' doi: 10.1007/978-3-319-05960-0_30 editor: - first_name: Diana full_name: Goehringer, Diana last_name: Goehringer - first_name: MarcoDomenico full_name: Santambrogio, MarcoDomenico last_name: Santambrogio - first_name: JoãoM.P. full_name: Cardoso, JoãoM.P. last_name: Cardoso - first_name: Koen full_name: Bertels, Koen last_name: Bertels file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:26:16Z date_updated: 2018-03-20T07:26:16Z file_id: '1417' file_name: 347-meisner13_xx_SFB1__1_.pdf file_size: 1168877 relation: main_file success: 1 file_date_updated: 2018-03-20T07:26:16Z has_accepted_license: '1' language: - iso: eng page: 283-290 project: - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) publisher: Springer series_title: Lecture Notes in Computer Science status: public title: 'Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection' type: conference user_id: '398' year: '2014' ... --- _id: '1782' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2' apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2' bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }' chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.' ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25. mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2. short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.' date_created: 2018-03-26T13:50:37Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-319-09165-5_2 issue: '8427' page: 14-25 place: Switzerland publication: Proc. Conf. on Computers and Games (CG) publisher: Springer series_title: Lecture Notes in Computer Science status: public title: On Semeai Detection in Monte-Carlo Go type: conference user_id: '24135' year: '2014' ... --- _id: '399' abstract: - lang: eng text: Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771' apa: 'Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174). https://doi.org/10.1109/FPT.2014.7082771' bibtex: '@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}, year={2014}, pages={167–174} }' chicago: 'Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771.' ieee: 'T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.' mla: 'Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.' short: 'T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.' date_created: 2017-10-17T12:42:09Z date_updated: 2022-01-06T07:00:05Z ddc: - '040' department: - _id: '78' doi: 10.1109/FPT.2014.7082771 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T06:57:44Z date_updated: 2018-03-20T06:57:44Z file_id: '1380' file_name: 399-wiersema14_fpt_IEEE_approved.pdf file_size: 404328 relation: main_file success: 1 file_date_updated: 2018-03-20T06:57:44Z has_accepted_license: '1' language: - iso: eng page: 167-174 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) status: public title: 'Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring' type: conference user_id: '477' year: '2014' ... --- _id: '408' abstract: - lang: eng text: Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques. author: - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19' apa: Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322). https://doi.org/10.1007/978-3-319-10181-1_19 bibtex: '@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19}, booktitle={Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors}, year={2014}, pages={307–322}, collection={LNCS} }' chicago: Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim. “Integrating Software and Hardware Verification.” In Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19. ieee: M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in Proceedings of the 11th International Conference on Integrated Formal Methods (iFM), 2014, pp. 307–322. mla: Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.” Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19. short: 'M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.' date_created: 2017-10-17T12:42:11Z date_updated: 2022-01-06T07:00:14Z ddc: - '040' department: - _id: '77' - _id: '78' doi: 10.1007/978-3-319-10181-1_19 editor: - first_name: Elvira full_name: Albert, Elvira last_name: Albert - first_name: Emil full_name: Sekerinski, Emil last_name: Sekerinski file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:35:28Z date_updated: 2018-03-16T11:35:28Z file_id: '1364' file_name: 408-jakobs14_ifm.pdf file_size: 561325 relation: main_file success: 1 file_date_updated: 2018-03-16T11:35:28Z has_accepted_license: '1' language: - iso: eng page: 307-322 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) series_title: LNCS status: public title: Integrating Software and Hardware Verification type: conference user_id: '477' year: '2014' ...