---
_id: '13153'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient
Reinforcement Learning. In: Advances in Computer Games: 14th International
Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected
Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1'
apa: 'Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree
Search with Policy-Gradient Reinforcement Learning. In Advances in Computer
Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July
1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing.
https://doi.org/10.1007/978-3-319-27992-3_1'
bibtex: '@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo
Tree Search with Policy-Gradient Reinforcement Learning}, DOI={10.1007/978-3-319-27992-3_1},
booktitle={Advances in Computer Games: 14th International Conference, ACG 2015,
Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer
International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015},
pages={1–11} }'
chicago: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree
Search with Policy-Gradient Reinforcement Learning.” In Advances in Computer
Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July
1-3, 2015, Revised Selected Papers, 1–11. Springer International Publishing,
2015. https://doi.org/10.1007/978-3-319-27992-3_1.'
ieee: 'T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with
Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th
International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised
Selected Papers, 2015, pp. 1–11.'
mla: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search
with Policy-Gradient Reinforcement Learning.” Advances in Computer Games: 14th
International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised
Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.'
short: 'T. Graf, M. Platzner, in: Advances in Computer Games: 14th International
Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected
Papers, Springer International Publishing, 2015, pp. 1–11.'
date_created: 2019-09-09T09:07:46Z
date_updated: 2022-01-06T06:51:29Z
department:
- _id: '78'
doi: 10.1007/978-3-319-27992-3_1
language:
- iso: eng
page: 1-11
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 'Advances in Computer Games: 14th International Conference, ACG 2015,
Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers'
publisher: Springer International Publishing
status: public
title: Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement
Learning
type: conference
user_id: '40778'
year: '2015'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '303'
abstract:
- lang: eng
text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use
on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling
existentsoftware to automatically utilize accelerators at runtime. BAARis based
on the LLVM Compiler Infrastructure and has aclient-server architecture. The client
runs the program to beaccelerated in an environment which allows program analysisand
profiling. Program parts which are identified as suitable forthe available accelerator
are exported and sent to the server.The server optimizes these program parts for
the acceleratorand provides RPC execution for the client. The client transformsits
program to utilize accelerated execution on the server foroffloaded program parts.
We evaluate our work with a proofof-concept implementation of BAAR that uses an
Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading,
parallelization and vectorization of suitable programparts. The practicality of
BAAR for real-world examples is shownbased on a study of stencil codes. Our results
show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints
over the same code compiled with the Intel Compiler atoptimization level O2 and
running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand
evaluation we outline future directions of research, e.g.,offloading more fine-granular
program parts than functions, amore sophisticated communication mechanism or introducing
onstack-replacement.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on
Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning
Computing Systems (ADAPT). ; 2015.'
apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores. Proceedings of the 5th International Workshop on
Adaptive Self-Tuning Computing Systems (ADAPT).
bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International
Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen,
Marvin and Plessl, Christian}, year={2015} }'
chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores.” In Proceedings of the 5th International
Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration
on Many-Cores,” 2015.
mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores.” Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.'
date_created: 2017-10-17T12:41:51Z
date_updated: 2023-09-26T13:29:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
external_id:
arxiv:
- '1412.3906'
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:46:46Z
date_updated: 2019-08-01T09:10:44Z
file_id: '1442'
file_name: 303-plessl15_adapt.pdf
file_size: 1176620
relation: main_file
file_date_updated: 2019-08-01T09:10:44Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning
Computing Systems (ADAPT)
quality_controlled: '1'
status: public
title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1773'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: J.
full_name: T. Anderson, J.
last_name: T. Anderson
- first_name: A.
full_name: Borga, A.
last_name: Borga
- first_name: H.
full_name: Boterenbrood, H.
last_name: Boterenbrood
- first_name: H.
full_name: Chen, H.
last_name: Chen
- first_name: K.
full_name: Chen, K.
last_name: Chen
- first_name: G.
full_name: Drake, G.
last_name: Drake
- first_name: D.
full_name: Francis, D.
last_name: Francis
- first_name: B.
full_name: Gorini, B.
last_name: Gorini
- first_name: F.
full_name: Lanni, F.
last_name: Lanni
- first_name: Giovanna
full_name: Lehmann-Miotto, Giovanna
last_name: Lehmann-Miotto
- first_name: L.
full_name: Levinson, L.
last_name: Levinson
- first_name: J.
full_name: Narevicius, J.
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A.
full_name: Roich, A.
last_name: Roich
- first_name: S.
full_name: Ryu, S.
last_name: Ryu
- first_name: F.
full_name: P. Schreuder, F.
last_name: P. Schreuder
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J.
full_name: Vermeulen, J.
last_name: Vermeulen
- first_name: J.
full_name: Zhang, J.
last_name: Zhang
citation:
ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015.
doi:10.1145/2675743.2771824'
apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen,
K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson,
L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli,
W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et
al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project
– Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824},
booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM},
author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H.
and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni,
F. and et al.}, year={2015} }'
chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K.
Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX
Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.
ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in
the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”
2015, doi: 10.1145/2675743.2771824.'
mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS
FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen,
G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J.
Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen,
J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM,
2015.'
date_created: 2018-03-23T14:09:33Z
date_updated: 2023-09-26T13:31:01Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/2675743.2771824
language:
- iso: eng
publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)
publisher: ACM
quality_controlled: '1'
status: public
title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis
and Optimization of a Memory-Bounded Algorithm
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1768'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Peter J.
full_name: Schreier, Peter J.
last_name: Schreier
citation:
ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing.
Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z'
apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort:
Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z'
bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate
Computing}, DOI={10.1007/s00287-015-0911-z},
number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl,
Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399}
}'
chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort:
Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.'
ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate
Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.'
mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik
Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.'
short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.
date_created: 2018-03-23T13:58:34Z
date_updated: 2023-09-26T13:30:22Z
department:
- _id: '27'
- _id: '518'
- _id: '263'
- _id: '78'
doi: 10.1007/s00287-015-0911-z
issue: '5'
keyword:
- approximate computing
- survey
language:
- iso: eng
page: 396-399
publication: Informatik Spektrum
publisher: Springer
quality_controlled: '1'
status: public
title: 'Aktuelles Schlagwort: Approximate Computing'
type: journal_article
user_id: '15278'
year: '2015'
...
---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '347'
abstract:
- lang: eng
text: Dynamic thread duplication is a known redundancy technique for multi-cores.
The approach duplicates a thread under observation for some time period and compares
the signatures of the two threads to detect errors. Hybrid multi-cores, typically
implemented on platform FPGAs, enable the unique option of running the thread
under observation and its copy in different modalities, i.e., software and hardware.
We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing.
In this paper we present the concept of thread shadowing and an implementation
on a multi-threaded hybrid multi-core architecture. We report on experiments with
a block-processing application and demonstrate the overheads, detection latencies
and coverage for a range of thread shadowing modes. The results show that trans-modal
thread shadowing, although bearing long detection latencies, offers attractive
coverage at a low overhead.
author:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid
Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP,
Bertels K, eds. Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer;
2014:283-290. doi:10.1007/978-3-319-05960-0_30'
apa: 'Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio,
J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer.
https://doi.org/10.1007/978-3-319-05960-0_30'
bibtex: '@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer
Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores
for Error Detection}, DOI={10.1007/978-3-319-05960-0_30},
booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner,
Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso,
JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic
Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the
10th International Symposium on Applied Reconfigurable Computing (ARC), edited
by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels,
283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.'
ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on
Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.'
mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer
et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.'
short: 'S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso,
K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.'
date_created: 2017-10-17T12:41:59Z
date_updated: 2022-01-06T06:59:18Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-05960-0_30
editor:
- first_name: Diana
full_name: Goehringer, Diana
last_name: Goehringer
- first_name: MarcoDomenico
full_name: Santambrogio, MarcoDomenico
last_name: Santambrogio
- first_name: JoãoM.P.
full_name: Cardoso, JoãoM.P.
last_name: Cardoso
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:26:16Z
date_updated: 2018-03-20T07:26:16Z
file_id: '1417'
file_name: 347-meisner13_xx_SFB1__1_.pdf
file_size: 1168877
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:26:16Z
has_accepted_license: '1'
language:
- iso: eng
page: 283-290
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: 'Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error
Detection'
type: conference
user_id: '398'
year: '2014'
...
---
_id: '1782'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science.
Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2'
apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in
Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25).
Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2'
bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture
Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2},
number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer},
author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25},
collection={Lecture Notes in Computer Science} }'
chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection
in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25.
Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.'
ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf.
on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games
(CG), Springer, Switzerland, 2014, pp. 14–25.'
date_created: 2018-03-26T13:50:37Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1007/978-3-319-09165-5_2
issue: '8427'
page: 14-25
place: Switzerland
publication: Proc. Conf. on Computers and Games (CG)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: On Semeai Detection in Monte-Carlo Go
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '399'
abstract:
- lang: eng
text: Ensuring memory access security is a challenge for reconfigurable systems
with multiple cores. Previous work introduced access monitors attached to the
memory subsystem to ensure that the cores adhere to pre-defined protocols when
accessing memory. In this paper, we combine access monitors with a formal runtime
verification technique known as proof-carrying hardware to guarantee memory security.
We extend previous work on proof-carrying hardware by covering sequential circuits
and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an
embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach
and the capabilities of the prototype, which constitutes the first realization
of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA
are measured as 2x-10x, depending on the resource type. The delay overhead is
substantial with almost 100x, but this is an extremely pessimistic estimate that
will be lowered once accurate timing analysis for FPGA overlays become available.
Finally, reconfiguration time for the virtual FPGA is about one order of magnitude
lower than for the native Zynq fabric.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers:
Combining Formal Verification with Monitoring. In: Proceedings of the International
Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771'
apa: 'Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in
Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings
of the International Conference on Field-Programmable Technology (FPT) (pp.
167–174). https://doi.org/10.1109/FPT.2014.7082771'
bibtex: '@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security
in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco},
year={2014}, pages={167–174} }'
chicago: 'Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security
in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In
Proceedings of the International Conference on Field-Programmable Technology
(FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771.'
ieee: 'T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable
Computers: Combining Formal Verification with Monitoring,” in Proceedings of
the International Conference on Field-Programmable Technology (FPT), 2014,
pp. 167–174.'
mla: 'Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining
Formal Verification with Monitoring.” Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.'
short: 'T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.'
date_created: 2017-10-17T12:42:09Z
date_updated: 2022-01-06T07:00:05Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/FPT.2014.7082771
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T06:57:44Z
date_updated: 2018-03-20T06:57:44Z
file_id: '1380'
file_name: 399-wiersema14_fpt_IEEE_approved.pdf
file_size: 404328
relation: main_file
success: 1
file_date_updated: 2018-03-20T06:57:44Z
has_accepted_license: '1'
language:
- iso: eng
page: 167-174
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
status: public
title: 'Memory Security in Reconfigurable Computers: Combining Formal Verification
with Monitoring'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '408'
abstract:
- lang: eng
text: Verification of hardware and software usually proceeds separately, software
analysis relying on the correctness of processors executing instructions. This
assumption is valid as long as the software runs on standard CPUs that have been
extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption.In
this paper we present an approach for integrating software analyses with hardware
verification, specifically targeting custom instruction set extensions. We propose
three different techniques for deriving the properties to be proven for the hardware
implementation of a custom instruction in order to support software analyses.
The techniques are designed to explore the trade-off between generality and efficiency
and span from proving functional equivalence over checking the rules of a particular
analysis domain to verifying actual pre and post conditions resulting from program
analysis. We demonstrate and compare the three techniques on example programs
with custom instructions, using stateof-the-art software and hardware verification
techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
citation:
ama: 'Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware
Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International
Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19'
apa: Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating
Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings
of the 11th International Conference on Integrated Formal Methods (iFM) (pp.
307–322). https://doi.org/10.1007/978-3-319-10181-1_19
bibtex: '@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating
Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19},
booktitle={Proceedings of the 11th International Conference on Integrated Formal
Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema,
Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors},
year={2014}, pages={307–322}, collection={LNCS} }'
chicago: Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim.
“Integrating Software and Hardware Verification.” In Proceedings of the 11th
International Conference on Integrated Formal Methods (IFM), edited by Elvira
Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19.
ieee: M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software
and Hardware Verification,” in Proceedings of the 11th International Conference
on Integrated Formal Methods (iFM), 2014, pp. 307–322.
mla: Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.”
Proceedings of the 11th International Conference on Integrated Formal Methods
(IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.
short: 'M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski
(Eds.), Proceedings of the 11th International Conference on Integrated Formal
Methods (IFM), 2014, pp. 307–322.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2022-01-06T07:00:14Z
ddc:
- '040'
department:
- _id: '77'
- _id: '78'
doi: 10.1007/978-3-319-10181-1_19
editor:
- first_name: Elvira
full_name: Albert, Elvira
last_name: Albert
- first_name: Emil
full_name: Sekerinski, Emil
last_name: Sekerinski
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:35:28Z
date_updated: 2018-03-16T11:35:28Z
file_id: '1364'
file_name: 408-jakobs14_ifm.pdf
file_size: 561325
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:35:28Z
has_accepted_license: '1'
language:
- iso: eng
page: 307-322
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the 11th International Conference on Integrated Formal
Methods (iFM)
series_title: LNCS
status: public
title: Integrating Software and Hardware Verification
type: conference
user_id: '477'
year: '2014'
...
---
_id: '433'
abstract:
- lang: eng
text: Virtual FPGAs are overlay architectures realized on top of physical FPGAs.
They are proposed to enhance or abstract away from the physical FPGA for experimenting
with novel architectures and design tool flows. In this paper, we present an embedding
of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip.
Such an embedding is required to fully harness the potential of virtual FPGAs,
in particular to give the virtual circuits access to main memory and operating
system services, and to enable a concurrent operation of virtualized and non-virtualized
circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS
operating system for hardware/software systems. Furthermore, we present an open
source tool flow to synthesize configurations for the virtual FPGA.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable
Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514'
apa: 'Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig)
(pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514'
bibtex: '@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={10.1109/ReConFig.2014.7032514},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner,
Marco}, year={2014}, pages={1–6} }'
chicago: 'Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–6, 2014. https://doi.org/10.1109/ReConFig.2014.7032514.'
ieee: 'T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into
Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.'
mla: 'Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip:
ReconOS Meets ZUMA.” Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514.'
short: 'T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.'
date_created: 2017-10-17T12:42:16Z
date_updated: 2022-01-06T07:00:56Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ReConFig.2014.7032514
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:30:58Z
date_updated: 2018-03-16T11:30:58Z
file_id: '1355'
file_name: 433-wiersema14_reconfig_IEEE_approved.pdf
file_size: 369333
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:30:58Z
has_accepted_license: '1'
language:
- iso: eng
page: '1-6 '
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
status: public
title: 'Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '10602'
author:
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Schaefers L, Platzner M. A Novel Technique and its Application to Computer
Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374.
doi:10.1109/TCIAIG.2014.2346997
apa: Schaefers, L., & Platzner, M. (2014). A Novel Technique and its Application
to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games,
6(3), 361–374. https://doi.org/10.1109/TCIAIG.2014.2346997
bibtex: '@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application
to Computer Go}, volume={6}, DOI={10.1109/TCIAIG.2014.2346997},
number={3}, journal={IEEE Transactions on Computational Intelligence and AI in
Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374}
}'
chicago: 'Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application
to Computer Go.” IEEE Transactions on Computational Intelligence and AI in
Games 6, no. 3 (2014): 361–74. https://doi.org/10.1109/TCIAIG.2014.2346997.'
ieee: L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer
Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol.
6, no. 3, pp. 361–374, 2014.
mla: Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application
to Computer Go.” IEEE Transactions on Computational Intelligence and AI in
Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.
short: L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence
and AI in Games 6 (2014) 361–374.
date_created: 2019-07-10T09:22:43Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TCIAIG.2014.2346997
intvolume: ' 6'
issue: '3'
language:
- iso: eng
page: 361-374
publication: IEEE Transactions on Computational Intelligence and AI in Games
status: public
title: A Novel Technique and its Application to Computer Go
type: journal_article
user_id: '3118'
volume: 6
year: '2014'
...
---
_id: '10603'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE
Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174
apa: Giefers, H., & Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core.
IEEE Transactions on Computers, 63(12), 2919–2932. https://doi.org/10.1109/TC.2013.174
bibtex: '@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh
Many-Core}, volume={63}, DOI={10.1109/TC.2013.174},
number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner
and Platzner, Marco}, year={2014}, pages={2919–2932} }'
chicago: 'Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh
Many-Core.” IEEE Transactions on Computers 63, no. 12 (2014): 2919–32.
https://doi.org/10.1109/TC.2013.174.'
ieee: H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,”
IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.
mla: Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.”
IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.
short: H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.
date_created: 2019-07-10T09:22:44Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TC.2013.174
intvolume: ' 63'
issue: '12'
language:
- iso: eng
page: 2919 - 2932
publication: IEEE Transactions on Computers
status: public
title: An FPGA-based Reconfigurable Mesh Many-Core
type: journal_article
user_id: '398'
volume: 63
year: '2014'
...
---
_id: '10621'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
citation:
ama: 'Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated
Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW).
RAW. ; 2014. doi:10.1109/IPDPSW.2014.37'
apa: 'Anwer, J., Platzner, M., & Meisner, S. (2014). FPGA Redundancy Configurations:
An Automated Design Space Exploration. In Reconfigurable Architectures Workshop
(RAW). https://doi.org/10.1109/IPDPSW.2014.37'
bibtex: '@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy
Configurations: An Automated Design Space Exploration}, DOI={10.1109/IPDPSW.2014.37},
booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb
and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }'
chicago: 'Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy
Configurations: An Automated Design Space Exploration.” In Reconfigurable Architectures
Workshop (RAW). RAW, 2014. https://doi.org/10.1109/IPDPSW.2014.37.'
ieee: 'J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An
Automated Design Space Exploration,” in Reconfigurable Architectures Workshop
(RAW), 2014.'
mla: 'Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design
Space Exploration.” Reconfigurable Architectures Workshop (RAW), 2014,
doi:10.1109/IPDPSW.2014.37.'
short: 'J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop
(RAW), 2014.'
date_created: 2019-07-10T09:32:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/IPDPSW.2014.37
language:
- iso: eng
publication: Reconfigurable Architectures Workshop (RAW)
series_title: RAW
status: public
title: 'FPGA Redundancy Configurations: An Automated Design Space Exploration'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10627'
author:
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
citation:
ama: Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board. Paderborn University; 2014.
apa: Bockhorn, A. (2014). Echtzeit Klassifikation von sEMG Signalen mit einem
low-cost DSP Evaluation Board. Paderborn University.
bibtex: '@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit
einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn,
Arne}, year={2014} }'
chicago: Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem
Low-Cost DSP Evaluation Board. Paderborn University, 2014.
ieee: A. Bockhorn, Echtzeit Klassifikation von sEMG Signalen mit einem low-cost
DSP Evaluation Board. Paderborn University, 2014.
mla: Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board. Paderborn University, 2014.
short: A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board, Paderborn University, 2014.
date_created: 2019-07-10T09:40:25Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation
Board
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10632'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. A computer vision-based approach to high density
EMG pattern recognition using structural similarity. In: Proc. MyoElectric
Controls Symposium (MEC). ; 2014.'
apa: Boschmann, A., & Platzner, M. (2014). A computer vision-based approach
to high density EMG pattern recognition using structural similarity. In Proc.
MyoElectric Controls Symposium (MEC).
bibtex: '@inproceedings{Boschmann_Platzner_2014, title={A computer vision-based
approach to high density EMG pattern recognition using structural similarity},
booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander
and Platzner, Marco}, year={2014} }'
chicago: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
to High Density EMG Pattern Recognition Using Structural Similarity.” In Proc.
MyoElectric Controls Symposium (MEC), 2014.
ieee: A. Boschmann and M. Platzner, “A computer vision-based approach to high density
EMG pattern recognition using structural similarity,” in Proc. MyoElectric
Controls Symposium (MEC), 2014.
mla: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
to High Density EMG Pattern Recognition Using Structural Similarity.” Proc.
MyoElectric Controls Symposium (MEC), 2014.
short: 'A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC),
2014.'
date_created: 2019-07-10T11:02:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. MyoElectric Controls Symposium (MEC)
status: public
title: A computer vision-based approach to high density EMG pattern recognition using
structural similarity
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10633'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing
electrode displacement effect using structural similarity. In: Proc. IEEE Int.
Conf. Eng. Med. Biolog. (EMBC). ; 2014.'
apa: 'Boschmann, A., & Platzner, M. (2014). Towards robust HD EMG pattern recognition:
Reducing electrode displacement effect using structural similarity. In Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC).'
bibtex: '@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern
recognition: Reducing electrode displacement effect using structural similarity},
booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann,
Alexander and Platzner, Marco}, year={2014} }'
chicago: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern
Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.”
In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
ieee: 'A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition:
Reducing electrode displacement effect using structural similarity,” in Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
mla: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition:
Reducing Electrode Displacement Effect Using Structural Similarity.” Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
short: 'A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC),
2014.'
date_created: 2019-07-10T11:02:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)
status: public
title: 'Towards robust HD EMG pattern recognition: Reducing electrode displacement
effect using structural similarity'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10640'
author:
- first_name: Marcel
full_name: Brand, Marcel
last_name: Brand
citation:
ama: Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University; 2014.
apa: Brand, M. (2014). A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University.
bibtex: '@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as
a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel},
year={2014} }'
chicago: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
ieee: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
mla: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
short: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array, Paderborn University, 2014.
date_created: 2019-07-10T11:03:41Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: A Generalized Loop Accelerator Implemented as a Coarse-Grained Array
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10645'
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
citation:
ama: Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores.
Paderborn University; 2014.
apa: Damschen, M. (2014). Easy-to-use-on-the-fly binary program acceleration
on many-cores. Paderborn University.
bibtex: '@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration
on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014}
}'
chicago: Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration
on Many-Cores. Paderborn University, 2014.
ieee: M. Damschen, Easy-to-use-on-the-fly binary program acceleration on many-cores.
Paderborn University, 2014.
mla: Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration on
Many-Cores. Paderborn University, 2014.
short: M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores,
Paderborn University, 2014.
date_created: 2019-07-10T11:08:47Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Easy-to-use-on-the-fly binary program acceleration on many-cores
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10654'
author:
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable
Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC).
; 2014.'
apa: Glette, K., & Kaufmann, P. (2014). Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System. In IEEE Congress on Evolutionary
Computation (CEC).
bibtex: '@inproceedings{Glette_Kaufmann_2014, title={Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System}, booktitle={IEEE Congress on Evolutionary
Computation (CEC)}, author={Glette, Kyrre and Kaufmann, Paul}, year={2014} }'
chicago: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System.” In IEEE Congress on Evolutionary
Computation (CEC), 2014.
ieee: K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable
Hardware Classifier System,” in IEEE Congress on Evolutionary Computation (CEC),
2014.
mla: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for
an Evolvable Hardware Classifier System.” IEEE Congress on Evolutionary Computation
(CEC), 2014.
short: 'K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC),
2014.'
date_created: 2019-07-10T11:13:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
publication: IEEE Congress on Evolutionary Computation (CEC)
status: public
title: Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10665'
author:
- first_name: Christoph
full_name: Hagedorn, Christoph
last_name: Hagedorn
citation:
ama: Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University;
2014.
apa: Hagedorn, C. (2014). Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University.
bibtex: '@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn
University}, author={Hagedorn, Christoph}, year={2014} }'
chicago: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
ieee: C. Hagedorn, Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University,
2014.
mla: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
short: C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014.
date_created: 2019-07-10T11:15:09Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller
in netzunabhängigen Notleuchten
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10674'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437},
booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
}'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on
Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic
and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
platforms
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10677'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems
(ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches:
A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf.
on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719},
booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl.
Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014,
pp. 31–37, doi:10.1109/ICES.2014.7008719.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10679'
author:
- first_name: Fabian
full_name: König, Fabian
last_name: König
citation:
ama: König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese. Paderborn University; 2014.
apa: König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese. Paderborn University.
bibtex: '@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian},
year={2014} }'
chicago: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
ieee: F. König, EMG-basierte simultane und proportionale Online-Steuerung einer
virtuellen Prothese. Paderborn University, 2014.
mla: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
short: F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese, Paderborn University, 2014.
date_created: 2019-07-10T11:23:20Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen
Prothese
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10701'
author:
- first_name: Benjamin
full_name: Koch, Benjamin
last_name: Koch
citation:
ama: Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University; 2014.
apa: Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University.
bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
year={2014} }'
chicago: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
ieee: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University, 2014.
mla: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University, 2014.
short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10715'
author:
- first_name: Robert
full_name: Mittendorf, Robert
last_name: Mittendorf
citation:
ama: Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs. Paderborn University; 2014.
apa: Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM using
multi-threading and FPGAs. Paderborn University.
bibtex: '@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM
using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf,
Robert}, year={2014} }'
chicago: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using
Multi-Threading and FPGAs. Paderborn University, 2014.
ieee: R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading
and FPGAs. Paderborn University, 2014.
mla: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs. Paderborn University, 2014.
short: R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs, Paderborn University, 2014.
date_created: 2019-07-10T11:48:26Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10732'
author:
- first_name: Christoph
full_name: Rüthing, Christoph
last_name: Rüthing
citation:
ama: Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University; 2014.
apa: Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University.
bibtex: '@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for
Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing,
Christoph}, year={2014} }'
chicago: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
ieee: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
mla: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
short: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores, Paderborn University, 2014.
date_created: 2019-07-10T11:58:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous
Multi-Cores
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10733'
abstract:
- lang: eng
text: "Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms.
It brought about great success in the past few years regarding the evaluation
of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this
thesis, we present a parallelization of the most popular MCTS variant for large
HPC compute clusters that efficiently shares a single game tree representation
in a distributed memory environment and scales up to 128 compute nodes and 2048
cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn
order to measure the impact of our parallelization on the search quality and remain
comparable to the most advanced MCTS implementations to date, we implemented it
in a state-of-the-art Go engine Gomorra, making it competitive with the strongest
Go programs in the world.\r\n\r\nWe further present an empirical comparison of
different Bayesian ranking systems when being used for predicting expert moves
for the game of Go and introduce a novel technique for automated detection and
analysis of evaluation uncertainties that show up during MCTS searches."
author:
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
citation:
ama: 'Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.'
apa: 'Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and
its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search
for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin
GmbH}, author={Schäfers, Lars}, year={2014} }'
chicago: 'Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and
Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
ieee: 'L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its
Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
mla: Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its
Application to Computer Go. Logos Verlag Berlin GmbH, 2014.
short: L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.
date_created: 2019-07-10T11:58:06Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: '133'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3748-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer
Go
type: dissertation
user_id: '3118'
year: '2014'
...
---
_id: '10738'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: 'Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After
a Power System Blackout. In: IEEE Power and Energy Society General Meeting
(IEEE GM). ; 2014.'
apa: Shen, C., Kaufmann, P., & Braun, M. (2014). Optimizing the Generator Start-up
Sequence After a Power System Blackout. In IEEE Power and Energy Society General
Meeting (IEEE GM).
bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator
Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy
Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and
Braun, Martin}, year={2014} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator
Start-up Sequence After a Power System Blackout.” In IEEE Power and Energy
Society General Meeting (IEEE GM), 2014.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence
After a Power System Blackout,” in IEEE Power and Energy Society General Meeting
(IEEE GM), 2014.
mla: Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power
System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM),
2014.
short: 'C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General
Meeting (IEEE GM), 2014.'
date_created: 2019-07-10T11:59:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: IEEE Power and Energy Society General Meeting (IEEE GM)
status: public
title: Optimizing the Generator Start-up Sequence After a Power System Blackout
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10739'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: 'Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and
Restoration Path Selection Algorithm. In: Power Systems Computation Conference
(PSCC). IEEE; 2014.'
apa: Shen, C., Kaufmann, P., & Braun, M. (2014). A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm. In Power Systems
Computation Conference (PSCC). IEEE.
bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems
Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann,
Paul and Braun, Martin}, year={2014} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm.” In Power Systems
Computation Conference (PSCC). IEEE, 2014.
ieee: C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration
and Restoration Path Selection Algorithm,” in Power Systems Computation Conference
(PSCC), 2014.
mla: Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration
Path Selection Algorithm.” Power Systems Computation Conference (PSCC),
IEEE, 2014.
short: 'C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference
(PSCC), IEEE, 2014.'
date_created: 2019-07-10T11:59:37Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: Power Systems Computation Conference (PSCC)
publisher: IEEE
status: public
title: A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10744'
author:
- first_name: Sebastian
full_name: Surmund, Sebastian
last_name: Surmund
citation:
ama: Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA. Paderborn University; 2014.
apa: Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University.
bibtex: '@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic
Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund,
Sebastian}, year={2014} }'
chicago: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
ieee: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
mla: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
short: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA, Paderborn University, 2014.
date_created: 2019-07-10T12:00:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform
FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10756'
author:
- first_name: Anna
full_name: I. Esparcia-Alc{\'a}zar, Anna
last_name: I. Esparcia-Alc{\'a}zar
- first_name: A.E.
full_name: Eiben, A.E.
last_name: Eiben
- first_name: Alexandros
full_name: Agapitos, Alexandros
last_name: Agapitos
- first_name: Anabela
full_name: Sim{\~o}es, Anabela
last_name: Sim{\~o}es
- first_name: Andrea
full_name: G.B. Tettamanzi, Andrea
last_name: G.B. Tettamanzi
- first_name: Antonio
full_name: Della Cioppa, Antonio
last_name: Della Cioppa
- first_name: Antonio
full_name: M. Mora, Antonio
last_name: M. Mora
- first_name: Carlos
full_name: Cotta, Carlos
last_name: Cotta
- first_name: Ernesto
full_name: Tarantino, Ernesto
last_name: Tarantino
- first_name: Evert
full_name: Haasdijk, Evert
last_name: Haasdijk
- first_name: Federico
full_name: Divina, Federico
last_name: Divina
- first_name: Francisco
full_name: Fern{\'a}ndez de Vega, Francisco
last_name: Fern{\'a}ndez de Vega
- first_name: Giovanni
full_name: Squillero, Giovanni
last_name: Squillero
- first_name: Ivanoe
full_name: De Falco, Ivanoe
last_name: De Falco
- first_name: J.
full_name: Ignacio Hidalgo, J.
last_name: Ignacio Hidalgo
- first_name: Kevin
full_name: Sim, Kevin
last_name: Sim
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Mengjie
full_name: Zhang, Mengjie
last_name: Zhang
- first_name: Neil
full_name: Urquhart, Neil
last_name: Urquhart
- first_name: Paolo
full_name: Burelli, Paolo
last_name: Burelli
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Petr
full_name: Po{\v s}{\'\i}k, Petr
last_name: Po{\v s}{\'\i}k
- first_name: Robert
full_name: Schaefer, Robert
last_name: Schaefer
- first_name: Rolf
full_name: Drechsler, Rolf
last_name: Drechsler
- first_name: Sophia
full_name: Antipolis, Sophia
last_name: Antipolis
- first_name: Stefano
full_name: Cagnoni, Stefano
last_name: Cagnoni
- first_name: Trung
full_name: Thanh Nguyen, Trung
last_name: Thanh Nguyen
- first_name: William
full_name: S. Bush (editors), William
last_name: S. Bush (editors)
citation:
ama: 'I. Esparcia-Alc{\’a}zar A, Eiben AE, Agapitos A, et al. Applications of
Evolutionary Computation - 17th European Conference, EvoApplications. Vol
8602. Granada, Spain: Springer; 2014.'
apa: 'I. Esparcia-Alc{\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\~o}es, A., G.B.
Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). Applications
of Evolutionary Computation - 17th European Conference, EvoApplications (Vol.
8602). Granada, Spain: Springer.'
bibtex: '@book{I. Esparcia-Alc{\’a}zar_Eiben_Agapitos_Sim{\~o}es_G.B. Tettamanzi_Della
Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture
Notes in Computer Science}, title={Applications of Evolutionary Computation -
17th European Conference, EvoApplications}, volume={8602}, publisher={Springer},
author={I. Esparcia-Alc{\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros
and Sim{\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio
and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert
and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }'
chicago: 'I. Esparcia-Alc{\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela
Sim{\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et
al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications.
Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014.'
ieee: 'A. I. Esparcia-Alc{\’a}zar et al., Applications of Evolutionary
Computation - 17th European Conference, EvoApplications, vol. 8602. Granada,
Spain: Springer, 2014.'
mla: I. Esparcia-Alc{\’a}zar, Anna, et al. Applications of Evolutionary Computation
- 17th European Conference, EvoApplications. Vol. 8602, Springer, 2014.
short: A. I. Esparcia-Alc{\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\~o}es, A. G.B.
Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk,
F. Divina, F. Fern{\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo,
K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\v s}{\’\i}k,
R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush
(editors), Applications of Evolutionary Computation - 17th European Conference,
EvoApplications, Springer, Granada, Spain, 2014.
date_created: 2019-07-10T12:06:33Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
intvolume: ' 8602'
place: Granada, Spain
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 17th European Conference, EvoApplications
type: book
user_id: '3118'
volume: 8602
year: '2014'
...
---
_id: '10764'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit
structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108'
apa: Anwer, J., & Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant
circuit structures on FPGAs. In IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 177–184). IEEE.
https://doi.org/10.1109/DFT.2014.6962108
bibtex: '@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation
for fault-tolerant circuit structures on FPGAs}, DOI={10.1109/DFT.2014.6962108},
booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and
Platzner, Marco}, year={2014}, pages={177–184} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for
Fault-Tolerant Circuit Structures on FPGAs.” In IEEE International Symposium
on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 177–84.
IEEE, 2014. https://doi.org/10.1109/DFT.2014.6962108.
ieee: J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant
circuit structures on FPGAs,” in IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 177–184.
mla: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant
Circuit Structures on FPGAs.” IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84,
doi:10.1109/DFT.2014.6962108.
short: 'J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.'
date_created: 2019-07-10T12:07:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2014.6962108
language:
- iso: eng
page: 177-184
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT)
publisher: IEEE
status: public
title: Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
type: conference
user_id: '398'
year: '2014'
...
---
_id: '10773'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process
variation analysis in nano-scaled technologies using column-wise sparse parameter
selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014,
title={Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection}, DOI={10.1109/NANOARCH.2014.6880479},
booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel
and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies
Using Column-Wise Sparse Parameter Selection.” In 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), 163–68. IEEE, 2014. https://doi.org/10.1109/NANOARCH.2014.6880479.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH), 2014, pp. 163–168.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled
Technologies Using Column-Wise Sparse Parameter Selection.” 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE,
2014, pp. 163–168.'
date_created: 2019-07-10T12:10:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/NANOARCH.2014.6880479
extern: '1'
language:
- iso: eng
page: 163-168
publication: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
publisher: IEEE
status: public
title: Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '13154'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search
for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and
Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863'
apa: Graf, T., & Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo
Tree Search for Computer Go. In 2014 IEEE Conference on Computational Intelligence
and Games (pp. 1–8). https://doi.org/10.1109/CIG.2014.6932863
bibtex: '@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in
Monte Carlo Tree Search for Computer Go}, DOI={10.1109/CIG.2014.6932863},
booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf,
Tobias and Platzner, Marco}, year={2014}, pages={1–8} }'
chicago: Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte
Carlo Tree Search for Computer Go.” In 2014 IEEE Conference on Computational
Intelligence and Games, 1–8, 2014. https://doi.org/10.1109/CIG.2014.6932863.
ieee: T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search
for Computer Go,” in 2014 IEEE Conference on Computational Intelligence and
Games, 2014, pp. 1–8.
mla: Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo
Tree Search for Computer Go.” 2014 IEEE Conference on Computational Intelligence
and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863.
short: 'T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence
and Games, 2014, pp. 1–8.'
date_created: 2019-09-09T09:09:31Z
date_updated: 2022-01-06T06:51:29Z
department:
- _id: '78'
doi: 10.1109/CIG.2014.6932863
language:
- iso: eng
page: 1-8
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2014 IEEE Conference on Computational Intelligence and Games
status: public
title: Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go
type: conference
user_id: '40778'
year: '2014'
...
---
_id: '335'
abstract:
- lang: eng
text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware
und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten
nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung
der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung
von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen
wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren
insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir
beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der
Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige
Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem
Computersystem besser in Hardware und welche besser in Software realisiert werden
sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen
Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat.
Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze
zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt,
um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten
Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software
beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen
eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption,
dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware
und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen
auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware
eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie
f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw.
l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer
flexiblen Software damit auf.
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software.
In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender
Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.”
Wilhelm Fink; 2014:123-144.'
apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen
Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144).
Wilhelm Fink.'
bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe
des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen
Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen},
publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller,
Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144},
collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }'
chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44.
Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink,
2014.'
ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware
und Software,” in Logiken strukturbildender Prozesse: Automatismen, J.
Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink,
2014, pp. 123–144.'
mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.'
short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn,
2014, pp. 123–144.'
date_created: 2017-10-17T12:41:57Z
date_updated: 2023-09-26T13:32:49Z
ddc:
- '040'
department:
- _id: '518'
- _id: '27'
- _id: '78'
editor:
- first_name: Jörn
full_name: Künsemöller, Jörn
last_name: Künsemöller
- first_name: Norber Otto
full_name: Eke, Norber Otto
last_name: Eke
- first_name: Lioba
full_name: Foit, Lioba
last_name: Foit
- first_name: Timo
full_name: Kaerlein, Timo
last_name: Kaerlein
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:29:58Z
date_updated: 2018-03-20T07:29:58Z
file_id: '1424'
file_name: 335-2014_plessl_automatismen.pdf
file_size: 2848154
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:29:58Z
has_accepted_license: '1'
language:
- iso: ger
page: 123-144
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Logiken strukturbildender Prozesse: Automatismen'
publication_identifier:
isbn:
- 978-3-7705-5730-1
publication_status: published
publisher: Wilhelm Fink
quality_controlled: '1'
series_title: Schriftenreihe des Graduiertenkollegs "Automatismen"
status: public
title: Verschiebungen an der Grenze zwischen Hardware und Software
type: book_chapter
user_id: '15278'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '365'
abstract:
- lang: eng
text: Self-aware computing is a paradigm for structuring and simplifying the design
and operation of computing systems that face unprecedented levels of system dynamics
and thus require novel forms of adaptivity. The generality of the paradigm makes
it applicable to many types of computing systems and, previously, researchers
started to introduce concepts of self-awareness to multicore architectures. In
our work we build on a recent reference architectural framework as a model for
self-aware computing and instantiate it for an FPGA-based heterogeneous multicore
running the ReconOS reconfigurable architecture and operating system. After presenting
the model for self-aware computing and ReconOS, we demonstrate with a case study
how a multicore application built on the principle of self-awareness, autonomously
adapts to changes in the workload and system state. Our work shows that the reference
architectural framework as a model for self-aware computing can be practically
applied and allows us to structure and simplify the design process, which is essential
for designing complex future computing systems.
article_number: '13'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for
Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable
Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions
on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13.
https://doi.org/10.1145/2617596
bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as
a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM
Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM},
author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian
and Platzner, Marco}, year={2014} }'
chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner.
“Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no.
2 (2014). https://doi.org/10.1145/2617596.
ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions
on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no.
13, 2014, doi: 10.1145/2617596.'
mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating
Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on
Reconfigurable Technology and Systems (TRETS) 7 (2014).
date_created: 2017-10-17T12:42:03Z
date_updated: 2023-09-26T13:33:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '78'
- _id: '518'
doi: 10.1145/2617596
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:19:19Z
date_updated: 2018-03-20T07:19:19Z
file_id: '1406'
file_name: 365-plessl14_trets_01.pdf
file_size: 916052
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:19:19Z
has_accepted_license: '1'
intvolume: ' 7'
issue: '2'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publisher: ACM
quality_controlled: '1'
status: public
title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
type: journal_article
user_id: '15278'
volume: 7
year: '2014'
...
---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1779'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain
Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture
News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH
Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372
bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41},
DOI={10.1145/2641361.2641372},
number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM},
author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014},
pages={65–70} }'
chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite
Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM
SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.'
ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time
Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer
Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.'
mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations
with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture
News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.
short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News
41 (2014) 65–70.
date_created: 2018-03-26T13:42:34Z
date_updated: 2023-09-26T13:35:58Z
department:
- _id: '27'
- _id: '518'
- _id: '61'
- _id: '78'
doi: 10.1145/2641361.2641372
intvolume: ' 41'
issue: '5'
keyword:
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 65-70
publication: ACM SIGARCH Computer Architecture News
publication_identifier:
issn:
- 0163-5964
publisher: ACM
quality_controlled: '1'
status: public
title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable
Dataflow Computers
type: journal_article
user_id: '15278'
volume: 41
year: '2014'
...
---
_id: '11619'
abstract:
- lang: eng
text: "Reconfigurable circuit devices have opened up a fundamentally new way of
creating adaptable systems. Combined with artificial evolution, reconfigurable
circuits allow an elegant adaptation approach to compensating for changes in the
distribution of input data, computational resource errors, and variations in resource
requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded
astonishing results for traditional engineering challenges and has discovered
intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn
this thesis, we present new and fundamental work on Evolvable Hardware motivated
by the insight that Evolvable Hardware needs to compensate for events with different
change rates. To solve the challenge of different adaptation speeds, we propose
a unified adaptation approach based on multi-objective evolution, evolving and
propagating candidate solutions that are diverse in objectives that may experience
radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic
Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective
optimization by introducing a meaningful recombination operator. We improve the
scalability of CGP by objectives scaling, periodization of local- and global-search
algorithms, and the automatic acquisition and reuse of subfunctions using age-
and cone-based techniques. We validate our methods on the applications of adaptation
of hardware classifiers to resource changes, recognition of muscular signals for
prosthesis control and optimization of processor caches."
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann,
Paul}, year={2013} }'
chicago: 'Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Logos Verlag Berlin GmbH, 2013.
short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2019-07-11T11:51:51Z
date_updated: 2022-01-06T06:51:04Z
department:
- _id: '78'
language:
- iso: eng
page: '249'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3530-8
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: dissertation
user_id: '3118'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1792'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing
the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans
on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3),
522–536. https://doi.org/10.1109/TVLSI.2013.2248069
bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices},
volume={22}, DOI={10.1109/TVLSI.2013.2248069},
number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems},
publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536}
}'
chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array
Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial
Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22,
no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.'
ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for
Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, pp. 522–536, 2013.
mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.
short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems
22 (2013) 522–536.
date_created: 2018-03-26T15:15:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/TVLSI.2013.2248069
intvolume: ' 22'
issue: '3'
page: 522-536
publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems
publisher: IEEE
status: public
title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue
Decomposition of Para-Hermitian Polynomial Matrices
type: journal_article
user_id: '24135'
volume: 22
year: '2013'
...
---
_id: '501'
abstract:
- lang: eng
text: 'Handling run-time dynamics on embedded system-on-chip architectures has become
more challenging over the years. On the one hand, the impact of workload and physical
dynamics on the system behavior has dramatically increased. On the other hand,
embedded architectures have become more complex as they have evolved from single-processor
systems over multi-processor systems to hybrid multi-core platforms.Static design-time
techniques no longer provide suitable solutions to deal with the run-time dynamics
of today''s embedded systems. Therefore, system designers have to apply run-time
solutions, which have hardly been investigated for hybrid multi-core platforms.In
this thesis, we present fundamental work in the new area of run-time management
on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive
hybrid multi-core system, that combines heterogeneous processors, reconfigurable
hardware cores, and monitoring cores on a single chip. Using self-adaptation on
thread-level, our hybrid multi-core systems can effectively perform performance
and thermal management autonomously at run-time. '
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
citation:
ama: 'Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Happe, M. (2013). Performance and thermal management on self-adaptive hybrid
multi-cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Happe_2013, place={Berlin}, title={Performance and thermal management
on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe,
Markus}, year={2013} }'
chicago: 'Happe, Markus. Performance and Thermal Management on Self-Adaptive
Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid
Multi-Cores. Logos Verlag Berlin GmbH, 2013.
short: M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2017-10-17T12:42:30Z
date_updated: 2022-01-06T07:01:34Z
department:
- _id: '78'
language:
- iso: eng
page: '220'
place: Berlin
project:
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publication_identifier:
isbn:
- 978-3-8325-3425-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
related_material:
link:
- relation: confirmation
url: https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Performance and thermal management on self-adaptive hybrid multi-cores
type: dissertation
user_id: '477'
year: '2013'
...