---
_id: '10665'
author:
- first_name: Christoph
full_name: Hagedorn, Christoph
last_name: Hagedorn
citation:
ama: Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University;
2014.
apa: Hagedorn, C. (2014). Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University.
bibtex: '@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn
University}, author={Hagedorn, Christoph}, year={2014} }'
chicago: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
ieee: C. Hagedorn, Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University,
2014.
mla: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
short: C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014.
date_created: 2019-07-10T11:15:09Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller
in netzunabhängigen Notleuchten
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10674'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437},
booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
}'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on
Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic
and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
platforms
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10677'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems
(ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches:
A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf.
on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719},
booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl.
Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014,
pp. 31–37, doi:10.1109/ICES.2014.7008719.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10679'
author:
- first_name: Fabian
full_name: König, Fabian
last_name: König
citation:
ama: König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese. Paderborn University; 2014.
apa: König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese. Paderborn University.
bibtex: '@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian},
year={2014} }'
chicago: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
ieee: F. König, EMG-basierte simultane und proportionale Online-Steuerung einer
virtuellen Prothese. Paderborn University, 2014.
mla: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
short: F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese, Paderborn University, 2014.
date_created: 2019-07-10T11:23:20Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen
Prothese
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10701'
author:
- first_name: Benjamin
full_name: Koch, Benjamin
last_name: Koch
citation:
ama: Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University; 2014.
apa: Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University.
bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
year={2014} }'
chicago: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
ieee: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University, 2014.
mla: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University, 2014.
short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10715'
author:
- first_name: Robert
full_name: Mittendorf, Robert
last_name: Mittendorf
citation:
ama: Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs. Paderborn University; 2014.
apa: Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM using
multi-threading and FPGAs. Paderborn University.
bibtex: '@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM
using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf,
Robert}, year={2014} }'
chicago: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using
Multi-Threading and FPGAs. Paderborn University, 2014.
ieee: R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading
and FPGAs. Paderborn University, 2014.
mla: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs. Paderborn University, 2014.
short: R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
and FPGAs, Paderborn University, 2014.
date_created: 2019-07-10T11:48:26Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10732'
author:
- first_name: Christoph
full_name: Rüthing, Christoph
last_name: Rüthing
citation:
ama: Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University; 2014.
apa: Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University.
bibtex: '@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for
Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing,
Christoph}, year={2014} }'
chicago: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
ieee: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
mla: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Paderborn University, 2014.
short: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores, Paderborn University, 2014.
date_created: 2019-07-10T11:58:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous
Multi-Cores
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10733'
abstract:
- lang: eng
text: "Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms.
It brought about great success in the past few years regarding the evaluation
of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this
thesis, we present a parallelization of the most popular MCTS variant for large
HPC compute clusters that efficiently shares a single game tree representation
in a distributed memory environment and scales up to 128 compute nodes and 2048
cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn
order to measure the impact of our parallelization on the search quality and remain
comparable to the most advanced MCTS implementations to date, we implemented it
in a state-of-the-art Go engine Gomorra, making it competitive with the strongest
Go programs in the world.\r\n\r\nWe further present an empirical comparison of
different Bayesian ranking systems when being used for predicting expert moves
for the game of Go and introduce a novel technique for automated detection and
analysis of evaluation uncertainties that show up during MCTS searches."
author:
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
citation:
ama: 'Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.'
apa: 'Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and
its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search
for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin
GmbH}, author={Schäfers, Lars}, year={2014} }'
chicago: 'Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and
Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
ieee: 'L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its
Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
mla: Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its
Application to Computer Go. Logos Verlag Berlin GmbH, 2014.
short: L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.
date_created: 2019-07-10T11:58:06Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: '133'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3748-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer
Go
type: dissertation
user_id: '3118'
year: '2014'
...
---
_id: '10738'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: 'Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After
a Power System Blackout. In: IEEE Power and Energy Society General Meeting
(IEEE GM). ; 2014.'
apa: Shen, C., Kaufmann, P., & Braun, M. (2014). Optimizing the Generator Start-up
Sequence After a Power System Blackout. In IEEE Power and Energy Society General
Meeting (IEEE GM).
bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator
Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy
Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and
Braun, Martin}, year={2014} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator
Start-up Sequence After a Power System Blackout.” In IEEE Power and Energy
Society General Meeting (IEEE GM), 2014.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence
After a Power System Blackout,” in IEEE Power and Energy Society General Meeting
(IEEE GM), 2014.
mla: Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power
System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM),
2014.
short: 'C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General
Meeting (IEEE GM), 2014.'
date_created: 2019-07-10T11:59:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: IEEE Power and Energy Society General Meeting (IEEE GM)
status: public
title: Optimizing the Generator Start-up Sequence After a Power System Blackout
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10739'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: 'Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and
Restoration Path Selection Algorithm. In: Power Systems Computation Conference
(PSCC). IEEE; 2014.'
apa: Shen, C., Kaufmann, P., & Braun, M. (2014). A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm. In Power Systems
Computation Conference (PSCC). IEEE.
bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems
Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann,
Paul and Braun, Martin}, year={2014} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network
Reconfiguration and Restoration Path Selection Algorithm.” In Power Systems
Computation Conference (PSCC). IEEE, 2014.
ieee: C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration
and Restoration Path Selection Algorithm,” in Power Systems Computation Conference
(PSCC), 2014.
mla: Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration
Path Selection Algorithm.” Power Systems Computation Conference (PSCC),
IEEE, 2014.
short: 'C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference
(PSCC), IEEE, 2014.'
date_created: 2019-07-10T11:59:37Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: Power Systems Computation Conference (PSCC)
publisher: IEEE
status: public
title: A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10744'
author:
- first_name: Sebastian
full_name: Surmund, Sebastian
last_name: Surmund
citation:
ama: Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA. Paderborn University; 2014.
apa: Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University.
bibtex: '@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic
Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund,
Sebastian}, year={2014} }'
chicago: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
ieee: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
mla: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
short: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA, Paderborn University, 2014.
date_created: 2019-07-10T12:00:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform
FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10756'
author:
- first_name: Anna
full_name: I. Esparcia-Alc{\'a}zar, Anna
last_name: I. Esparcia-Alc{\'a}zar
- first_name: A.E.
full_name: Eiben, A.E.
last_name: Eiben
- first_name: Alexandros
full_name: Agapitos, Alexandros
last_name: Agapitos
- first_name: Anabela
full_name: Sim{\~o}es, Anabela
last_name: Sim{\~o}es
- first_name: Andrea
full_name: G.B. Tettamanzi, Andrea
last_name: G.B. Tettamanzi
- first_name: Antonio
full_name: Della Cioppa, Antonio
last_name: Della Cioppa
- first_name: Antonio
full_name: M. Mora, Antonio
last_name: M. Mora
- first_name: Carlos
full_name: Cotta, Carlos
last_name: Cotta
- first_name: Ernesto
full_name: Tarantino, Ernesto
last_name: Tarantino
- first_name: Evert
full_name: Haasdijk, Evert
last_name: Haasdijk
- first_name: Federico
full_name: Divina, Federico
last_name: Divina
- first_name: Francisco
full_name: Fern{\'a}ndez de Vega, Francisco
last_name: Fern{\'a}ndez de Vega
- first_name: Giovanni
full_name: Squillero, Giovanni
last_name: Squillero
- first_name: Ivanoe
full_name: De Falco, Ivanoe
last_name: De Falco
- first_name: J.
full_name: Ignacio Hidalgo, J.
last_name: Ignacio Hidalgo
- first_name: Kevin
full_name: Sim, Kevin
last_name: Sim
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Mengjie
full_name: Zhang, Mengjie
last_name: Zhang
- first_name: Neil
full_name: Urquhart, Neil
last_name: Urquhart
- first_name: Paolo
full_name: Burelli, Paolo
last_name: Burelli
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Petr
full_name: Po{\v s}{\'\i}k, Petr
last_name: Po{\v s}{\'\i}k
- first_name: Robert
full_name: Schaefer, Robert
last_name: Schaefer
- first_name: Rolf
full_name: Drechsler, Rolf
last_name: Drechsler
- first_name: Sophia
full_name: Antipolis, Sophia
last_name: Antipolis
- first_name: Stefano
full_name: Cagnoni, Stefano
last_name: Cagnoni
- first_name: Trung
full_name: Thanh Nguyen, Trung
last_name: Thanh Nguyen
- first_name: William
full_name: S. Bush (editors), William
last_name: S. Bush (editors)
citation:
ama: 'I. Esparcia-Alc{\’a}zar A, Eiben AE, Agapitos A, et al. Applications of
Evolutionary Computation - 17th European Conference, EvoApplications. Vol
8602. Granada, Spain: Springer; 2014.'
apa: 'I. Esparcia-Alc{\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\~o}es, A., G.B.
Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). Applications
of Evolutionary Computation - 17th European Conference, EvoApplications (Vol.
8602). Granada, Spain: Springer.'
bibtex: '@book{I. Esparcia-Alc{\’a}zar_Eiben_Agapitos_Sim{\~o}es_G.B. Tettamanzi_Della
Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture
Notes in Computer Science}, title={Applications of Evolutionary Computation -
17th European Conference, EvoApplications}, volume={8602}, publisher={Springer},
author={I. Esparcia-Alc{\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros
and Sim{\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio
and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert
and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }'
chicago: 'I. Esparcia-Alc{\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela
Sim{\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et
al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications.
Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014.'
ieee: 'A. I. Esparcia-Alc{\’a}zar et al., Applications of Evolutionary
Computation - 17th European Conference, EvoApplications, vol. 8602. Granada,
Spain: Springer, 2014.'
mla: I. Esparcia-Alc{\’a}zar, Anna, et al. Applications of Evolutionary Computation
- 17th European Conference, EvoApplications. Vol. 8602, Springer, 2014.
short: A. I. Esparcia-Alc{\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\~o}es, A. G.B.
Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk,
F. Divina, F. Fern{\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo,
K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\v s}{\’\i}k,
R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush
(editors), Applications of Evolutionary Computation - 17th European Conference,
EvoApplications, Springer, Granada, Spain, 2014.
date_created: 2019-07-10T12:06:33Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
intvolume: ' 8602'
place: Granada, Spain
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 17th European Conference, EvoApplications
type: book
user_id: '3118'
volume: 8602
year: '2014'
...
---
_id: '10764'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit
structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108'
apa: Anwer, J., & Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant
circuit structures on FPGAs. In IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 177–184). IEEE.
https://doi.org/10.1109/DFT.2014.6962108
bibtex: '@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation
for fault-tolerant circuit structures on FPGAs}, DOI={10.1109/DFT.2014.6962108},
booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and
Platzner, Marco}, year={2014}, pages={177–184} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for
Fault-Tolerant Circuit Structures on FPGAs.” In IEEE International Symposium
on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 177–84.
IEEE, 2014. https://doi.org/10.1109/DFT.2014.6962108.
ieee: J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant
circuit structures on FPGAs,” in IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 177–184.
mla: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant
Circuit Structures on FPGAs.” IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84,
doi:10.1109/DFT.2014.6962108.
short: 'J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.'
date_created: 2019-07-10T12:07:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2014.6962108
language:
- iso: eng
page: 177-184
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT)
publisher: IEEE
status: public
title: Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
type: conference
user_id: '398'
year: '2014'
...
---
_id: '10773'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process
variation analysis in nano-scaled technologies using column-wise sparse parameter
selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014,
title={Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection}, DOI={10.1109/NANOARCH.2014.6880479},
booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel
and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies
Using Column-Wise Sparse Parameter Selection.” In 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), 163–68. IEEE, 2014. https://doi.org/10.1109/NANOARCH.2014.6880479.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH), 2014, pp. 163–168.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled
Technologies Using Column-Wise Sparse Parameter Selection.” 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE,
2014, pp. 163–168.'
date_created: 2019-07-10T12:10:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/NANOARCH.2014.6880479
extern: '1'
language:
- iso: eng
page: 163-168
publication: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
publisher: IEEE
status: public
title: Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '13154'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search
for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and
Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863'
apa: Graf, T., & Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo
Tree Search for Computer Go. In 2014 IEEE Conference on Computational Intelligence
and Games (pp. 1–8). https://doi.org/10.1109/CIG.2014.6932863
bibtex: '@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in
Monte Carlo Tree Search for Computer Go}, DOI={10.1109/CIG.2014.6932863},
booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf,
Tobias and Platzner, Marco}, year={2014}, pages={1–8} }'
chicago: Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte
Carlo Tree Search for Computer Go.” In 2014 IEEE Conference on Computational
Intelligence and Games, 1–8, 2014. https://doi.org/10.1109/CIG.2014.6932863.
ieee: T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search
for Computer Go,” in 2014 IEEE Conference on Computational Intelligence and
Games, 2014, pp. 1–8.
mla: Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo
Tree Search for Computer Go.” 2014 IEEE Conference on Computational Intelligence
and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863.
short: 'T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence
and Games, 2014, pp. 1–8.'
date_created: 2019-09-09T09:09:31Z
date_updated: 2022-01-06T06:51:29Z
department:
- _id: '78'
doi: 10.1109/CIG.2014.6932863
language:
- iso: eng
page: 1-8
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2014 IEEE Conference on Computational Intelligence and Games
status: public
title: Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go
type: conference
user_id: '40778'
year: '2014'
...
---
_id: '335'
abstract:
- lang: eng
text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware
und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten
nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung
der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung
von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen
wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren
insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir
beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der
Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige
Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem
Computersystem besser in Hardware und welche besser in Software realisiert werden
sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen
Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat.
Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze
zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt,
um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten
Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software
beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen
eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption,
dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware
und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen
auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware
eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie
f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw.
l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer
flexiblen Software damit auf.
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software.
In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender
Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.”
Wilhelm Fink; 2014:123-144.'
apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen
Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144).
Wilhelm Fink.'
bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe
des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen
Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen},
publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller,
Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144},
collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }'
chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44.
Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink,
2014.'
ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware
und Software,” in Logiken strukturbildender Prozesse: Automatismen, J.
Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink,
2014, pp. 123–144.'
mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.'
short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn,
2014, pp. 123–144.'
date_created: 2017-10-17T12:41:57Z
date_updated: 2023-09-26T13:32:49Z
ddc:
- '040'
department:
- _id: '518'
- _id: '27'
- _id: '78'
editor:
- first_name: Jörn
full_name: Künsemöller, Jörn
last_name: Künsemöller
- first_name: Norber Otto
full_name: Eke, Norber Otto
last_name: Eke
- first_name: Lioba
full_name: Foit, Lioba
last_name: Foit
- first_name: Timo
full_name: Kaerlein, Timo
last_name: Kaerlein
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:29:58Z
date_updated: 2018-03-20T07:29:58Z
file_id: '1424'
file_name: 335-2014_plessl_automatismen.pdf
file_size: 2848154
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:29:58Z
has_accepted_license: '1'
language:
- iso: ger
page: 123-144
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Logiken strukturbildender Prozesse: Automatismen'
publication_identifier:
isbn:
- 978-3-7705-5730-1
publication_status: published
publisher: Wilhelm Fink
quality_controlled: '1'
series_title: Schriftenreihe des Graduiertenkollegs "Automatismen"
status: public
title: Verschiebungen an der Grenze zwischen Hardware und Software
type: book_chapter
user_id: '15278'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '365'
abstract:
- lang: eng
text: Self-aware computing is a paradigm for structuring and simplifying the design
and operation of computing systems that face unprecedented levels of system dynamics
and thus require novel forms of adaptivity. The generality of the paradigm makes
it applicable to many types of computing systems and, previously, researchers
started to introduce concepts of self-awareness to multicore architectures. In
our work we build on a recent reference architectural framework as a model for
self-aware computing and instantiate it for an FPGA-based heterogeneous multicore
running the ReconOS reconfigurable architecture and operating system. After presenting
the model for self-aware computing and ReconOS, we demonstrate with a case study
how a multicore application built on the principle of self-awareness, autonomously
adapts to changes in the workload and system state. Our work shows that the reference
architectural framework as a model for self-aware computing can be practically
applied and allows us to structure and simplify the design process, which is essential
for designing complex future computing systems.
article_number: '13'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for
Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable
Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions
on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13.
https://doi.org/10.1145/2617596
bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as
a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM
Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM},
author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian
and Platzner, Marco}, year={2014} }'
chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner.
“Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no.
2 (2014). https://doi.org/10.1145/2617596.
ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions
on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no.
13, 2014, doi: 10.1145/2617596.'
mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating
Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on
Reconfigurable Technology and Systems (TRETS) 7 (2014).
date_created: 2017-10-17T12:42:03Z
date_updated: 2023-09-26T13:33:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '78'
- _id: '518'
doi: 10.1145/2617596
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:19:19Z
date_updated: 2018-03-20T07:19:19Z
file_id: '1406'
file_name: 365-plessl14_trets_01.pdf
file_size: 916052
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:19:19Z
has_accepted_license: '1'
intvolume: ' 7'
issue: '2'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publisher: ACM
quality_controlled: '1'
status: public
title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
type: journal_article
user_id: '15278'
volume: 7
year: '2014'
...
---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1779'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain
Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture
News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH
Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372
bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41},
DOI={10.1145/2641361.2641372},
number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM},
author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014},
pages={65–70} }'
chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite
Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM
SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.'
ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time
Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer
Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.'
mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations
with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture
News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.
short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News
41 (2014) 65–70.
date_created: 2018-03-26T13:42:34Z
date_updated: 2023-09-26T13:35:58Z
department:
- _id: '27'
- _id: '518'
- _id: '61'
- _id: '78'
doi: 10.1145/2641361.2641372
intvolume: ' 41'
issue: '5'
keyword:
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 65-70
publication: ACM SIGARCH Computer Architecture News
publication_identifier:
issn:
- 0163-5964
publisher: ACM
quality_controlled: '1'
status: public
title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable
Dataflow Computers
type: journal_article
user_id: '15278'
volume: 41
year: '2014'
...
---
_id: '11619'
abstract:
- lang: eng
text: "Reconfigurable circuit devices have opened up a fundamentally new way of
creating adaptable systems. Combined with artificial evolution, reconfigurable
circuits allow an elegant adaptation approach to compensating for changes in the
distribution of input data, computational resource errors, and variations in resource
requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded
astonishing results for traditional engineering challenges and has discovered
intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn
this thesis, we present new and fundamental work on Evolvable Hardware motivated
by the insight that Evolvable Hardware needs to compensate for events with different
change rates. To solve the challenge of different adaptation speeds, we propose
a unified adaptation approach based on multi-objective evolution, evolving and
propagating candidate solutions that are diverse in objectives that may experience
radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic
Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective
optimization by introducing a meaningful recombination operator. We improve the
scalability of CGP by objectives scaling, periodization of local- and global-search
algorithms, and the automatic acquisition and reuse of subfunctions using age-
and cone-based techniques. We validate our methods on the applications of adaptation
of hardware classifiers to resource changes, recognition of muscular signals for
prosthesis control and optimization of processor caches."
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann,
Paul}, year={2013} }'
chicago: 'Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Logos Verlag Berlin GmbH, 2013.
short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2019-07-11T11:51:51Z
date_updated: 2022-01-06T06:51:04Z
department:
- _id: '78'
language:
- iso: eng
page: '249'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3530-8
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: dissertation
user_id: '3118'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1792'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing
the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans
on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3),
522–536. https://doi.org/10.1109/TVLSI.2013.2248069
bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices},
volume={22}, DOI={10.1109/TVLSI.2013.2248069},
number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems},
publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536}
}'
chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array
Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial
Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22,
no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.'
ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for
Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, pp. 522–536, 2013.
mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.
short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems
22 (2013) 522–536.
date_created: 2018-03-26T15:15:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/TVLSI.2013.2248069
intvolume: ' 22'
issue: '3'
page: 522-536
publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems
publisher: IEEE
status: public
title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue
Decomposition of Para-Hermitian Polynomial Matrices
type: journal_article
user_id: '24135'
volume: 22
year: '2013'
...
---
_id: '501'
abstract:
- lang: eng
text: 'Handling run-time dynamics on embedded system-on-chip architectures has become
more challenging over the years. On the one hand, the impact of workload and physical
dynamics on the system behavior has dramatically increased. On the other hand,
embedded architectures have become more complex as they have evolved from single-processor
systems over multi-processor systems to hybrid multi-core platforms.Static design-time
techniques no longer provide suitable solutions to deal with the run-time dynamics
of today''s embedded systems. Therefore, system designers have to apply run-time
solutions, which have hardly been investigated for hybrid multi-core platforms.In
this thesis, we present fundamental work in the new area of run-time management
on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive
hybrid multi-core system, that combines heterogeneous processors, reconfigurable
hardware cores, and monitoring cores on a single chip. Using self-adaptation on
thread-level, our hybrid multi-core systems can effectively perform performance
and thermal management autonomously at run-time. '
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
citation:
ama: 'Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Happe, M. (2013). Performance and thermal management on self-adaptive hybrid
multi-cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Happe_2013, place={Berlin}, title={Performance and thermal management
on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe,
Markus}, year={2013} }'
chicago: 'Happe, Markus. Performance and Thermal Management on Self-Adaptive
Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid
Multi-Cores. Logos Verlag Berlin GmbH, 2013.
short: M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2017-10-17T12:42:30Z
date_updated: 2022-01-06T07:01:34Z
department:
- _id: '78'
language:
- iso: eng
page: '220'
place: Berlin
project:
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publication_identifier:
isbn:
- 978-3-8325-3425-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
related_material:
link:
- relation: confirmation
url: https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Performance and thermal management on self-adaptive hybrid multi-cores
type: dissertation
user_id: '477'
year: '2013'
...
---
_id: '10604'
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture
for Embedded Real-time Video Object Tracking. International Journal of Real-time
Image Processing. 2013;8(1):95-110. doi:doi:10.1007/s11554-011-0212-y
apa: Happe, M., Lübbers, E., & Platzner, M. (2013). A Self-adaptive Heterogeneous
Multi-core Architecture for Embedded Real-time Video Object Tracking. International
Journal of Real-Time Image Processing, 8(1), 95–110. https://doi.org/doi:10.1007/s11554-011-0212-y
bibtex: '@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous
Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8},
DOI={doi:10.1007/s11554-011-0212-y},
number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer},
author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110}
}'
chicago: 'Happe, Markus, Enno Lübbers, and Marco Platzner. “A Self-Adaptive Heterogeneous
Multi-Core Architecture for Embedded Real-Time Video Object Tracking.” International
Journal of Real-Time Image Processing 8, no. 1 (2013): 95–110. https://doi.org/doi:10.1007/s11554-011-0212-y.'
ieee: M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core
Architecture for Embedded Real-time Video Object Tracking,” International Journal
of Real-time Image Processing, vol. 8, no. 1, pp. 95–110, 2013.
mla: Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture
for Embedded Real-Time Video Object Tracking.” International Journal of Real-Time
Image Processing, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:doi:10.1007/s11554-011-0212-y.
short: M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image
Processing 8 (2013) 95–110.
date_created: 2019-07-10T09:22:45Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: doi:10.1007/s11554-011-0212-y
intvolume: ' 8'
issue: '1'
language:
- iso: eng
page: 95 - 110
publication: International Journal of Real-time Image Processing
publisher: Springer
status: public
title: A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time
Video Object Tracking
type: journal_article
user_id: '398'
volume: 8
year: '2013'
...
---
_id: '10620'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime. In: Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280'
apa: 'Anwer, J., Meisner, S., & Platzner, M. (2013). Dynamic reliability management:
Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable
Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6).
https://doi.org/10.1109/ReConFig.2013.6732280'
bibtex: '@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability
management: Reconfiguring reliability-levels of hardware designs at runtime},
DOI={10.1109/ReConFig.2013.6732280},
booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013},
pages={1–6} }'
chicago: 'Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.”
In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
On, 1–6, 2013. https://doi.org/10.1109/ReConFig.2013.6732280.'
ieee: 'J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime,” in Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6.'
mla: 'Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels
of Hardware Designs at Runtime.” Reconfigurable Computing and FPGAs (ReConFig),
2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.'
short: 'J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs
(ReConFig), 2013 International Conference On, 2013, pp. 1–6.'
date_created: 2019-07-10T09:32:57Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/ReConFig.2013.6732280
keyword:
- fault tolerant computing
- field programmable gate arrays
- logic design
- reliability
- BYU-LANL tool
- DRM tool flow
- FPGA based hardware designs
- avionic application
- device technologies
- dynamic reliability management
- fault-tolerant operation
- hardware designs
- reconfiguring reliability levels
- space applications
- Field programmable gate arrays
- Hardware
- Redundancy
- Reliability engineering
- Runtime
- Tunneling magnetoresistance
language:
- iso: eng
page: 1-6
publication: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on
status: public
title: 'Dynamic reliability management: Reconfiguring reliability-levels of hardware
designs at runtime'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10626'
author:
- first_name: Christian
full_name: Bick, Christian
last_name: Bick
citation:
ama: Bick C. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte
Datenflussrechner. Paderborn University; 2013.
apa: Bick, C. (2013). Beschleunigung von Tiefenberechnung aus Stereobildern durch
FPGA-basierte Datenflussrechner. Paderborn University.
bibtex: '@book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern
durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick,
Christian}, year={2013} }'
chicago: Bick, Christian. Beschleunigung von Tiefenberechnung Aus Stereobildern
Durch FPGA-Basierte Datenflussrechner. Paderborn University, 2013.
ieee: C. Bick, Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte
Datenflussrechner. Paderborn University, 2013.
mla: Bick, Christian. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch
FPGA-Basierte Datenflussrechner. Paderborn University, 2013.
short: C. Bick, Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte
Datenflussrechner, Paderborn University, 2013.
date_created: 2019-07-10T09:40:24Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10634'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Barbara
full_name: Nofen, Barbara
last_name: Nofen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Nofen B, Platzner M. Improving transient state myoelectric signal
recognition in hand movement classification using gyroscopes. In: Proc. IEEE
Int. Conf. Eng. Med. Biolog. (EMBC). ; 2013.'
apa: Boschmann, A., Nofen, B., & Platzner, M. (2013). Improving transient state
myoelectric signal recognition in hand movement classification using gyroscopes.
In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC).
bibtex: '@inproceedings{Boschmann_Nofen_Platzner_2013, title={Improving transient
state myoelectric signal recognition in hand movement classification using gyroscopes},
booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann,
Alexander and Nofen, Barbara and Platzner, Marco}, year={2013} }'
chicago: Boschmann, Alexander, Barbara Nofen, and Marco Platzner. “Improving Transient
State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.”
In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.
ieee: A. Boschmann, B. Nofen, and M. Platzner, “Improving transient state myoelectric
signal recognition in hand movement classification using gyroscopes,” in Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.
mla: Boschmann, Alexander, et al. “Improving Transient State Myoelectric Signal
Recognition in Hand Movement Classification Using Gyroscopes.” Proc. IEEE Int.
Conf. Eng. Med. Biolog. (EMBC), 2013.
short: 'A. Boschmann, B. Nofen, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med.
Biolog. (EMBC), 2013.'
date_created: 2019-07-10T11:03:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)
status: public
title: Improving transient state myoelectric signal recognition in hand movement classification
using gyroscopes
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10635'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. Reducing the limb position effect in pattern recognition
based myoelectric control using a high density electrode array. In: Proc. IEEE
ISSNIP Biosignals and Biorobotics Conference (BRC). ; 2013.'
apa: Boschmann, A., & Platzner, M. (2013). Reducing the limb position effect
in pattern recognition based myoelectric control using a high density electrode
array. In Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC).
bibtex: '@inproceedings{Boschmann_Platzner_2013, title={Reducing the limb position
effect in pattern recognition based myoelectric control using a high density electrode
array}, booktitle={Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC)},
author={Boschmann, Alexander and Platzner, Marco}, year={2013} }'
chicago: Boschmann, Alexander, and Marco Platzner. “Reducing the Limb Position Effect
in Pattern Recognition Based Myoelectric Control Using a High Density Electrode
Array.” In Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC),
2013.
ieee: A. Boschmann and M. Platzner, “Reducing the limb position effect in pattern
recognition based myoelectric control using a high density electrode array,” in
Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.
mla: Boschmann, Alexander, and Marco Platzner. “Reducing the Limb Position Effect
in Pattern Recognition Based Myoelectric Control Using a High Density Electrode
Array.” Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC),
2013.
short: 'A. Boschmann, M. Platzner, in: Proc. IEEE ISSNIP Biosignals and Biorobotics
Conference (BRC), 2013.'
date_created: 2019-07-10T11:03:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC)
status: public
title: Reducing the limb position effect in pattern recognition based myoelectric
control using a high density electrode array
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10655'
author:
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christopher
full_name: Assad, Christopher
last_name: Assad
- first_name: Michael
full_name: Wolf, Michael
last_name: Wolf
citation:
ama: 'Glette K, Kaufmann P, Assad C, Wolf M. Investigating Evolvable Hardware Classification
for the BioSleeve Electromyographic Interface. In: IEEE Intl. Conf. on Evolvable
Systems (ICES). Vol 1. LNCS. Springer; 2013:1-1.'
apa: Glette, K., Kaufmann, P., Assad, C., & Wolf, M. (2013). Investigating Evolvable
Hardware Classification for the BioSleeve Electromyographic Interface. In IEEE
Intl. Conf. on Evolvable Systems (ICES) (Vol. 1, pp. 1–1). Springer.
bibtex: '@inproceedings{Glette_Kaufmann_Assad_Wolf_2013, series={LNCS}, title={Investigating
Evolvable Hardware Classification for the BioSleeve Electromyographic Interface},
volume={1}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer},
author={Glette, Kyrre and Kaufmann, Paul and Assad, Christopher and Wolf, Michael},
year={2013}, pages={1–1}, collection={LNCS} }'
chicago: Glette, Kyrre, Paul Kaufmann, Christopher Assad, and Michael Wolf. “Investigating
Evolvable Hardware Classification for the BioSleeve Electromyographic Interface.”
In IEEE Intl. Conf. on Evolvable Systems (ICES), 1:1–1. LNCS. Springer,
2013.
ieee: K. Glette, P. Kaufmann, C. Assad, and M. Wolf, “Investigating Evolvable Hardware
Classification for the BioSleeve Electromyographic Interface,” in IEEE Intl.
Conf. on Evolvable Systems (ICES), 2013, vol. 1, pp. 1–1.
mla: Glette, Kyrre, et al. “Investigating Evolvable Hardware Classification for
the BioSleeve Electromyographic Interface.” IEEE Intl. Conf. on Evolvable Systems
(ICES), vol. 1, Springer, 2013, pp. 1–1.
short: 'K. Glette, P. Kaufmann, C. Assad, M. Wolf, in: IEEE Intl. Conf. on Evolvable
Systems (ICES), Springer, 2013, pp. 1–1.'
date_created: 2019-07-10T11:13:16Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: ' 1'
page: 1-1
publication: IEEE Intl. Conf. on Evolvable Systems (ICES)
publisher: Springer
series_title: LNCS
status: public
title: Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic
Interface
type: conference
user_id: '3118'
volume: 1
year: '2013'
...
---
_id: '10681'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag; 2013.'
apa: 'Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag.'
bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
Means of Multi-Objective Evolution}, publisher={Logos Verlag}, author={Kaufmann,
Paul}, year={2013} }'
chicago: 'Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag, 2013.'
ieee: 'P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag, 2013.'
mla: Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Logos Verlag, 2013.
short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
Logos Verlag, Berlin, 2013.
date_created: 2019-07-10T11:27:24Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
place: Berlin
publisher: Logos Verlag
status: public
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: book
user_id: '3118'
year: '2013'
...
---
_id: '10684'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Tiemo
full_name: Gruber, Tiemo
last_name: Gruber
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Bernhard
full_name: Sick, Bernhard
last_name: Sick
citation:
ama: 'Kaufmann P, Glette K, Gruber T, Platzner M, Torresen J, Sick B. Classification
of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers.
IEEE Transactions on Evolutionary Computation. 2013;17(1):46-63. doi:10.1109/TEVC.2012.2185845'
apa: 'Kaufmann, P., Glette, K., Gruber, T., Platzner, M., Torresen, J., & Sick,
B. (2013). Classification of Electromyographic Signals: Comparing Evolvable Hardware
to Conventional Classifiers. IEEE Transactions on Evolutionary Computation,
17(1), 46–63. https://doi.org/10.1109/TEVC.2012.2185845'
bibtex: '@article{Kaufmann_Glette_Gruber_Platzner_Torresen_Sick_2013, title={Classification
of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers},
volume={17}, DOI={10.1109/TEVC.2012.2185845},
number={1}, journal={IEEE Transactions on Evolutionary Computation}, author={Kaufmann,
Paul and Glette, Kyrre and Gruber, Tiemo and Platzner, Marco and Torresen, Jim
and Sick, Bernhard}, year={2013}, pages={46–63} }'
chicago: 'Kaufmann, Paul, Kyrre Glette, Tiemo Gruber, Marco Platzner, Jim Torresen,
and Bernhard Sick. “Classification of Electromyographic Signals: Comparing Evolvable
Hardware to Conventional Classifiers.” IEEE Transactions on Evolutionary Computation
17, no. 1 (2013): 46–63. https://doi.org/10.1109/TEVC.2012.2185845.'
ieee: 'P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, and B. Sick,
“Classification of Electromyographic Signals: Comparing Evolvable Hardware to
Conventional Classifiers,” IEEE Transactions on Evolutionary Computation,
vol. 17, no. 1, pp. 46–63, 2013.'
mla: 'Kaufmann, Paul, et al. “Classification of Electromyographic Signals: Comparing
Evolvable Hardware to Conventional Classifiers.” IEEE Transactions on Evolutionary
Computation, vol. 17, no. 1, 2013, pp. 46–63, doi:10.1109/TEVC.2012.2185845.'
short: P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, B. Sick, IEEE
Transactions on Evolutionary Computation 17 (2013) 46–63.
date_created: 2019-07-10T11:27:28Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/TEVC.2012.2185845
intvolume: ' 17'
issue: '1'
language:
- iso: eng
page: 46-63
publication: IEEE Transactions on Evolutionary Computation
status: public
title: 'Classification of Electromyographic Signals: Comparing Evolvable Hardware
to Conventional Classifiers'
type: journal_article
user_id: '398'
volume: 17
year: '2013'
...
---
_id: '10700'
author:
- first_name: Michael
full_name: Knoop, Michael
last_name: Knoop
citation:
ama: Knoop M. Behavior Models for Electric Vehicles. IWES Kassel; 2013.
apa: Knoop, M. (2013). Behavior Models for Electric Vehicles. IWES Kassel.
bibtex: '@book{Knoop_2013, title={Behavior Models for Electric Vehicles}, publisher={IWES
Kassel}, author={Knoop, Michael}, year={2013} }'
chicago: Knoop, Michael. Behavior Models for Electric Vehicles. IWES Kassel,
2013.
ieee: M. Knoop, Behavior Models for Electric Vehicles. IWES Kassel, 2013.
mla: Knoop, Michael. Behavior Models for Electric Vehicles. IWES Kassel,
2013.
short: M. Knoop, Behavior Models for Electric Vehicles, IWES Kassel, 2013.
date_created: 2019-07-10T11:38:26Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: IWES Kassel
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Behavior Models for Electric Vehicles
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10720'
author:
- first_name: Barbara
full_name: Nofen, Barbara
last_name: Nofen
citation:
ama: Nofen B. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation
von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University;
2013.
apa: Nofen, B. (2013). Verbesserung der Erkennungsrate eines Systems zur Klassifikation
von EMG-Signalen durch den Einsatz eines hybriden Lagesensors. Paderborn University.
bibtex: '@book{Nofen_2013, title={Verbesserung der Erkennungsrate eines Systems
zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors},
publisher={Paderborn University}, author={Nofen, Barbara}, year={2013} }'
chicago: Nofen, Barbara. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation
von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University,
2013.
ieee: B. Nofen, Verbesserung der Erkennungsrate eines Systems zur Klassifikation
von EMG-Signalen durch den Einsatz eines hybriden Lagesensors. Paderborn University,
2013.
mla: Nofen, Barbara. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation
von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University,
2013.
short: B. Nofen, Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation
von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors, Paderborn University,
2013.
date_created: 2019-07-10T11:52:50Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen
durch den Einsatz eines hybriden Lagesensors
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10727'
author:
- first_name: Daniel
full_name: Pudelko, Daniel
last_name: Pudelko
citation:
ama: Pudelko D. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten
Eines Platform FPGAs. Paderborn University; 2013.
apa: Pudelko, D. (2013). Überquerung der Styx - Betriebsparametervariation und
Fehlerverhalten eines Platform FPGAs. Paderborn University.
bibtex: '@book{Pudelko_2013, title={Überquerung der Styx - Betriebsparametervariation
und Fehlerverhalten eines Platform FPGAs}, publisher={Paderborn University}, author={Pudelko,
Daniel}, year={2013} }'
chicago: Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und
Fehlerverhalten Eines Platform FPGAs. Paderborn University, 2013.
ieee: D. Pudelko, Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten
eines Platform FPGAs. Paderborn University, 2013.
mla: Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten
Eines Platform FPGAs. Paderborn University, 2013.
short: D. Pudelko, Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten
Eines Platform FPGAs, Paderborn University, 2013.
date_created: 2019-07-10T11:54:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines
Platform FPGAs
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10730'
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
citation:
ama: Riebler H. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln
Mit FPGAs. Paderborn University; 2013.
apa: Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen
Schlüsseln mit FPGAs. Paderborn University.
bibtex: '@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen
Schlüsseln mit FPGAs}, publisher={Paderborn University}, author={Riebler, Heinrich},
year={2013} }'
chicago: Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen
Schlüsseln Mit FPGAs. Paderborn University, 2013.
ieee: H. Riebler, Identifikation und Wiederherstellung von kryptographischen
Schlüsseln mit FPGAs. Paderborn University, 2013.
mla: Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen
Schlüsseln Mit FPGAs. Paderborn University, 2013.
short: H. Riebler, Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln
Mit FPGAs, Paderborn University, 2013.
date_created: 2019-07-10T11:54:49Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs
type: mastersthesis
user_id: '3118'
year: '2013'
...
---
_id: '10741'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
last_name: Sprenger
citation:
ama: 'Sprenger A. MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung.
Paderborn University; 2013.'
apa: 'Sprenger, A. (2013). MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung.
Paderborn University.'
bibtex: '@book{Sprenger_2013, title={MiBenchHybrid : Erweiterung eines Benchmarks
um Hardwarebeschleunigung}, publisher={Paderborn University}, author={Sprenger,
Alexander}, year={2013} }'
chicago: 'Sprenger, Alexander. MiBenchHybrid : Erweiterung Eines Benchmarks Um
Hardwarebeschleunigung. Paderborn University, 2013.'
ieee: 'A. Sprenger, MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung.
Paderborn University, 2013.'
mla: 'Sprenger, Alexander. MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung.
Paderborn University, 2013.'
short: 'A. Sprenger, MiBenchHybrid : Erweiterung Eines Benchmarks Um Hardwarebeschleunigung,
Paderborn University, 2013.'
date_created: 2019-07-10T11:59:40Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: 'MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung'
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10743'
author:
- first_name: Philipp
full_name: Steppeler, Philipp
last_name: Steppeler
citation:
ama: Steppeler P. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss
Basierenden HPC Systemen. Paderborn University; 2013.
apa: Steppeler, P. (2013). Beschleunigung von Einzelbild-Erkennungsverfahren
auf Datenfluss basierenden HPC Systemen. Paderborn University.
bibtex: '@book{Steppeler_2013, title={Beschleunigung von Einzelbild-Erkennungsverfahren
auf Datenfluss basierenden HPC Systemen}, publisher={Paderborn University}, author={Steppeler,
Philipp}, year={2013} }'
chicago: Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren
Auf Datenfluss Basierenden HPC Systemen. Paderborn University, 2013.
ieee: P. Steppeler, Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss
basierenden HPC Systemen. Paderborn University, 2013.
mla: Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren Auf
Datenfluss Basierenden HPC Systemen. Paderborn University, 2013.
short: P. Steppeler, Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss
Basierenden HPC Systemen, Paderborn University, 2013.
date_created: 2019-07-10T12:00:44Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden
HPC Systemen
type: bachelorsthesis
user_id: '3118'
year: '2013'
...
---
_id: '10745'
author:
- first_name: Christian
full_name: Toebermann, Christian
last_name: Toebermann
- first_name: Daniel
full_name: Geibel, Daniel
last_name: Geibel
- first_name: Manuel
full_name: Hau, Manuel
last_name: Hau
- first_name: Ron
full_name: Brandl, Ron
last_name: Brandl
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Chenjie
full_name: Ma, Chenjie
last_name: Ma
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
- first_name: Tobias
full_name: Degner, Tobias
last_name: Degner
citation:
ama: 'Toebermann C, Geibel D, Hau M, et al. Real-Time Simulation of Distribution
Grids with high Penetration of Regenerative and Distributed Generation. In: Real-Time
Conference. OPAL RT Paris; 2013.'
apa: Toebermann, C., Geibel, D., Hau, M., Brandl, R., Kaufmann, P., Ma, C., … Degner,
T. (2013). Real-Time Simulation of Distribution Grids with high Penetration of
Regenerative and Distributed Generation. In Real-Time Conference. OPAL
RT Paris.
bibtex: '@inproceedings{Toebermann_Geibel_Hau_Brandl_Kaufmann_Ma_Braun_Degner_2013,
title={Real-Time Simulation of Distribution Grids with high Penetration of Regenerative
and Distributed Generation}, booktitle={Real-Time Conference}, publisher={OPAL
RT Paris}, author={Toebermann, Christian and Geibel, Daniel and Hau, Manuel and
Brandl, Ron and Kaufmann, Paul and Ma, Chenjie and Braun, Martin and Degner, Tobias},
year={2013} }'
chicago: Toebermann, Christian, Daniel Geibel, Manuel Hau, Ron Brandl, Paul Kaufmann,
Chenjie Ma, Martin Braun, and Tobias Degner. “Real-Time Simulation of Distribution
Grids with High Penetration of Regenerative and Distributed Generation.” In Real-Time
Conference. OPAL RT Paris, 2013.
ieee: C. Toebermann et al., “Real-Time Simulation of Distribution Grids with
high Penetration of Regenerative and Distributed Generation,” in Real-Time
Conference, 2013.
mla: Toebermann, Christian, et al. “Real-Time Simulation of Distribution Grids with
High Penetration of Regenerative and Distributed Generation.” Real-Time Conference,
OPAL RT Paris, 2013.
short: 'C. Toebermann, D. Geibel, M. Hau, R. Brandl, P. Kaufmann, C. Ma, M. Braun,
T. Degner, in: Real-Time Conference, OPAL RT Paris, 2013.'
date_created: 2019-07-10T12:01:51Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: Real-Time Conference
publisher: OPAL RT Paris
status: public
title: Real-Time Simulation of Distribution Grids with high Penetration of Regenerative
and Distributed Generation
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10774'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based
methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE
International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2013). A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS) (pp. 83–88). IEEE. https://doi.org/10.1109/DFT.2013.6653587
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2013,
title={A fast TCAD-based methodology for Variation analysis of emerging nano-devices},
DOI={10.1109/DFT.2013.6653587},
booktitle={2013 IEEE International Symposium on Defect and Fault Tolerance in
VLSI and Nanotechnology Systems (DFTS)}, publisher={IEEE}, author={Ghasemzadeh
Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli,
Giovanni}, year={2013}, pages={83–88} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “A Fast TCAD-Based Methodology for Variation Analysis
of Emerging Nano-Devices.” In 2013 IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 83–88. IEEE, 2013.
https://doi.org/10.1109/DFT.2013.6653587.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“A fast TCAD-based methodology for Variation analysis of emerging nano-devices,”
in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS), 2013, pp. 83–88.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation
Analysis of Emerging Nano-Devices.” 2013 IEEE International Symposium on Defect
and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013,
pp. 83–88, doi:10.1109/DFT.2013.6653587.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS), IEEE, 2013, pp. 83–88.'
date_created: 2019-07-10T12:10:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2013.6653587
extern: '1'
language:
- iso: eng
page: 83-88
publication: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS)
publisher: IEEE
status: public
title: A fast TCAD-based methodology for Variation analysis of emerging nano-devices
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10775'
author:
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study. In:
2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673'
apa: 'Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013).
Vertically-stacked silicon nanowire transistors with controllable polarity: A
robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6).
IEEE. https://doi.org/10.1109/LATW.2013.6562673'
bibtex: '@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study},
DOI={10.1109/LATW.2013.6562673},
booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon,
Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013},
pages={1–6} }'
chicago: 'Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni
De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable
Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW,
1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.'
ieee: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study,”
in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.'
mla: 'Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors
with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test
Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.'
short: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th
Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.'
date_created: 2019-07-10T12:10:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/LATW.2013.6562673
extern: '1'
language:
- iso: eng
page: 1-6
publication: 2013 14th Latin American Test Workshop-LATW
publisher: IEEE
status: public
title: 'Vertically-stacked silicon nanowire transistors with controllable polarity:
A robustness study'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '13645'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proceedings of the International Conference on Computers and Games (CG).
Springer; 2013.'
apa: Graf, T., Schäfers, L., & Platzner, M. (2013). On Semeai Detection in Monte-Carlo
Go. In Proceedings of the International Conference on Computers and Games (CG).
Springer.
bibtex: '@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection
in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on
Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers,
Lars and Platzner, Marco}, year={2013} }'
chicago: Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in
Monte-Carlo Go.” In Proceedings of the International Conference on Computers
and Games (CG). Springer, 2013.
ieee: T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go.,” in Proceedings of the International Conference on Computers and Games
(CG), 2013.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings
of the International Conference on Computers and Games (CG), Springer, 2013.
short: 'T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International
Conference on Computers and Games (CG), Springer, 2013.'
date_created: 2019-10-04T22:50:51Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Conference on Computers and Games (CG)
publisher: Springer
status: public
title: On Semeai Detection in Monte-Carlo Go.
type: conference
user_id: '398'
year: '2013'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '505'
abstract:
- lang: eng
text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT
services that will be provided by assembling modular software components available
on world-wide markets. After suitable components have been found, they are automatically
integrated, configured and brought to execution in an On-The-Fly Compute Center.
We envision that these future compute centers will continue to leverage three
current trends in large scale computing which are an increasing amount of parallel
processing, a trend to use heterogeneous computing resources, and—in the light
of rising energy cost—energy-efficiency as a primary goal in the design and operation
of computing systems. In this paper, we point out three research challenges and
our current work in these areas.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
citation:
ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings
of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous
Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232'
apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide,
F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232'
bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232},
booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus
and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide,
Friedhelm}, year={2013} }'
chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm
Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology
for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.'
ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.'
mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for
Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.'
short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in:
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS), IEEE, 2013.'
date_created: 2017-10-17T12:42:30Z
date_updated: 2023-09-26T13:38:20Z
ddc:
- '040'
department:
- _id: '63'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISORC.2013.6913232
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T13:38:56Z
date_updated: 2018-03-15T13:38:56Z
file_id: '1308'
file_name: 505-Plessl13_seus.pdf
file_size: 1040834
relation: main_file
success: 1
file_date_updated: 2018-03-15T13:38:56Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services'
type: conference
user_id: '15278'
year: '2013'
...