---
_id: '13642'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. A Self-Reconfigurable Lightweight Interconnect for
Scalable Processor Fabrics. In: Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010.'
apa: Giefers, H., & Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics. In Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@inproceedings{Giefers_Platzner_2010, title={A Self-Reconfigurable Lightweight
Interconnect for Scalable Processor Fabrics}, booktitle={Proceedings of the 10th
International Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA)}, publisher={CSREA Press}, author={Giefers, Heiner and Platzner, Marco},
year={2010} }'
chicago: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight
Interconnect for Scalable Processor Fabrics.” In Proceedings of the 10th International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA).
CSREA Press, 2010.
ieee: H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010.
mla: Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect
for Scalable Processor Fabrics.” Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010.
short: 'H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.'
date_created: 2019-10-04T22:37:54Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 10th International Conference on Engineering of Reconfigurable
Systems and Algorithms (ERSA)
publisher: CSREA Press
status: public
title: A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
type: conference
user_id: '398'
year: '2010'
...
---
_id: '2223'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
citation:
ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking
for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010:225-231.'
apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010).
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
225–231.
bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards
Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller,
Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }'
chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard
Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable
Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 225–31. CSREA Press, 2010.
ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive
Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2010, pp. 225–231.
mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based
on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010, pp. 225–231.'
date_created: 2018-04-05T16:27:13Z
date_updated: 2023-09-26T13:48:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 225-231
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2216'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization.
In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19'
apa: Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time
Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs
(ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19
bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning
the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian},
year={2010}, pages={67–72} }'
chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010.
https://doi.org/10.1109/ReConFig.2010.19.'
ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor
Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig),
2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.'
mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.'
date_created: 2018-04-05T14:48:51Z
date_updated: 2023-09-26T13:47:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2010.19
language:
- iso: eng
page: 67-72
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Pruning the Design Space for Just-In-Time Processor Customization
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2224'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:144-150.'
apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking
Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 144–150.
bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library
with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz
and Plessl, Christian}, year={2010}, pages={144–150} }'
chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with
Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.
ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2010, pp. 144–150.
mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking
Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.'
date_created: 2018-04-05T16:28:38Z
date_updated: 2023-09-26T13:48:59Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 144-150
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: An Open Source Circuit Library with Benchmarking Facilities
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2220'
author:
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:165.'
apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures:
History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165.'
bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures:
History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David
and Plessl, Christian}, year={2010}, pages={165} }'
chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165. CSREA Press, 2010.'
ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History
and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 2010, p. 165.'
mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
date_created: 2018-04-05T14:57:07Z
date_updated: 2023-09-26T13:47:33Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: '165'
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Configurable Processor Architectures: History and Trends'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2222'
citation:
ama: Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.
apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &
Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, year={2010} }'
chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
ieee: T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
mla: Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
full_name: Plaks, Toomas P.
last_name: Plaks
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Ronald
full_name: DeMara, Ronald
last_name: DeMara
- first_name: Herman
full_name: Lam, Herman
last_name: Lam
- first_name: Jooheung
full_name: Lee, Jooheung
last_name: Lee
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Greg
full_name: Stitt, Greg
last_name: Stitt
language:
- iso: eng
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Manuel
full_name: Niekamp, Manuel
last_name: Niekamp
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798'
apa: Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing
for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798
bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators}, DOI={10.1109/ASAP.2010.5540798},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures,
and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.
ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.'
mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010,
pp. 65–72, doi:10.1109/ASAP.2010.5540798.
short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publication_identifier:
isbn:
- 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future
(FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341'
apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010).
Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network
of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341
bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341},
booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom
Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.
ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the
Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.'
mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc.
IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp.
372–76, doi:10.1109/GLOCOMW.2010.5700341.
short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
isbn:
- 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA). ; 2010.'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance
Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
& S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping
(WARP), International Symposium on Computer Architecture (ISCA).
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
Workshop on Architectural Research Prototyping (WARP), International Symposium
on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
Sandra}, year={2010} }'
chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
In Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra
Larrabee, 2010.
ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on
Architectural Research Prototyping (WARP), International Symposium on Computer
Architecture (ISCA), 2010.
mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP),
International Symposium on Computer Architecture (ISCA), edited by Omar Hammami
and Sandra Larrabee, 2010.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
(Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
full_name: Hammami, Omar
last_name: Hammami
- first_name: Sandra
full_name: Larrabee, Sandra
last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '10639'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Michael
full_name: Winkler, Michael
last_name: Winkler
citation:
ama: 'Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand
prostheses: Combining adaptive classification with high precision sockets. In:
Proc. Technically Assisted Rehabilitation (TAR). ; 2009.'
apa: 'Boschmann, A., Kaufmann, P., Platzner, M., & Winkler, M. (2009). Towards
multi-movement hand prostheses: Combining adaptive classification with high precision
sockets. In Proc. Technically Assisted Rehabilitation (TAR).'
bibtex: '@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards
multi-movement hand prostheses: Combining adaptive classification with high precision
sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann,
Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009}
}'
chicago: 'Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler.
“Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with
High Precision Sockets.” In Proc. Technically Assisted Rehabilitation (TAR),
2009.'
ieee: 'A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement
hand prostheses: Combining adaptive classification with high precision sockets,”
in Proc. Technically Assisted Rehabilitation (TAR), 2009.'
mla: 'Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining
Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted
Rehabilitation (TAR), 2009.'
short: 'A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically
Assisted Rehabilitation (TAR), 2009.'
date_created: 2019-07-10T11:03:25Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. Technically Assisted Rehabilitation (TAR)
status: public
title: 'Towards multi-movement hand prostheses: Combining adaptive classification
with high precision sockets'
type: conference
user_id: '3118'
year: '2009'
...
---
_id: '10702'
author:
- first_name: Alexander
full_name: Kostin, Alexander
last_name: Kostin
citation:
ama: Kostin A. Evolvable Robot Controller. Paderborn University; 2009.
apa: Kostin, A. (2009). Evolvable Robot Controller. Paderborn University.
bibtex: '@book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn
University}, author={Kostin, Alexander}, year={2009} }'
chicago: Kostin, Alexander. Evolvable Robot Controller. Paderborn University,
2009.
ieee: A. Kostin, Evolvable Robot Controller. Paderborn University, 2009.
mla: Kostin, Alexander. Evolvable Robot Controller. Paderborn University,
2009.
short: A. Kostin, Evolvable Robot Controller, Paderborn University, 2009.
date_created: 2019-07-10T11:38:28Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Evolvable Robot Controller
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10703'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable
Computers. ACM Transactions on Embedded Computing Systems. 2009;9(1):8:1-8:33.
doi:10.1145/1596532.1596540'
apa: 'Lübbers, E., & Platzner, M. (2009). ReconOS: Multithreaded Programming
for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems,
9(1), 8:1-8:33. https://doi.org/10.1145/1596532.1596540'
bibtex: '@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming
for Reconfigurable Computers}, volume={9}, DOI={10.1145/1596532.1596540},
number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers,
Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }'
chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming
for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems
9, no. 1 (2009): 8:1-8:33. https://doi.org/10.1145/1596532.1596540.'
ieee: 'E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable
Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no.
1, pp. 8:1-8:33, 2009.'
mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for
Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems,
vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.'
short: E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9
(2009) 8:1-8:33.
date_created: 2019-07-10T11:41:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1145/1596532.1596540
intvolume: ' 9'
issue: '1'
keyword:
- Reconfigurable computing
- multithreading
- operating systems
language:
- iso: eng
page: 8:1-8:33
publication: ACM Transactions on Embedded Computing Systems
publication_identifier:
issn:
- 1539-9087
status: public
title: 'ReconOS: Multithreaded Programming for Reconfigurable Computers'
type: journal_article
user_id: '3118'
volume: 9
year: '2009'
...
---
_id: '10746'
author:
- first_name: Martin
full_name: Tofall, Martin
last_name: Tofall
citation:
ama: Tofall M. Compiler for a Custom Instruction Set CPU. Paderborn University;
2009.
apa: Tofall, M. (2009). Compiler for a Custom Instruction Set CPU. Paderborn
University.
bibtex: '@book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn
University}, author={Tofall, Martin}, year={2009} }'
chicago: Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn
University, 2009.
ieee: M. Tofall, Compiler for a Custom Instruction Set CPU. Paderborn University,
2009.
mla: Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn
University, 2009.
short: M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University,
2009.
date_created: 2019-07-10T12:01:52Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Compiler for a Custom Instruction Set CPU
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10749'
author:
- first_name: Alexander
full_name: Warkentin, Alexander
last_name: Warkentin
citation:
ama: Warkentin A. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional
Units. Paderborn University; 2009.
apa: Warkentin, A. (2009). Coarse-grained CGP Model using Xilinx Virtex5 DSP48E
Functional Units. Paderborn University.
bibtex: '@book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5
DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin,
Alexander}, year={2009} }'
chicago: Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5
DSP48E Functional Units. Paderborn University, 2009.
ieee: A. Warkentin, Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional
Units. Paderborn University, 2009.
mla: Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E
Functional Units. Paderborn University, 2009.
short: A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional
Units, Paderborn University, 2009.
date_created: 2019-07-10T12:02:58Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10753'
author:
- first_name: Benedikt
full_name: Wildenhain, Benedikt
last_name: Wildenhain
citation:
ama: Wildenhain B. Implementierung von Kryptographie-Hardwarebeschleunigern Für
Das HW/SW-Betriebssystem ReconOS. Paderborn University; 2009.
apa: Wildenhain, B. (2009). Implementierung von Kryptographie-Hardwarebeschleunigern
für das HW/SW-Betriebssystem ReconOS. Paderborn University.
bibtex: '@book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern
für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain,
Benedikt}, year={2009} }'
chicago: Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern
Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.
ieee: B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern
für das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.
mla: Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern
Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.
short: B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für
Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.
date_created: 2019-07-10T12:05:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem
ReconOS
type: bachelorsthesis
user_id: '3118'
year: '2009'
...
---
_id: '10777'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Seyed Ghassem
full_name: Miremadi, Seyed Ghassem
last_name: Miremadi
- first_name: Alireza
full_name: Ejlali, Alireza
last_name: Ejlali
citation:
ama: 'Ghasemzadeh Mohammadi H, Miremadi SG, Ejlali A. Signature Self Checking (SSC):
A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In: Dependable
Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On. IEEE;
2009:252-255. doi:10.1109/PRDC.2009.69'
apa: 'Ghasemzadeh Mohammadi, H., Miremadi, S. G., & Ejlali, A. (2009). Signature
Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.
In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
on (pp. 252–255). IEEE. https://doi.org/10.1109/PRDC.2009.69'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Miremadi_Ejlali_2009, title={Signature
Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors},
DOI={10.1109/PRDC.2009.69},
booktitle={Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
on}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed
Ghassem and Ejlali, Alireza}, year={2009}, pages={252–255} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Seyed Ghassem Miremadi, and Alireza Ejlali.
“Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined
Microprocessors.” In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International
Symposium On, 252–55. IEEE, 2009. https://doi.org/10.1109/PRDC.2009.69.'
ieee: 'H. Ghasemzadeh Mohammadi, S. G. Miremadi, and A. Ejlali, “Signature Self
Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors,”
in Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
on, 2009, pp. 252–255.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost
Reliable Control Logic for Pipelined Microprocessors.” Dependable Computing
(PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp.
252–55, doi:10.1109/PRDC.2009.69.'
short: 'H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing
(PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.'
date_created: 2019-07-10T12:11:34Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/PRDC.2009.69
extern: '1'
language:
- iso: eng
page: 252-255
publication: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
on
publisher: IEEE
status: public
title: 'Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined
Microprocessors'
type: conference
user_id: '3118'
year: '2009'
...
---
_id: '13632'
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte
Carlo Methods on CPU/FPGA Platforms. In: Proceedings of the International Workshop
on Applied Reconfigurable Computing (ARC). Springer; 2009.'
apa: Happe, M., Lübbers, E., & Platzner, M. (2009). A Multithreaded Framework
for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In Proceedings of
the International Workshop on Applied Reconfigurable Computing (ARC). Springer.
bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework
for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings
of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer},
author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }'
chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework
for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In Proceedings of
the International Workshop on Applied Reconfigurable Computing (ARC). Springer,
2009.
ieee: M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential
Monte Carlo Methods on CPU/FPGA Platforms,” in Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), 2009.
mla: Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo
Methods on CPU/FPGA Platforms.” Proceedings of the International Workshop on
Applied Reconfigurable Computing (ARC), Springer, 2009.
short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.'
date_created: 2019-10-04T22:13:24Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC)
publisher: Springer
status: public
title: A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13634'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable
Mesh. In: Proceedings of the Workshop on Many-Cores, International Conference
on Architecture of Computing Systems (ARCS). ; 2009.'
apa: 'Giefers, H., & Platzner, M. (2009). Towards Models for Many-Cores: The
Case for the Reconfigurable Mesh. In Proceedings of the Workshop on Many-Cores,
International Conference on Architecture of Computing Systems (ARCS).'
bibtex: '@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores:
The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop
on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)},
author={Giefers, Heiner and Platzner, Marco}, year={2009} }'
chicago: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The
Case for the Reconfigurable Mesh.” In Proceedings of the Workshop on Many-Cores,
International Conference on Architecture of Computing Systems (ARCS), 2009.'
ieee: 'H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for
the Reconfigurable Mesh,” in Proceedings of the Workshop on Many-Cores, International
Conference on Architecture of Computing Systems (ARCS), 2009.'
mla: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case
for the Reconfigurable Mesh.” Proceedings of the Workshop on Many-Cores, International
Conference on Architecture of Computing Systems (ARCS), 2009.'
short: 'H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores,
International Conference on Architecture of Computing Systems (ARCS), 2009.'
date_created: 2019-10-04T22:16:01Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the Workshop on Many-Cores, International Conference on
Architecture of Computing Systems (ARCS)
status: public
title: 'Towards Models for Many-Cores: The Case for the Reconfigurable Mesh'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13635'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable
Mesh Many-Cores. In: Reconfigurable Architectures Workshop (RAW), Proceedings
of the International Parallel and Distributed Processing Symposium. IEEE;
2009.'
apa: 'Giefers, H., & Platzner, M. (2009). ARMLang: A Language and Compiler for
Programming Reconfigurable Mesh Many-Cores. In Reconfigurable Architectures
Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
Symposium. IEEE.'
bibtex: '@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler
for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures
Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009}
}'
chicago: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler
for Programming Reconfigurable Mesh Many-Cores.” In Reconfigurable Architectures
Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
Symposium. IEEE, 2009.'
ieee: 'H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming
Reconfigurable Mesh Many-Cores,” in Reconfigurable Architectures Workshop (RAW),
Proceedings of the International Parallel and Distributed Processing Symposium,
2009.'
mla: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for
Programming Reconfigurable Mesh Many-Cores.” Reconfigurable Architectures Workshop
(RAW), Proceedings of the International Parallel and Distributed Processing Symposium,
IEEE, 2009.'
short: 'H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW),
Proceedings of the International Parallel and Distributed Processing Symposium,
IEEE, 2009.'
date_created: 2019-10-04T22:17:57Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Reconfigurable Architectures Workshop (RAW), Proceedings of the International
Parallel and Distributed Processing Symposium
publisher: IEEE
status: public
title: 'ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13636'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable
Systems. In: Proceedings of the 19th International Workshop on Field Programmable
Logic and Applications (FPL) . IEEE; 2009.'
apa: Lübbers, E., & Platzner, M. (2009). Cooperative Multithreading in Dynamically
Reconfigurable Systems. In Proceedings of the 19th International Workshop on
Field Programmable Logic and Applications (FPL) . IEEE.
bibtex: '@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading
in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International
Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE},
author={Lübbers, Enno and Platzner, Marco}, year={2009} }'
chicago: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically
Reconfigurable Systems.” In Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) . IEEE, 2009.
ieee: E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable
Systems,” in Proceedings of the 19th International Workshop on Field Programmable
Logic and Applications (FPL) , 2009.
mla: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically
Reconfigurable Systems.” Proceedings of the 19th International Workshop on
Field Programmable Logic and Applications (FPL) , IEEE, 2009.
short: 'E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , IEEE, 2009.'
date_created: 2019-10-04T22:20:12Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: 'Proceedings of the 19th International Workshop on Field Programmable
Logic and Applications (FPL) '
publisher: IEEE
status: public
title: Cooperative Multithreading in Dynamically Reconfigurable Systems
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13637'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. Program-driven Fine-grained Power Management for the
Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on
Field Programmable Logic and Applications (FPL) . IEEE; 2009.'
apa: Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management
for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) . IEEE.
bibtex: '@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained
Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th
International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE},
author={Giefers, Heiner and Platzner, Marco}, year={2009} }'
chicago: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power
Management for the Reconfigurable Mesh.” In Proceedings of the 19th International
Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009.
ieee: H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management
for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , 2009.
mla: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management
for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , IEEE, 2009.
short: 'H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop
on Field Programmable Logic and Applications (FPL) , IEEE, 2009.'
date_created: 2019-10-04T22:22:02Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: 'Proceedings of the 19th International Workshop on Field Programmable
Logic and Applications (FPL) '
publisher: IEEE
status: public
title: Program-driven Fine-grained Power Management for the Reconfigurable Mesh
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13638'
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework
with runtime HW/SW repartitioning. In: Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645'
apa: Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte
Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009
International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645
bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential
Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645},
booktitle={Proceedings of the 2009 International Conference on Field-Programmable
Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and
Platzner, Marco}, year={2009} }'
chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential
Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of
the 2009 International Conference on Field-Programmable Technology (FPT).
IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645.
ieee: M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo
framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT), 2009.
mla: Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime
HW/SW Repartitioning.” Proceedings of the 2009 International Conference on
Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645.
short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International
Conference on Field-Programmable Technology (FPT), IEEE, 2009.'
date_created: 2019-10-04T22:22:52Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpt.2009.5377645
language:
- iso: eng
publication: Proceedings of the 2009 International Conference on Field-Programmable
Technology (FPT)
publication_identifier:
isbn:
- '9781424443758'
publication_status: published
publisher: IEEE
status: public
title: An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13639'
author:
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
- first_name: Uwe
full_name: Kastens, Uwe
last_name: Kastens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime
Verification of Reconfigurable Modules. In: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.'
apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware:
Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig).
IEEE.'
bibtex: '@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying
Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner,
Marco}, year={2009} }'
chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying
Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig).
IEEE, 2009.'
ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards
Runtime Verification of Reconfigurable Modules,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.'
mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification
of Reconfigurable Modules.” Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.'
short: 'S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.'
date_created: 2019-10-04T22:25:10Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
status: public
title: 'Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '2350'
abstract:
- lang: eng
text: 'Mapping applications that consist of a collection of cores to FPGA accelerators
and optimizing their performance is a challenging task in high performance reconfigurable
computing. We present IMORC, an architectural template and highly versatile on-chip
interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which
allows for flexibly composing accelerators from cores running at full speed within
their own clock domains, thus facilitating the re-use of cores and portability.
Further, IMORC inserts performance counters for monitoring runtime data. In this
paper, we first introduce the IMORC architectural template and the on-chip interconnect,
and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor
thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s
monitoring infrastructure, we gain insights into the data-dependent behavior of
the application which, in turn, allow for optimizing the accelerator. '
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer
Society; 2009:275-278. doi:10.1109/FCCM.2009.25'
apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–278. https://doi.org/10.1109/FCCM.2009.25'
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing},
DOI={10.1109/FCCM.2009.25},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian
and Platzner, Marco}, year={2009}, pages={275–278} }'
chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.'
ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278,
doi: 10.1109/FCCM.2009.25.'
mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization
for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78,
doi:10.1109/FCCM.2009.25.'
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.'
date_created: 2018-04-16T15:05:52Z
date_updated: 2023-09-26T13:51:44Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2009.25
keyword:
- IMORC
- interconnect
- performance
language:
- iso: eng
page: 275-278
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publication_identifier:
isbn:
- 978-1-4244-4450-2
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance
Reconfigurable Computing'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2262'
abstract:
- lang: eng
text: 'In this work we present EvoCache, a novel approach for implementing application-specific
caches. The key innovation of EvoCache is to make the function that maps memory
addresses from the CPU address space to cache indices programmable. We support
arbitrary Boolean mapping functions that are implemented within a small reconfigurable
logic fabric. For finding suitable cache mapping functions we rely on techniques
from the evolvable hardware domain and utilize an evolutionary optimization procedure.
We evaluate the use of EvoCache in an embedded processor for two specific applications
(JPEG and BZIP2 compression) with respect to execution time, cache miss rate and
energy consumption. We show that the evolvable hardware approach for optimizing
the cache functions not only significantly improves the cache performance for
the training data used during optimization, but that the evolved mapping functions
generalize very well. Compared to a conventional cache architecture, EvoCache
applied to test data achieves a reduction in execution time of up to 14.31% for
JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70%
for BZIP2). We also discuss the integration of EvoCache into the operating system
and show that the area and delay overheads introduced by EvoCache are acceptable. '
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation
of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems
(AHS). IEEE Computer Society; 2009:11-18.'
apa: 'Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific
Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18.'
bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA,
USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc.
NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer
Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009},
pages={11–18} }'
chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific
Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.'
ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific
Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 2009, pp. 11–18.'
mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache
Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS),
IEEE Computer Society, 2009, pp. 11–18.'
short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive
Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009,
pp. 11–18.'
date_created: 2018-04-06T15:18:24Z
date_updated: 2023-09-26T13:53:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- EvoCache
- evolvable hardware
- computer architecture
language:
- iso: eng
page: 11-18
place: Los Alamitos, CA, USA
publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvoCaches: Application-specific Adaptation of Cache Mapping'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2238'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization
for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on
ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124.
doi:10.1109/ReConFig.2009.32'
apa: Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124.
https://doi.org/10.1109/ReConFig.2009.32
bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos,
CA, USA}, title={Communication Performance Characterization for Reconfigurable
Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and
Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }'
chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.”
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24.
Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.'
ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance
Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc.
Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124,
doi: 10.1109/ReConFig.2009.32.'
mla: Schumacher, Tobias, et al. “Communication Performance Characterization for
Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.
short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA,
2009, pp. 119–124.'
date_created: 2018-04-05T17:11:28Z
date_updated: 2023-09-26T13:52:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2009.32
keyword:
- IMORC
- graphics
language:
- iso: eng
page: 119-124
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
isbn:
- 978-0-7695-3917-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Communication Performance Characterization for Reconfigurable Accelerator Design
on the XD1000
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2261'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor
Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL). IEEE; 2009:338-344.'
apa: Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th
Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf.
on Field Programmable Logic and Applications (FPL), 338–344.
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for
k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE},
author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009},
pages={338–344} }'
chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator
for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE,
2009.
ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest
Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on
Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.
mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning
Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–44.
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–344.'
date_created: 2018-04-06T15:15:47Z
date_updated: 2023-09-26T13:52:52Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- NOC
- KNN
- accelerator
language:
- iso: eng
page: 338-344
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publication_identifier:
isbn:
- 978-1-4244-3892-1
issn:
- 1946-1488
publisher: IEEE
quality_controlled: '1'
status: public
title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2263'
abstract:
- lang: eng
text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture.
The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary
Processing Unit (APU) as well as the partial reconfiguration capabilities to provide
dynamically reconfigurable custom instructions. We also present a hardware tool
flow that automatically translates software functions into custom instructions
and a software tool flow that creates binaries using these instructions. While
previous research on processors with reconfigurable functional units has been
performed predominantly with simulation, the Woolcano architecture allows for
exploring dynamic instruction set extension with commercially available hardware.
Finally, we present a case study demonstrating a custom floating-point instruction
generated with our approach, which achieves a 40x speedup over software-emulated
floating-point operations and a 21% speedup over the Xilinx hardware floating-point
unit. '
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction
Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of
Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.'
apa: 'Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.'
bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture
and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322}
}'
chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool
Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
319–22. USA: CSREA Press, 2009.'
ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic
Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.'
mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2009, pp. 319–22.'
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.'
date_created: 2018-04-06T15:19:51Z
date_updated: 2023-09-26T13:53:30Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 319-322
place: USA
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-101-5
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension
on Xilinx Virtex-4 FX'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2358'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Stefan
full_name: Lietsch, Stefan
last_name: Lietsch
- first_name: Kris
full_name: Thielemans, Kris
last_name: Thielemans
citation:
ama: 'Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on
parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference
Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198'
apa: Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET
reconstruction on parallel architectures using STIR. In IEEE Nuclear Science
Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198
bibtex: '@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM
PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198},
booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE},
author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008},
pages={4161–4168} }'
chicago: Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM
PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science
Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198.
ieee: T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction
on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference
Record (NSS), 2008, pp. 4161–4168.
mla: Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures
Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE,
2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198.
short: 'T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium
Conference Record (NSS), IEEE, 2008, pp. 4161–4168.'
date_created: 2018-04-17T10:59:40Z
date_updated: 2022-01-06T06:55:57Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/NSSMIC.2008.4774198
page: 4161-4168
publication: IEEE Nuclear Science Symposium Conference Record (NSS)
publisher: IEEE
status: public
title: A method for OSEM PET reconstruction on parallel architectures using STIR
type: conference
user_id: '24135'
year: '2008'
...
---
_id: '2365'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sven
full_name: Döhre, Sven
last_name: Döhre
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Ulf
full_name: Lorenz, Ulf
last_name: Lorenz
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Andre
full_name: Send, Andre
last_name: Send
- first_name: Alexander
full_name: Warkentin, Alexander
last_name: Warkentin
citation:
ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2008:245-251.'
apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T.,
… Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
(pp. 245–251). CSREA Press.'
bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008,
title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter,
Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander},
year={2008}, pages={245–251} }'
chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz,
Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating
GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 245–51. CSREA Press, 2008.'
ieee: 'M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2008, pp. 245–251.'
mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2008, pp. 245–51.'
short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A.
Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:34:35Z
date_updated: 2022-01-06T06:55:58Z
department:
- _id: '27'
- _id: '78'
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-064-7
publisher: CSREA Press
status: public
title: 'The GOmputer: Accelerating GO with FPGAs'
type: conference
user_id: '24135'
year: '2008'
...
---
_id: '10628'
alternative_title:
- Effects of Pattern Matching Algorithms on Long-term Electromyography Signals
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
citation:
ama: Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation
von EMG-Signalen. Paderborn University; 2008.
apa: Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems
zur Langzeitklassifikation von EMG-Signalen. Paderborn University.
bibtex: '@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines
Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University},
author={Boschmann, Alexander}, year={2008} }'
chicago: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems
Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.
ieee: A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation
von EMG-Signalen. Paderborn University, 2008.
mla: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems
Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.
short: A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation
von EMG-Signalen, Paderborn University, 2008.
date_created: 2019-07-10T09:40:26Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation
von EMG-Signalen
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10641'
alternative_title:
- Self-optimizing Cache Controller
author:
- first_name: Daniel
full_name: Breitlauch, Daniel
last_name: Breitlauch
citation:
ama: Breitlauch D. Selbstoptimierender Cache-Kontroller. Paderborn University;
2008.
apa: Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn
University.
bibtex: '@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn
University}, author={Breitlauch, Daniel}, year={2008} }'
chicago: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn
University, 2008.
ieee: D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University,
2008.
mla: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn
University, 2008.
short: D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University,
2008.
date_created: 2019-07-10T11:03:42Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Selbstoptimierender Cache-Kontroller
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10644'
alternative_title:
- Distributed Simulation of mobile Robots using EyeSim
author:
- first_name: Toni
full_name: Ceylan, Toni
last_name: Ceylan
- first_name: Coni
full_name: Yalcin, Coni
last_name: Yalcin
citation:
ama: Ceylan T, Yalcin C. Verteilte Simulation von Mobilen Robotern Mit EyeSim.
Paderborn University; 2008.
apa: Ceylan, T., & Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern
mit EyeSim. Paderborn University.
bibtex: '@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern
mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin,
Coni}, year={2008} }'
chicago: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern
Mit EyeSim. Paderborn University, 2008.
ieee: T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit
EyeSim. Paderborn University, 2008.
mla: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern
Mit EyeSim. Paderborn University, 2008.
short: T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim,
Paderborn University, 2008.
date_created: 2019-07-10T11:03:45Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Verteilte Simulation von mobilen Robotern mit EyeSim
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10653'
author:
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Thiemo
full_name: Gruber, Thiemo
last_name: Gruber
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Bernhard
full_name: Sick, Bernhard
last_name: Sick
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing
Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic
Hand Control. In: IEEE Adaptive Hardware and Systems (AHS). IEEE; 2008:32-39.'
apa: Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., & Platzner,
M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp.
32–39). IEEE.
bibtex: '@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing
Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic
Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE},
author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim
and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }'
chicago: Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick,
and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers
for Electromyographic Prosthetic Hand Control.” In IEEE Adaptive Hardware and
Systems (AHS), 32–39. IEEE, 2008.
ieee: K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner,
“Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS),
2008, pp. 32–39.
mla: Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers
for Electromyographic Prosthetic Hand Control.” IEEE Adaptive Hardware and
Systems (AHS), IEEE, 2008, pp. 32–39.
short: 'K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in:
IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.'
date_created: 2019-07-10T11:13:13Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 32-39
publication: IEEE Adaptive Hardware and Systems (AHS)
publisher: IEEE
status: public
title: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
Prosthetic Hand Control
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '10656'
author:
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware
Architectures for Classification Tasks. In: IEEE Intl. Conf. on Evolvable Systems
(ICES). Vol 5216. LNCS. Springer; 2008:22-33.'
apa: Glette, K., Torresen, J., Kaufmann, P., & Platzner, M. (2008). A Comparison
of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl.
Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer.
bibtex: '@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A
Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216},
booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer},
author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco},
year={2008}, pages={22–33}, collection={LNCS} }'
chicago: Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison
of Evolvable Hardware Architectures for Classification Tasks.” In IEEE Intl.
Conf. on Evolvable Systems (ICES), 5216:22–33. LNCS. Springer, 2008.
ieee: K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable
Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable
Systems (ICES), 2008, vol. 5216, pp. 22–33.
mla: Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for
Classification Tasks.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol.
5216, Springer, 2008, pp. 22–33.
short: 'K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on
Evolvable Systems (ICES), Springer, 2008, pp. 22–33.'
date_created: 2019-07-10T11:13:31Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: ' 5216'
language:
- iso: eng
page: 22-33
publication: IEEE Intl. Conf. on Evolvable Systems (ICES)
publisher: Springer
series_title: LNCS
status: public
title: A Comparison of Evolvable Hardware Architectures for Classification Tasks
type: conference
user_id: '3118'
volume: 5216
year: '2008'
...
---
_id: '10669'
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
citation:
ama: Happe M. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern.
Paderborn University; 2008.
apa: Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von
Partikelfiltern. Paderborn University.
bibtex: '@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign
von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus},
year={2008} }'
chicago: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign
von Partikelfiltern. Paderborn University, 2008.
ieee: M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern.
Paderborn University, 2008.
mla: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von
Partikelfiltern. Paderborn University, 2008.
short: M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern,
Paderborn University, 2008.
date_created: 2019-07-10T11:15:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern
type: mastersthesis
user_id: '3118'
year: '2008'
...
---
_id: '10690'
author:
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial
at Architecture of Computing Systems (ARCS). 2008.
apa: Torresen, J., Glette, K., Platzner, M., & Kaufmann, P. (2008). Evolvable
Hardware - Tutorial at Architecture of Computing Systems (ARCS).
bibtex: '@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware
- Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim
and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }'
chicago: Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable
Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008.
ieee: J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware
- Tutorial at Architecture of Computing Systems (ARCS).” 2008.
mla: Torresen, Jim, et al. Evolvable Hardware - Tutorial at Architecture of Computing
Systems (ARCS). 2008.
short: J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).
date_created: 2019-07-10T11:29:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
status: public
title: Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)
type: preprint
user_id: '398'
year: '2008'
...
---
_id: '10691'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation
of Modules in Cartesian Genetic Programming. In: Genetic and Evolutionary Computation
(GECCO). ACM Press; 2008:1219-1226.'
apa: Kaufmann, P., & Platzner, M. (2008). Advanced Techniques for the Creation
and Propagation of Modules in Cartesian Genetic Programming. In Genetic and
Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press.
bibtex: '@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the
Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic
and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann,
Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }'
chicago: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation
and Propagation of Modules in Cartesian Genetic Programming.” In Genetic and
Evolutionary Computation (GECCO), 1219–26. ACM Press, 2008.
ieee: P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation
of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation
(GECCO), 2008, pp. 1219–1226.
mla: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and
Propagation of Modules in Cartesian Genetic Programming.” Genetic and Evolutionary
Computation (GECCO), ACM Press, 2008, pp. 1219–26.
short: 'P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO),
ACM Press, 2008, pp. 1219–1226.'
date_created: 2019-07-10T11:29:57Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 1219 - 1226
publication: Genetic and Evolutionary Computation (GECCO)
publisher: ACM Press
status: public
title: Advanced Techniques for the Creation and Propagation of Modules in Cartesian
Genetic Programming
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '10696'
alternative_title:
- Multi-objective Optimizer IBEA for Digital Logic Design
author:
- first_name: Tobias
full_name: Knieper, Tobias
last_name: Knieper
citation:
ama: Knieper T. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University; 2008.
apa: Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen
Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn
University.
bibtex: '@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen
Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn
University}, author={Knieper, Tobias}, year={2008} }'
chicago: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen
Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn
University, 2008.
ieee: T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens
IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008.
mla: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008.
short: T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.
date_created: 2019-07-10T11:30:22Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens
IBEA für den automatisierten Schaltungsentwurf
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10698'
author:
- first_name: Tobias
full_name: Knieper, Tobias
last_name: Knieper
- first_name: Bertrand
full_name: Defo, Bertrand
last_name: Defo
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital
Hardware. In: Biologically Inspired Collaborative Computing (BICC). Vol
268. IFIP International Federation for Information Processing. Springer; 2008:2313-222.'
apa: Knieper, T., Defo, B., Kaufmann, P., & Platzner, M. (2008). On Robust Evolution
of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC)
(Vol. 268, pp. 2313–222). Springer.
bibtex: '@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International
Federation for Information Processing}, title={On Robust Evolution of Digital
Hardware}, volume={268}, booktitle={Biologically Inspired Collaborative Computing
(BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and
Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={2313–222}, collection={IFIP
International Federation for Information Processing} }'
chicago: Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On
Robust Evolution of Digital Hardware.” In Biologically Inspired Collaborative
Computing (BICC), 268:2313–222. IFIP International Federation for Information
Processing. Springer, 2008.
ieee: T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of
Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC),
2008, vol. 268, pp. 2313–222.
mla: Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” Biologically
Inspired Collaborative Computing (BICC), vol. 268, Springer, 2008, pp. 2313–222.
short: 'T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired
Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.'
date_created: 2019-07-10T11:38:02Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: ' 268'
language:
- iso: eng
page: 2313-222
publication: Biologically Inspired Collaborative Computing (BICC)
publisher: Springer
series_title: IFIP International Federation for Information Processing
status: public
title: On Robust Evolution of Digital Hardware
type: conference
user_id: '3118'
volume: 268
year: '2008'
...
---
_id: '10718'
author:
- first_name: Jörg
full_name: Niklas, Jörg
last_name: Niklas
citation:
ama: Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme.
Paderborn University; 2008.
apa: Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride
HW/SW-Systeme. Paderborn University.
bibtex: '@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur
für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas,
Jörg}, year={2008} }'
chicago: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride
HW/SW-Systeme. Paderborn University, 2008.
ieee: J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme.
Paderborn University, 2008.
mla: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme.
Paderborn University, 2008.
short: J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme,
Paderborn University, 2008.
date_created: 2019-07-10T11:48:29Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10721'
author:
- first_name: Marco
full_name: Östermann, Marco
last_name: Östermann
citation:
ama: Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University;
2008.
apa: Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn
University.
bibtex: '@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU},
publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }'
chicago: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn
University, 2008.
ieee: M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn
University, 2008.
mla: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn
University, 2008.
short: M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University,
2008.
date_created: 2019-07-10T11:52:51Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Raytracing on a Custom Instruction Set CPU
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10751'
author:
- first_name: Nico
full_name: Westerheide, Nico
last_name: Westerheide
citation:
ama: Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures.
Paderborn University; 2008.
apa: Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures.
Paderborn University.
bibtex: '@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core
Architectures}, publisher={Paderborn University}, author={Westerheide, Nico},
year={2008} }'
chicago: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures.
Paderborn University, 2008.
ieee: N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures.
Paderborn University, 2008.
mla: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures.
Paderborn University, 2008.
short: N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures,
Paderborn University, 2008.
date_created: 2019-07-10T12:03:01Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Design and Evaluation of MicroBlaze Multi-core Architectures
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10778'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Hamed
full_name: Tabkhi, Hamed
last_name: Tabkhi
- first_name: Seyed Ghassem
full_name: Miremadi, Seyed Ghassem
last_name: Miremadi
- first_name: Alireza
full_name: Ejlali, Alireza
last_name: Ejlali
citation:
ama: 'Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective
error detection and roll-back recovery technique for embedded microprocessor control
logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447.
doi:10.1109/ICM.2008.5393497'
apa: Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008).
A cost-effective error detection and roll-back recovery technique for embedded
microprocessor control logic. In 2008 International Conference on Microelectronics
(pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A
cost-effective error detection and roll-back recovery technique for embedded microprocessor
control logic}, DOI={10.1109/ICM.2008.5393497},
booktitle={2008 International Conference on Microelectronics}, publisher={IEEE},
author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem
and Ejlali, Alireza}, year={2008}, pages={444–447} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and
Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique
for Embedded Microprocessor Control Logic.” In 2008 International Conference
on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497.
ieee: H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective
error detection and roll-back recovery technique for embedded microprocessor control
logic,” in 2008 International Conference on Microelectronics, 2008, pp.
444–447.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and
Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008
International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497.
short: 'H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008
International Conference on Microelectronics, IEEE, 2008, pp. 444–447.'
date_created: 2019-07-10T12:11:35Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ICM.2008.5393497
extern: '1'
language:
- iso: eng
page: 444-447
publication: 2008 International Conference on Microelectronics
publisher: IEEE
status: public
title: A cost-effective error detection and roll-back recovery technique for embedded
microprocessor control logic
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '13629'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore
Arrays. In: Proceedings of the International Symposium on Systems, Architectures,
Modeling and Simulation (SAMOS). IEEE; 2008.'
apa: Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms
on Softcore Arrays. In Proceedings of the International Symposium on Systems,
Architectures, Modeling and Simulation (SAMOS). IEEE.
bibtex: '@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh
Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium
on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE},
author={Giefers, Heiner and Platzner, Marco}, year={2008} }'
chicago: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms
on Softcore Arrays.” In Proceedings of the International Symposium on Systems,
Architectures, Modeling and Simulation (SAMOS). IEEE, 2008.
ieee: H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore
Arrays,” in Proceedings of the International Symposium on Systems, Architectures,
Modeling and Simulation (SAMOS), 2008.
mla: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms
on Softcore Arrays.” Proceedings of the International Symposium on Systems,
Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.
short: 'H. Giefers, M. Platzner, in: Proceedings of the International Symposium
on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.'
date_created: 2019-10-04T22:05:22Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Symposium on Systems, Architectures,
Modeling and Simulation (SAMOS)
publisher: IEEE
status: public
title: Realizing Reconfigurable Mesh Algorithms on Softcore Arrays
type: conference
user_id: '398'
year: '2008'
...
---
_id: '13630'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lübbers E, Platzner M. Communication and Synchronization in Multithreaded
Reconfigurable Computing Systems. In: Proceedings of the 8th International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA).
CSREA Press; 2008.'
apa: Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in
Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA).
CSREA Press.
bibtex: '@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization
in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of
the 8th International Conference on Engineering of Reconfigurable Systems and
Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner,
Marco}, year={2008} }'
chicago: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in
Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th
International Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press, 2008.
ieee: E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded
Reconfigurable Computing Systems,” in Proceedings of the 8th International
Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2008.
mla: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded
Reconfigurable Computing Systems.” Proceedings of the 8th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2008.
short: 'E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.'
date_created: 2019-10-04T22:07:14Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 8th International Conference on Engineering of Reconfigurable
Systems and Algorithms (ERSA)
publisher: CSREA Press
status: public
title: Communication and Synchronization in Multithreaded Reconfigurable Computing
Systems
type: conference
user_id: '398'
year: '2008'
...
---
_id: '13631'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lübbers E, Platzner M. A portable abstraction layer for hardware threads.
In: Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901'
apa: Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware
threads. In Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901
bibtex: '@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer
for hardware threads}, DOI={10.1109/fpl.2008.4629901},
booktitle={Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner,
Marco}, year={2008} }'
chicago: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware
Threads.” In Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901.
ieee: E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,”
in Proceedings of the 18th International Conference on Field Programmable Logic
and Applications (FPL), 2008.
mla: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware
Threads.” Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901.
short: 'E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference
on Field Programmable Logic and Applications (FPL), IEEE, 2008.'
date_created: 2019-10-04T22:07:43Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpl.2008.4629901
language:
- iso: eng
publication: Proceedings of the 18th International Conference on Field Programmable
Logic and Applications (FPL)
publication_identifier:
isbn:
- '9781424419609'
publication_status: published
publisher: IEEE
status: public
title: A portable abstraction layer for hardware threads
type: conference
user_id: '398'
year: '2008'
...
---
_id: '2364'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Robert
full_name: Meiche, Robert
last_name: Meiche
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware
Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.'
apa: Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner,
M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
245–251.
bibtex: '@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008,
title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers,
Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251}
}'
chicago: Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian
Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor
Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 245–51. CSREA Press, 2008.
ieee: T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner,
“A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008,
pp. 245–251.
mla: Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor
Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), CSREA Press, 2008, pp. 245–51.
short: 'T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner,
in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:33:32Z
date_updated: 2023-09-26T13:54:24Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-064-7
publisher: CSREA Press
quality_controlled: '1'
status: public
title: A Hardware Accelerator for k-th Nearest Neighbor Thinning
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '2372'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance
monitoring and optimization of reconfigurable computers. In: Many-Core and
Reconfigurable Supercomputing Conference (MRSC). ; 2008.'
apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure
for performance monitoring and optimization of reconfigurable computers. Many-Core
and Reconfigurable Supercomputing Conference (MRSC).'
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure
for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core
and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias
and Plessl, Christian and Platzner, Marco}, year={2008} }'
chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure
for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core
and Reconfigurable Supercomputing Conference (MRSC), 2008.'
ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for
performance monitoring and optimization of reconfigurable computers,” 2008.'
mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring
and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable
Supercomputing Conference (MRSC), 2008.'
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable
Supercomputing Conference (MRSC), 2008.'
date_created: 2018-04-17T12:05:28Z
date_updated: 2023-09-26T13:55:51Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- IP core
- interconnect
language:
- iso: eng
publication: Many-core and Reconfigurable Supercomputing Conference (MRSC)
quality_controlled: '1'
status: public
title: 'IMORC: An infrastructure for performance monitoring and optimization of reconfigurable
computers'
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '6508'
abstract:
- lang: eng
text: 'In this paper, we present a framework that supports experimenting with evolutionary
hardware design. We describe the framework''s modules for composing evolutionary
optimizers and for setting up, controlling, and analyzing experiments. Two case
studies demonstrate the usefulness of the framework: evolution of hash functions
and evolution based on pre-engineered circuits.'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution.
In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
IEEE; 2007:447-454. doi:10.1109/ahs.2007.73'
apa: 'Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware
Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73'
bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework
for Hardware Evolution}, DOI={10.1109/ahs.2007.73},
booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)},
publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454}
}'
chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems
(AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.'
ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,”
in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007),
Edinburgh, UK, 2007, pp. 447–454.'
mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.'
short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware
and Systems (AHS 2007), IEEE, 2007, pp. 447–454.'
conference:
end_date: 2007-08-08
location: Edinburgh, UK
name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
start_date: 2007-08-05
date_created: 2019-01-08T09:52:43Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
doi: 10.1109/ahs.2007.73
keyword:
- integrated circuit design
- hardware evolution
- evolutionary hardware design
- evolutionary optimizers
- hash functions
- preengineered circuits
- Hardware
- Circuits
- Design optimization
- Visualization
- Genetic programming
- Genetic mutations
- Clustering algorithms
- Biological cells
- Field programmable gate arrays
- Routing
language:
- iso: eng
page: 447-454
publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
publication_identifier:
isbn:
- 076952866X
- '9780769528663'
publication_status: published
publisher: IEEE
status: public
title: 'MOVES: A Modular Framework for Hardware Evolution'
type: conference
user_id: '3118'
year: '2007'
...