--- _id: '13637' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE; 2009.' apa: Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE. bibtex: '@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }' chicago: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE, 2009. ieee: H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009. mla: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009. short: 'H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.' date_created: 2019-10-04T22:22:02Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: 'Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ' publisher: IEEE status: public title: Program-driven Fine-grained Power Management for the Reconfigurable Mesh type: conference user_id: '398' year: '2009' ... --- _id: '13638' author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE; 2009. doi:10.1109/fpt.2009.5377645' apa: Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645 bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={10.1109/fpt.2009.5377645}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }' chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. https://doi.org/10.1109/fpt.2009.5377645. ieee: M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), 2009. mla: Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009, doi:10.1109/fpt.2009.5377645. short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.' date_created: 2019-10-04T22:22:52Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpt.2009.5377645 language: - iso: eng publication: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT) publication_identifier: isbn: - '9781424443758' publication_status: published publisher: IEEE status: public title: An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning type: conference user_id: '398' year: '2009' ... --- _id: '13639' author: - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Uwe full_name: Kastens, Uwe last_name: Kastens - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2009.' apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.' bibtex: '@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }' chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2009.' ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.' mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.' short: 'S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.' date_created: 2019-10-04T22:25:10Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE status: public title: 'Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules' type: conference user_id: '398' year: '2009' ... --- _id: '2350' abstract: - lang: eng text: 'Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25' bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.' mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.' short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.' date_created: 2018-04-16T15:05:52Z date_updated: 2023-09-26T13:51:44Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FCCM.2009.25 keyword: - IMORC - interconnect - performance language: - iso: eng page: 275-278 publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) publication_identifier: isbn: - 978-1-4244-4450-2 publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing' type: conference user_id: '15278' year: '2009' ... --- _id: '2262' abstract: - lang: eng text: 'In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.' apa: 'Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.' bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }' chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.' ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.' mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.' short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.' date_created: 2018-04-06T15:18:24Z date_updated: 2023-09-26T13:53:11Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - EvoCache - evolvable hardware - computer architecture language: - iso: eng page: 11-18 place: Los Alamitos, CA, USA publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'EvoCaches: Application-specific Adaptation of Cache Mapping' type: conference user_id: '15278' year: '2009' ... --- _id: '2238' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32' apa: Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32 bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }' chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.' ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.' mla: Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32. short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.' date_created: 2018-04-05T17:11:28Z date_updated: 2023-09-26T13:52:32Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2009.32 keyword: - IMORC - graphics language: - iso: eng page: 119-124 place: Los Alamitos, CA, USA publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) publication_identifier: isbn: - 978-0-7695-3917-1 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 type: conference user_id: '15278' year: '2009' ... --- _id: '2261' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.' apa: Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344. bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }' chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009. ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344. mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44. short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.' date_created: 2018-04-06T15:15:47Z date_updated: 2023-09-26T13:52:52Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - IMORC - NOC - KNN - accelerator language: - iso: eng page: 338-344 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - 978-1-4244-3892-1 issn: - 1946-1488 publisher: IEEE quality_controlled: '1' status: public title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure type: conference user_id: '15278' year: '2009' ... --- _id: '2263' abstract: - lang: eng text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.' apa: 'Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.' bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }' chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.' ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.' mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.' short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.' date_created: 2018-04-06T15:19:51Z date_updated: 2023-09-26T13:53:30Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 319-322 place: USA publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-101-5 publisher: CSREA Press quality_controlled: '1' status: public title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX' type: conference user_id: '15278' year: '2009' ... --- _id: '2358' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Stefan full_name: Lietsch, Stefan last_name: Lietsch - first_name: Kris full_name: Thielemans, Kris last_name: Thielemans citation: ama: 'Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on parallel architectures using STIR. In: IEEE Nuclear Science Symposium Conference Record (NSS). IEEE; 2008:4161-4168. doi:10.1109/NSSMIC.2008.4774198' apa: Beisel, T., Lietsch, S., & Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE. https://doi.org/10.1109/NSSMIC.2008.4774198 bibtex: '@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM PET reconstruction on parallel architectures using STIR}, DOI={10.1109/NSSMIC.2008.4774198}, booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE}, author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008}, pages={4161–4168} }' chicago: Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” In IEEE Nuclear Science Symposium Conference Record (NSS), 4161–68. IEEE, 2008. https://doi.org/10.1109/NSSMIC.2008.4774198. ieee: T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction on parallel architectures using STIR,” in IEEE Nuclear Science Symposium Conference Record (NSS), 2008, pp. 4161–4168. mla: Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures Using STIR.” IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–68, doi:10.1109/NSSMIC.2008.4774198. short: 'T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–4168.' date_created: 2018-04-17T10:59:40Z date_updated: 2022-01-06T06:55:57Z department: - _id: '27' - _id: '78' doi: 10.1109/NSSMIC.2008.4774198 page: 4161-4168 publication: IEEE Nuclear Science Symposium Conference Record (NSS) publisher: IEEE status: public title: A method for OSEM PET reconstruction on parallel architectures using STIR type: conference user_id: '24135' year: '2008' ... --- _id: '2365' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Sven full_name: Döhre, Sven last_name: Döhre - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Ulf full_name: Lorenz, Ulf last_name: Lorenz - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Andre full_name: Send, Andre last_name: Send - first_name: Alexander full_name: Warkentin, Alexander last_name: Warkentin citation: ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.' apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.' bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }' chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008.' ieee: 'M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.' mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.' short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.' date_created: 2018-04-17T11:34:35Z date_updated: 2022-01-06T06:55:58Z department: - _id: '27' - _id: '78' page: 245-251 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-064-7 publisher: CSREA Press status: public title: 'The GOmputer: Accelerating GO with FPGAs' type: conference user_id: '24135' year: '2008' ... --- _id: '10628' alternative_title: - Effects of Pattern Matching Algorithms on Long-term Electromyography Signals author: - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann citation: ama: Boschmann A. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University; 2008. apa: Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University. bibtex: '@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }' chicago: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. ieee: A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. mla: Boschmann, Alexander. Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008. short: A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation von EMG-Signalen, Paderborn University, 2008. date_created: 2019-07-10T09:40:26Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10641' alternative_title: - Self-optimizing Cache Controller author: - first_name: Daniel full_name: Breitlauch, Daniel last_name: Breitlauch citation: ama: Breitlauch D. Selbstoptimierender Cache-Kontroller. Paderborn University; 2008. apa: Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn University. bibtex: '@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }' chicago: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. ieee: D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. mla: Breitlauch, Daniel. Selbstoptimierender Cache-Kontroller. Paderborn University, 2008. short: D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008. date_created: 2019-07-10T11:03:42Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Selbstoptimierender Cache-Kontroller type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10644' alternative_title: - Distributed Simulation of mobile Robots using EyeSim author: - first_name: Toni full_name: Ceylan, Toni last_name: Ceylan - first_name: Coni full_name: Yalcin, Coni last_name: Yalcin citation: ama: Ceylan T, Yalcin C. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University; 2008. apa: Ceylan, T., & Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University. bibtex: '@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }' chicago: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008. ieee: T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University, 2008. mla: Ceylan, Toni, and Coni Yalcin. Verteilte Simulation von Mobilen Robotern Mit EyeSim. Paderborn University, 2008. short: T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008. date_created: 2019-07-10T11:03:45Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Verteilte Simulation von mobilen Robotern mit EyeSim type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10653' author: - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Thiemo full_name: Gruber, Thiemo last_name: Gruber - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Bernhard full_name: Sick, Bernhard last_name: Sick - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: IEEE Adaptive Hardware and Systems (AHS). IEEE; 2008:32-39.' apa: Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., & Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp. 32–39). IEEE. bibtex: '@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }' chicago: Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” In IEEE Adaptive Hardware and Systems (AHS), 32–39. IEEE, 2008. ieee: K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS), 2008, pp. 32–39. mla: Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39. short: 'K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.' date_created: 2019-07-10T11:13:13Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 32-39 publication: IEEE Adaptive Hardware and Systems (AHS) publisher: IEEE status: public title: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control type: conference user_id: '3118' year: '2008' ... --- _id: '10656' author: - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 5216. LNCS. Springer; 2008:22-33.' apa: Glette, K., Torresen, J., Kaufmann, P., & Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer. bibtex: '@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={22–33}, collection={LNCS} }' chicago: Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In IEEE Intl. Conf. on Evolvable Systems (ICES), 5216:22–33. LNCS. Springer, 2008. ieee: K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2008, vol. 5216, pp. 22–33. mla: Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 5216, Springer, 2008, pp. 22–33. short: 'K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33.' date_created: 2019-07-10T11:13:31Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 5216' language: - iso: eng page: 22-33 publication: IEEE Intl. Conf. on Evolvable Systems (ICES) publisher: Springer series_title: LNCS status: public title: A Comparison of Evolvable Hardware Architectures for Classification Tasks type: conference user_id: '3118' volume: 5216 year: '2008' ... --- _id: '10669' author: - first_name: Markus full_name: Happe, Markus last_name: Happe citation: ama: Happe M. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University; 2008. apa: Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University. bibtex: '@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }' chicago: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. ieee: M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. mla: Happe, Markus. Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008. short: M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008. date_created: 2019-07-10T11:15:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern type: mastersthesis user_id: '3118' year: '2008' ... --- _id: '10690' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Kyrre full_name: Glette, Kyrre last_name: Glette - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann citation: ama: Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008. apa: Torresen, J., Glette, K., Platzner, M., & Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). bibtex: '@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }' chicago: Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008. ieee: J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008. mla: Torresen, Jim, et al. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008. short: J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008). date_created: 2019-07-10T11:29:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng status: public title: Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS) type: preprint user_id: '398' year: '2008' ... --- _id: '10691' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO). ACM Press; 2008:1219-1226.' apa: Kaufmann, P., & Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press. bibtex: '@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }' chicago: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In Genetic and Evolutionary Computation (GECCO), 1219–26. ACM Press, 2008. ieee: P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), 2008, pp. 1219–1226. mla: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–26. short: 'P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.' date_created: 2019-07-10T11:29:57Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng page: 1219 - 1226 publication: Genetic and Evolutionary Computation (GECCO) publisher: ACM Press status: public title: Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming type: conference user_id: '3118' year: '2008' ... --- _id: '10696' alternative_title: - Multi-objective Optimizer IBEA for Digital Logic Design author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper citation: ama: Knieper T. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University; 2008. apa: Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University. bibtex: '@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }' chicago: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008. ieee: T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008. mla: Knieper, Tobias. Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf. Paderborn University, 2008. short: T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008. date_created: 2019-07-10T11:30:22Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10698' author: - first_name: Tobias full_name: Knieper, Tobias last_name: Knieper - first_name: Bertrand full_name: Defo, Bertrand last_name: Defo - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: Biologically Inspired Collaborative Computing (BICC). Vol 268. IFIP International Federation for Information Processing. Springer; 2008:2313-222.' apa: Knieper, T., Defo, B., Kaufmann, P., & Platzner, M. (2008). On Robust Evolution of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC) (Vol. 268, pp. 2313–222). Springer. bibtex: '@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={2313–222}, collection={IFIP International Federation for Information Processing} }' chicago: Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In Biologically Inspired Collaborative Computing (BICC), 268:2313–222. IFIP International Federation for Information Processing. Springer, 2008. ieee: T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC), 2008, vol. 268, pp. 2313–222. mla: Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” Biologically Inspired Collaborative Computing (BICC), vol. 268, Springer, 2008, pp. 2313–222. short: 'T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.' date_created: 2019-07-10T11:38:02Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 268' language: - iso: eng page: 2313-222 publication: Biologically Inspired Collaborative Computing (BICC) publisher: Springer series_title: IFIP International Federation for Information Processing status: public title: On Robust Evolution of Digital Hardware type: conference user_id: '3118' volume: 268 year: '2008' ... --- _id: '10718' author: - first_name: Jörg full_name: Niklas, Jörg last_name: Niklas citation: ama: Niklas J. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University; 2008. apa: Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University. bibtex: '@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }' chicago: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008. ieee: J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008. mla: Niklas, Jörg. Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme. Paderborn University, 2008. short: J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008. date_created: 2019-07-10T11:48:29Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10721' author: - first_name: Marco full_name: Östermann, Marco last_name: Östermann citation: ama: Östermann M. Raytracing on a Custom Instruction Set CPU. Paderborn University; 2008. apa: Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University. bibtex: '@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }' chicago: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. ieee: M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. mla: Östermann, Marco. Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008. short: M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008. date_created: 2019-07-10T11:52:51Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Raytracing on a Custom Instruction Set CPU type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10751' author: - first_name: Nico full_name: Westerheide, Nico last_name: Westerheide citation: ama: Westerheide N. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University; 2008. apa: Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University. bibtex: '@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }' chicago: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008. ieee: N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008. mla: Westerheide, Nico. Design and Evaluation of MicroBlaze Multi-Core Architectures. Paderborn University, 2008. short: N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008. date_created: 2019-07-10T12:03:01Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Design and Evaluation of MicroBlaze Multi-core Architectures type: bachelorsthesis user_id: '3118' year: '2008' ... --- _id: '10778' author: - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Hamed full_name: Tabkhi, Hamed last_name: Tabkhi - first_name: Seyed Ghassem full_name: Miremadi, Seyed Ghassem last_name: Miremadi - first_name: Alireza full_name: Ejlali, Alireza last_name: Ejlali citation: ama: 'Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In: 2008 International Conference on Microelectronics. IEEE; 2008:444-447. doi:10.1109/ICM.2008.5393497' apa: Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., & Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE. https://doi.org/10.1109/ICM.2008.5393497 bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}, DOI={10.1109/ICM.2008.5393497}, booktitle={2008 International Conference on Microelectronics}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}, year={2008}, pages={444–447} }' chicago: Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” In 2008 International Conference on Microelectronics, 444–47. IEEE, 2008. https://doi.org/10.1109/ICM.2008.5393497. ieee: H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447. mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–47, doi:10.1109/ICM.2008.5393497. short: 'H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.' date_created: 2019-07-10T12:11:35Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' doi: 10.1109/ICM.2008.5393497 extern: '1' language: - iso: eng page: 444-447 publication: 2008 International Conference on Microelectronics publisher: IEEE status: public title: A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic type: conference user_id: '3118' year: '2008' ... --- _id: '13629' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE; 2008.' apa: Giefers, H., & Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE. bibtex: '@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }' chicago: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE, 2008. ieee: H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008. mla: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008. short: 'H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.' date_created: 2019-10-04T22:05:22Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS) publisher: IEEE status: public title: Realizing Reconfigurable Mesh Algorithms on Softcore Arrays type: conference user_id: '398' year: '2008' ... --- _id: '13630' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008.' apa: Lübbers, E., & Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press. bibtex: '@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }' chicago: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2008. ieee: E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008. mla: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008. short: 'E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.' date_created: 2019-10-04T22:07:14Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) publisher: CSREA Press status: public title: Communication and Synchronization in Multithreaded Reconfigurable Computing Systems type: conference user_id: '398' year: '2008' ... --- _id: '13631' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2008. doi:10.1109/fpl.2008.4629901' apa: Lübbers, E., & Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2008.4629901 bibtex: '@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={10.1109/fpl.2008.4629901}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }' chicago: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. https://doi.org/10.1109/fpl.2008.4629901. ieee: E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), 2008. mla: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008, doi:10.1109/fpl.2008.4629901. short: 'E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.' date_created: 2019-10-04T22:07:43Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2008.4629901 language: - iso: eng publication: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424419609' publication_status: published publisher: IEEE status: public title: A portable abstraction layer for hardware threads type: conference user_id: '398' year: '2008' ... --- _id: '2364' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Robert full_name: Meiche, Robert last_name: Meiche - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.' apa: Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251. bibtex: '@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }' chicago: Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008. ieee: T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251. mla: Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51. short: 'T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.' date_created: 2018-04-17T11:33:32Z date_updated: 2023-09-26T13:54:24Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 245-251 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-064-7 publisher: CSREA Press quality_controlled: '1' status: public title: A Hardware Accelerator for k-th Nearest Neighbor Thinning type: conference user_id: '15278' year: '2008' ... --- _id: '2372' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008.' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).' bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.' mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' short: 'T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.' date_created: 2018-04-17T12:05:28Z date_updated: 2023-09-26T13:55:51Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - IMORC - IP core - interconnect language: - iso: eng publication: Many-core and Reconfigurable Supercomputing Conference (MRSC) quality_controlled: '1' status: public title: 'IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers' type: conference user_id: '15278' year: '2008' ... --- _id: '6508' abstract: - lang: eng text: 'In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework''s modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73' apa: 'Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73' bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={10.1109/ahs.2007.73}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }' chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.' ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, UK, 2007, pp. 447–454.' mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.' short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.' conference: end_date: 2007-08-08 location: Edinburgh, UK name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) start_date: 2007-08-05 date_created: 2019-01-08T09:52:43Z date_updated: 2022-01-06T07:03:08Z department: - _id: '78' doi: 10.1109/ahs.2007.73 keyword: - integrated circuit design - hardware evolution - evolutionary hardware design - evolutionary optimizers - hash functions - preengineered circuits - Hardware - Circuits - Design optimization - Visualization - Genetic programming - Genetic mutations - Clustering algorithms - Biological cells - Field programmable gate arrays - Routing language: - iso: eng page: 447-454 publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) publication_identifier: isbn: - 076952866X - '9780769528663' publication_status: published publisher: IEEE status: public title: 'MOVES: A Modular Framework for Hardware Evolution' type: conference user_id: '3118' year: '2007' ... --- _id: '10623' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel citation: ama: Beisel T. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University; 2007. apa: Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University. bibtex: '@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }' chicago: Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007. ieee: T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007. mla: Beisel, Tobias. Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen. Paderborn University, 2007. short: T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn University, 2007. date_created: 2019-07-10T09:36:57Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10625' author: - first_name: Neil full_name: Bergmann, Neil last_name: Bergmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich citation: ama: Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405 apa: Bergmann, N., Platzner, M., & Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems, 2007, 1–2. https://doi.org/10.1155/2007/28405 bibtex: '@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }' chicago: 'Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems 2007 (2007): 1–2. https://doi.org/10.1155/2007/28405.' ieee: N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” {EURASIP} Journal on Embedded Systems, vol. 2007, pp. 1–2, 2007. mla: Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” {EURASIP} Journal on Embedded Systems, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:10.1155/2007/28405. short: N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2. date_created: 2019-07-10T09:40:11Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' doi: 10.1155/2007/28405 intvolume: ' 2007' language: - iso: eng page: 1-2 publication: '{EURASIP} Journal on Embedded Systems' publisher: Springer Science+Business Media status: public title: Dynamically Reconfigurable Architectures (editorial) type: journal_article user_id: '398' volume: 2007 year: '2007' ... --- _id: '10643' author: - first_name: Toni full_name: Ceylan, Toni last_name: Ceylan - first_name: Coni full_name: Yalcin, Coni last_name: Yalcin citation: ama: Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007. apa: Ceylan, T., & Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University. bibtex: '@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }' chicago: Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007. ieee: T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007. mla: Ceylan, Toni, and Coni Yalcin. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University, 2007. short: T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007. date_created: 2019-07-10T11:03:44Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: Distributed Simulation of mobile Robots using EyeSim type: bachelorsthesis user_id: '3118' year: '2007' ... --- _id: '10646' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186 apa: Danne, K., Mühlenbernd, R., & Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302. https://doi.org/10.1049/iet-cdt:20060186 bibtex: '@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }' chicago: 'Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques 1, no. 4 (2007): 295–302. https://doi.org/10.1049/iet-cdt:20060186.' ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” IET Computers Digital Techniques, vol. 1, no. 4, pp. 295–302, 2007. mla: Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” IET Computers Digital Techniques, vol. 1, no. 4, 2007, pp. 295–302, doi:10.1049/iet-cdt:20060186. short: K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302. date_created: 2019-07-10T11:10:54Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1049/iet-cdt:20060186 intvolume: ' 1' issue: '4' keyword: - reconfigurable architectures - resource allocation - device reconfiguration time - dynamic hardware reconfiguration - dynamically reconfigurable hardware - light-weight runtime system - merge server distribute load - periodic real-time tasks - runtime system overheads - schedulability analysis - scheduling technique - server-based execution - synthesis tool flow language: - iso: eng page: 295-302 publication: IET Computers Digital Techniques publication_identifier: issn: - 1751-8601 status: public title: Server-based execution of periodic tasks on dynamically reconfigurable hardware type: journal_article user_id: '3118' volume: 1 year: '2007' ... --- _id: '10647' author: - first_name: Bertrand full_name: Defo, Bertrand last_name: Defo citation: ama: Defo B. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University; 2007. apa: Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University. bibtex: '@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }' chicago: Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. ieee: B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. mla: Defo, Bertrand. A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007. short: B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007. date_created: 2019-07-10T11:10:55Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10648' author: - first_name: Sven full_name: Döhre, Sven last_name: Döhre citation: ama: Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007. apa: Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University. bibtex: '@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }' chicago: Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007. ieee: S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007. mla: Döhre, Sven. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University, 2007. short: S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007. date_created: 2019-07-10T11:10:56Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10689' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In: Architecture of Computing Systems (ARCS). Vol 4415. LNCS. Springer; 2007:199-208.' apa: 'Kaufmann, P., & Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.' bibtex: '@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }' chicago: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” In Architecture of Computing Systems (ARCS), 4415:199–208. LNCS. Springer, 2007.' ieee: 'P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208.' mla: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems: Multi-Objective Hardware Evolution.” Architecture of Computing Systems (ARCS), vol. 4415, Springer, 2007, pp. 199–208.' short: 'P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208.' date_created: 2019-07-10T11:29:03Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' intvolume: ' 4415' language: - iso: eng page: 199-208 publication: Architecture of Computing Systems (ARCS) publisher: Springer series_title: LNCS status: public title: 'Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution' type: conference user_id: '3118' volume: 4415 year: '2007' ... --- _id: '10709' alternative_title: - k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving Mechanism Acceleration author: - first_name: Robert full_name: Meiche, Robert last_name: Meiche citation: ama: Meiche R. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University; 2007. apa: Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University. bibtex: '@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }' chicago: Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. ieee: R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. mla: Meiche, Robert. VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen. Paderborn University, 2007. short: R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007. date_created: 2019-07-10T11:43:33Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann title: VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen type: bachelorsthesis user_id: '3118' year: '2007' ... --- _id: '10728' author: - first_name: Waldemar full_name: Reisch, Waldemar last_name: Reisch citation: ama: Reisch W. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University; 2007. apa: Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University. bibtex: '@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }' chicago: Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. ieee: W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. mla: Reisch, Waldemar. Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007. short: W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007. date_created: 2019-07-10T11:54:46Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10729' author: - first_name: Eike full_name: Rethmeier, Eike last_name: Rethmeier citation: ama: Rethmeier E. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University; 2007. apa: Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University. bibtex: '@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }' chicago: Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007. ieee: E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007. mla: Rethmeier, Eike. Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem. Paderborn University, 2007. short: E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007. date_created: 2019-07-10T11:54:47Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem type: mastersthesis user_id: '3118' year: '2007' ... --- _id: '10735' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO). Vol 15. Advances in Parallel Computing. IOS Press; 2007:749-756.' apa: 'Schumacher, T., Lübbers, E., Kaufmann, P., & Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.' bibtex: '@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances in Parallel Computing} }' chicago: 'Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 15:749–56. Advances in Parallel Computing. IOS Press, 2007.' ieee: 'T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.' mla: 'Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), vol. 15, IOS Press, 2007, pp. 749–56.' short: 'T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.' date_created: 2019-07-10T11:58:09Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' intvolume: ' 15' language: - iso: eng page: 749-756 publication: 'Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)' publisher: IOS Press series_title: Advances in Parallel Computing status: public title: Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster type: conference user_id: '398' volume: 15 year: '2007' ... --- _id: '13627' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable Mesh Model. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380623' apa: Giefers, H., & Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380623 bibtex: '@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation Based on the Reconfigurable Mesh Model}, DOI={10.1109/fpl.2007.4380623}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2007} }' chicago: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380623. ieee: H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable Mesh Model,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007. mla: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the Reconfigurable Mesh Model.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380623. short: 'H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:57:25Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380623 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: A Many-Core Implementation Based on the Reconfigurable Mesh Model type: conference user_id: '398' year: '2007' ... --- _id: '13628' author: - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686' apa: 'Lübbers, E., & Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE. https://doi.org/10.1109/fpl.2007.4380686' bibtex: '@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting Hard-and Software Threads}, DOI={10.1109/fpl.2007.4380686}, booktitle={Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2007} }' chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2007. https://doi.org/10.1109/fpl.2007.4380686.' ieee: 'E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software Threads,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.' mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software Threads.” Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007, doi:10.1109/fpl.2007.4380686.' short: 'E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.' date_created: 2019-10-04T21:58:35Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' doi: 10.1109/fpl.2007.4380686 language: - iso: eng publication: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) publication_identifier: isbn: - '9781424410590' - '9781424410606' publication_status: published publisher: IEEE status: public title: 'ReconOS: An RTOS Supporting Hard-and Software Threads' type: conference user_id: '398' year: '2007' ... --- _id: '2401' abstract: - lang: eng text: ' This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit''s performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lothar full_name: Thiele, Lothar last_name: Thiele citation: ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344' apa: Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344 bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }' chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344. ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348. mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344. short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.' date_created: 2018-04-17T13:43:21Z date_updated: 2022-01-06T06:56:05Z department: - _id: '518' - _id: '78' doi: 10.1109/FPT.2006.270344 keyword: - temporal partitioning - retiming - ILP page: 345-348 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: Optimal Temporal Partitioning based on Slowdown and Retiming type: conference user_id: '24135' year: '2006' ... --- _id: '10688' author: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.' apa: Kaufmann, P., & Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). bibtex: '@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006} }' chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.” Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006. short: 'P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.' date_created: 2019-07-10T11:28:14Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' language: - iso: eng publication: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD) status: public title: Multi-objective Intrinsic Hardware Evolution type: conference user_id: '3118' year: '2006' ... --- _id: '10716' author: - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd citation: ama: Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006. apa: Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University. bibtex: '@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }' chicago: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. ieee: R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006. mla: Mühlenbernd, Roland. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University, 2006. short: R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006. date_created: 2019-07-10T11:48:27Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' language: - iso: eng publisher: Paderborn University status: public title: FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks type: bachelorsthesis user_id: '3118' year: '2006' ... --- _id: '13624' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Roland full_name: Mühlenbernd, Roland last_name: Mühlenbernd - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.' apa: Danne, K., Mühlenbernd, R., & Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE. bibtex: '@inproceedings{Danne_Mühlenbernd_Platzner_2006, title={Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}, booktitle={Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2006. ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006. mla: Danne, Klaus, et al. “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-Time Conditions.” Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006. short: 'K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.' date_created: 2019-10-04T21:48:42Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE status: public title: Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions type: conference user_id: '398' year: '2006' ... --- _id: '13625' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.' apa: Danne, K., & Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). bibtex: '@inproceedings{Danne_Platzner_2006, title={An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}, booktitle={In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. ieee: K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. mla: Danne, Klaus, and Marco Platzner. “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices.” In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006. short: 'K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.' date_created: 2019-10-04T21:51:29Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) status: public title: An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices type: conference user_id: '398' year: '2006' ... --- _id: '13626' author: - first_name: Klaus full_name: Danne, Klaus last_name: Danne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.' apa: Danne, K., & Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press. bibtex: '@inproceedings{Danne_Platzner_2006, title={Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}, booktitle={Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE CS Press}, author={Danne, Klaus and Platzner, Marco}, year={2006} }' chicago: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press, 2006. ieee: K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006. mla: Danne, Klaus, and Marco Platzner. “Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware.” Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006. short: 'K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.' date_created: 2019-10-04T21:53:12Z date_updated: 2022-01-06T06:51:40Z department: - _id: '78' language: - iso: eng publication: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW) publisher: IEEE CS Press status: public title: Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware type: conference user_id: '398' year: '2006' ... --- _id: '2411' abstract: - lang: eng text: ' This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69' apa: Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69 bibtex: '@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }' chicago: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69. ieee: C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218. mla: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69. short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.' date_created: 2018-04-17T14:34:03Z date_updated: 2022-01-06T06:56:07Z department: - _id: '518' - _id: '78' doi: 10.1109/ASAP.2005.69 keyword: - Zippy page: 213-218 publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publisher: IEEE Computer Society status: public title: Zippy – A coarse-grained reconfigurable array with support for hardware virtualization type: conference user_id: '24135' year: '2005' ...