---
_id: '21813'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies
for the Learning Classifier System XCS. In: GECCO ’21: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. Association for Computing
Machinery (ACM); 2021:1639–1647. doi:10.1145/3449726.3463159'
apa: 'Hansmeier, T., & Platzner, M. (2021). An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS. GECCO ’21: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
https://doi.org/10.1145/3449726.3463159'
bibtex: '@inproceedings{Hansmeier_Platzner_2021, place={New York, NY, United States},
title={An Experimental Comparison of Explore/Exploit Strategies for the Learning
Classifier System XCS}, DOI={10.1145/3449726.3463159},
booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Platzner, Marco}, year={2021}, pages={1639–1647} }'
chicago: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” In GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
New York, NY, United States: Association for Computing Machinery (ACM), 2021.
https://doi.org/10.1145/3449726.3463159.'
ieee: 'T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Lille, France,
2021, pp. 1639–1647, doi: 10.1145/3449726.3463159.'
mla: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Association
for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:10.1145/3449726.3463159.'
short: 'T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, Association for Computing Machinery
(ACM), New York, NY, United States, 2021, pp. 1639–1647.'
conference:
end_date: 2021-07-14
location: Lille, France
name: International Workshop on Learning Classifier Systems (IWLCS 2021)
start_date: 2021-07-10
date_created: 2021-04-28T09:08:17Z
date_updated: 2022-09-02T09:42:38Z
department:
- _id: '78'
doi: 10.1145/3449726.3463159
language:
- iso: eng
page: 1639–1647
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-8351-6
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier
System XCS
type: conference
user_id: '49992'
year: '2021'
...
---
_id: '27841'
abstract:
- lang: eng
text: Verification of software and processor hardware usually proceeds separately,
software analysis relying on the correctness of processors executing machine instructions.
This assumption is valid as long as the software runs on standard CPUs that have
been extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption. In
this paper we present a novel formal approach for hardware/software co-verification
targeting processors with custom instruction set extensions. We detail two different
approaches for checking whether the hardware fulfills the requirements expected
by the software analysis. The approaches are designed to explore a trade-off between
generality of the verification and computational effort. Then, we describe the
integration of software and hardware analyses for both techniques and describe
a fully automated tool chain implementing the approaches. Finally, we demonstrate
and compare the two approaches on example source code with custom instructions,
using state-of-the-art software analysis and hardware verification techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Felix
full_name: Pauck, Felix
id: '22398'
last_name: Pauck
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware
Co-Verification for Custom Instruction Set Processors. IEEE Access. Published
online 2021. doi:10.1109/ACCESS.2021.3131213
apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021).
Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE
Access. https://doi.org/10.1109/ACCESS.2021.3131213
bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware
Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213},
journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck,
Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021}
}'
chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and
Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set
Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.
ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware
Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021,
doi: 10.1109/ACCESS.2021.3131213.'
mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom
Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.
short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access
(2021).
date_created: 2021-11-25T14:12:22Z
date_updated: 2023-01-18T08:34:50Z
department:
- _id: '78'
doi: 10.1109/ACCESS.2021.3131213
funded_apc: '1'
keyword:
- Software Analysis
- Abstract Interpretation
- Custom Instruction
- Hardware Verification
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: IEEE Access
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Software/Hardware Co-Verification for Custom Instruction Set Processors
type: journal_article
user_id: '22398'
year: '2021'
...
---
_id: '29138'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: 'Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE
29th International Conference on Very Large Scale Integration (VLSI-SoC).
; 2021. doi:10.1109/vlsi-soc53125.2021.9606974'
apa: Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC).
https://doi.org/10.1109/vlsi-soc53125.2021.9606974
bibtex: '@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing},
DOI={10.1109/vlsi-soc53125.2021.9606974},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }'
chicago: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021. https://doi.org/10.1109/vlsi-soc53125.2021.9606974.
ieee: 'Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.'
mla: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021, doi:10.1109/vlsi-soc53125.2021.9606974.
short: 'Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large
Scale Integration (VLSI-SoC), 2021.'
date_created: 2021-12-30T00:02:24Z
date_updated: 2023-04-19T15:03:45Z
department:
- _id: '78'
doi: 10.1109/vlsi-soc53125.2021.9606974
language:
- iso: eng
project:
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
- _id: '1'
name: 'SFB 901: SFB 901'
publication: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)
publication_status: published
status: public
title: Hardware Trojans in Reconfigurable Computing
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '20681'
abstract:
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. The advanced stealthy malicious look-up-table (LUT) attack activates a
Trojan only when generating the FPGA bitstream and can thus not be detected by
register transfer and gate level testing and verification. However, also this
attack was recently revealed by a bitstream-level proof-carrying hardware (PCH)
approach. In this paper, we present a novel attack that leverages malicious routing
of the inserted Trojan circuit to acquire a dormant state even in the generated
and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs
of the FPGA via a programmable interconnect point (PIP). The Trojan is detached
from inputs/outputs during place-and-route and re-connected only when the FPGA
is being programmed, thus activating the Trojan circuit without any need for a
trigger logic. Since the Trojan is injected in a post-synthesis step and remains
unconnected in the bitstream, the presented attack can currently neither be prevented
by conventional testing and verification methods nor by recent bitstream-level
verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level
Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference
(DATE); 2021. doi:10.23919/DATE51398.2021.9474026'
apa: 'Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing:
Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Design, Automation
and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026'
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble,
France}, title={Malicious Routing: Circumventing Bitstream-level Verification
for FPGAs}, DOI={10.23919/DATE51398.2021.9474026},
booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition
(DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)},
author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021}
}'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing:
Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble,
France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing
Bitstream-level Verification for FPGAs,” presented at the Design, Automation and
Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.'
mla: 'Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level
Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference
(DATE), 2021, doi:10.23919/DATE51398.2021.9474026.'
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation &
Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and
Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.'
conference:
end_date: 2021-02-05
location: Alpexpo | Grenoble, France
name: Design, Automation and Test in Europe Conference (DATE'21)
start_date: 2021-02-01
date_created: 2020-12-07T14:03:00Z
date_updated: 2023-05-11T09:16:34Z
ddc:
- '006'
department:
- _id: '78'
doi: 10.23919/DATE51398.2021.9474026
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:16:15Z
date_updated: 2023-05-11T09:16:15Z
file_id: '44752'
file_name: 1812.pdf
file_size: 394011
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:16:15Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Alpexpo | Grenoble, France
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
publication_identifier:
eisbn:
- 978-3-9819263-5-4
publication_status: published
publisher: 2021 Design, Automation and Test in Europe Conference (DATE)
status: public
title: 'Malicious Routing: Circumventing Bitstream-level Verification for FPGAs'
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '30909'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: 'Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
ACM; 2021. doi:10.1145/3468044.3468056'
apa: 'Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
https://doi.org/10.1145/3468044.3468056'
bibtex: '@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded
Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={10.1145/3468044.3468056}, booktitle={Proceedings
of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }'
chicago: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for
Industrial Analytics on a Reconfigurable System-on-Chip.” In Proceedings of
the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies. ACM, 2021. https://doi.org/10.1145/3468044.3468056.'
ieee: 'L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.'
mla: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip.” Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
ACM, 2021, doi:10.1145/3468044.3468056.'
short: 'L. Clausing, in: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.'
date_created: 2022-04-18T10:17:47Z
date_updated: 2023-07-09T13:09:11Z
department:
- _id: '78'
doi: 10.1145/3468044.3468056
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: Proceedings of the 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies
publication_status: published
publisher: ACM
status: public
title: 'ReconOS64: High-Performance Embedded Computing for Industrial Analytics on
a Reconfigurable System-on-Chip'
type: conference
user_id: '398'
year: '2021'
...
---
_id: '30908'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Maurice
full_name: Kuschel, Maurice
last_name: Kuschel
- first_name: 'Rahil '
full_name: 'Arshad, Rahil '
last_name: Arshad
- first_name: Sneha
full_name: Rautmare, Sneha
last_name: Rautmare
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: 'Dirk '
full_name: 'Schollbach, Dirk '
last_name: Schollbach
citation:
ama: 'Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration
of Lightweight DNN Model Inference in Industrial Analytics. In: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases. Springer;
2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27'
apa: 'Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare,
S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021).
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Machine Learning and Principles and Practice of Knowledge Discovery in Databases.
https://doi.org/10.1007/978-3-030-93736-2_27'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021,
title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics}, DOI={https://doi.org/10.1007/978-3-030-93736-2_27},
booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery
in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and
Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and
Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach,
Dirk }, year={2021} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil Arshad,
Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk Schollbach.
“FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.”
In Machine Learning and Principles and Practice of Knowledge Discovery in
Databases. Springer, 2021. https://doi.org/10.1007/978-3-030-93736-2_27.'
ieee: 'H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics.” Machine Learning and Principles
and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.'
short: 'H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare,
S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.'
date_created: 2022-04-18T10:16:55Z
date_updated: 2023-09-15T15:09:07Z
department:
- _id: '78'
doi: https://doi.org/10.1007/978-3-030-93736-2_27
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: ' Machine Learning and Principles and Practice of Knowledge Discovery
in Databases'
publisher: Springer
status: public
title: 'FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics'
type: conference
user_id: '477'
year: '2021'
...
---
_id: '3583'
author:
- first_name: Zakarya
full_name: ' Guetttatfi, Zakarya'
last_name: ' Guetttatfi'
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches
for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.
In: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC). ; 2020.'
apa: Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices. In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC).
bibtex: '@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices}, booktitle={Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul
and Platzner, Marco}, year={2020} }'
chicago: Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices.” In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC), 2020.
ieee: Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic
Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing
Devices,” in Proceedings of the International Workshop on Applied Reconfigurable
Computing (ARC), 2020.
mla: Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling
and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings
of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
short: 'Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), 2020.'
date_created: 2018-07-20T14:07:15Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC)
status: public
title: Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware
Tasks to Reconfigurable Computing Devices
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21324'
author:
- first_name: Khushboo
full_name: Chandrakar, Khushboo
last_name: Chandrakar
citation:
ama: Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis.; 2020.
apa: Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis.
bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
}'
chicago: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to
Improve Approximate Circuit Synthesis, 2020.
ieee: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis. 2020.
mla: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis. 2020.
short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...
---
_id: '21432'
abstract:
- lang: eng
text: "Robots are becoming increasingly autonomous and more capable. Because of
a limited portable energy budget by e.g. batteries, and more demanding algorithms,
an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs)
for example can provide fast and efficient processing and the Robot Operating
System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel
ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework
for integrating reconfigurable hardware. It provides a unified interface between
software and hardware. ReconROS is evaluated in this thesis by implementing a
Sobel filter as the video processing application, running on a Zynq-7000 series
System on Chip. Timing measurements were taken of execution and transfer times
and were compared to theoretical values. Designing the hardware implementation
is done by C code using High Level Synthesis and with the interface and functionality
provided by ReconROS. An important aspect is the publish/subscribe mechanism of
ROS. The Operating System interface functions for publishing and subscribing are
reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface
performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing
to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces
consistency to the execution times and performs twice as fast as the software
implementation."
author:
- first_name: Luca-Sebastian
full_name: Henke, Luca-Sebastian
last_name: Henke
citation:
ama: Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application.; 2020.
apa: Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a
Video Processing Application.
bibtex: '@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based
on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020}
}'
chicago: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based
on a Video Processing Application, 2020.
ieee: L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing
Application. 2020.
mla: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on
a Video Processing Application. 2020.
short: L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application, 2020.
date_created: 2021-03-10T07:07:01Z
date_updated: 2022-01-06T06:54:59Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
type: bachelorsthesis
user_id: '60323'
year: '2020'
...
---
_id: '21584'
author:
- first_name: Carlos Paiz
full_name: Gatica, Carlos Paiz
last_name: Gatica
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions
on Edge-Devices using Reconfigurable Architectures. In: Machine Learning for
Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg; 2020. doi:10.1007/978-3-662-59084-3_9'
apa: Gatica, C. P., & Platzner, M. (2020). Adaptable Realization of Industrial
Analytics Functions on Edge-Devices using Reconfigurable Architectures. In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-59084-3_9
bibtex: '@inproceedings{Gatica_Platzner_2020, place={Berlin, Heidelberg}, title={Adaptable
Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable
Architectures}, DOI={10.1007/978-3-662-59084-3_9},
booktitle={Machine Learning for Cyber Physical Systems (ML4CPS 2017)}, author={Gatica,
Carlos Paiz and Platzner, Marco}, year={2020} }'
chicago: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg, 2020.
https://doi.org/10.1007/978-3-662-59084-3_9.
ieee: C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics
Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning
for Cyber Physical Systems (ML4CPS 2017), 2020.
mla: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” Machine
Learning for Cyber Physical Systems (ML4CPS 2017), 2020, doi:10.1007/978-3-662-59084-3_9.
short: 'C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems
(ML4CPS 2017), Berlin, Heidelberg, 2020.'
date_created: 2021-03-31T08:58:59Z
date_updated: 2022-01-06T06:55:06Z
department:
- _id: '78'
doi: 10.1007/978-3-662-59084-3_9
language:
- iso: eng
place: Berlin, Heidelberg
publication: Machine Learning for Cyber Physical Systems (ML4CPS 2017)
publication_identifier:
isbn:
- '9783662590836'
- '9783662590843'
issn:
- 2522-8579
- 2522-8587
publication_status: published
status: public
title: Adaptable Realization of Industrial Analytics Functions on Edge-Devices using
Reconfigurable Architectures
type: conference
user_id: '398'
year: '2020'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '17369'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings.
International Journal of Hybrid intelligent Systems. 2020.
apa: Ho, N., Kaufmann, P., & Platzner, M. (2020). Evolution of Application-Specific
Cache Mappings. International Journal of Hybrid Intelligent Systems.
bibtex: '@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific
Cache Mappings}, journal={International Journal of Hybrid intelligent Systems},
publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco},
year={2020} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific
Cache Mappings.” International Journal of Hybrid Intelligent Systems, 2020.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache
Mappings,” International Journal of Hybrid intelligent Systems, 2020.
mla: Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” International
Journal of Hybrid Intelligent Systems, IOS Press, 2020.
short: N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent
Systems (2020).
date_created: 2020-07-10T18:55:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
language:
- iso: eng
publication: International Journal of Hybrid intelligent Systems
publisher: IOS Press
status: public
title: Evolution of Application-Specific Cache Mappings
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '20748'
abstract:
- lang: eng
text: "On the circuit level, the design paradigm Approximate Computing seeks to
trade off computational accuracy against a target metric, e.g., energy consumption.
This trade-off is possible for many applications due to their inherent resiliency
against inaccuracies.\r\nIn the past, several automated approximation frameworks
have been presented, which either utilize designated approximation techniques
or libraries to replace approximable circuit parts with inaccurate versions. The
frameworks invoke a search algorithm to iteratively explore the search space of
performance degraded circuits, and validate their quality individually. \r\nIn
this paper, we propose to reverse this procedure. Rather than exploring the search
space, we delineate the approximate parts of the search space which are guaranteed
to lead to valid approximate circuits. Our methodology is supported by formal
verification and independent of approximation techniques. Eventually, the user
is provided with quality bounds of the individual approximable circuit parts.
Consequently, our approach guarantees that any approximate circuit which implements
these parts within the determined quality constraints satisfies the global quality
constraints, superseding a subsequent quality verification.\r\nIn our experimental
results, we present the runtimes of our approach."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC
Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization
for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
bibtex: '@article{Witschen_Wiersema_Platzner, title={Search Space Characterization
for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search
Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing
(AxC 2020), n.d.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization
for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020).
.
mla: Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.”
Fifth Workshop on Approximate Computing (AxC 2020).
short: L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing
(AxC 2020) (n.d.).
date_created: 2020-12-15T15:13:49Z
date_updated: 2022-01-06T06:54:35Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-12-15T15:11:06Z
date_updated: 2020-12-15T15:11:06Z
file_id: '20749'
file_name: witschen20_axc.pdf
file_size: 250870
relation: main_file
success: 1
file_date_updated: 2020-12-15T15:11:06Z
has_accepted_license: '1'
language:
- iso: eng
page: '2'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: Fifth Workshop on Approximate Computing (AxC 2020)
publication_status: accepted
status: public
title: Search Space Characterization for AxC Synthesis
type: preprint
user_id: '3118'
year: '2020'
...
---
_id: '20750'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for
ROS2 Applications. In: Proceedings of the 2020 International Conference on
Field-Programmable Technology (FPT). ; 2020.'
apa: 'Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware
Acceleration for ROS2 Applications. In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT).'
bibtex: '@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware
Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian
and Platzner, Marco and Rinner, Bernhard}, year={2020} }'
chicago: 'Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible
Hardware Acceleration for ROS2 Applications.” In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
ieee: 'C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration
for ROS2 Applications,” in Proceedings of the 2020 International Conference
on Field-Programmable Technology (FPT), 2020.'
mla: 'Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2
Applications.” Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT), 2020.'
short: 'C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
conference:
end_date: 2020-12-11
name: International Conference on Field Programmable Technology (ICFPT)
start_date: 2020-12-09
date_created: 2020-12-16T05:20:01Z
date_updated: 2022-01-06T06:54:35Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT)
status: public
title: 'ReconROS: Flexible Hardware Acceleration for ROS2 Applications'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '20820'
author:
- first_name: Simon
full_name: Thiele, Simon
last_name: Thiele
citation:
ama: Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.;
2020.
apa: Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA
Overlays.
bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
chicago: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA
Overlays, 2020.
ieee: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
mla: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
full_name: Jaganath, Vivek
last_name: Jaganath
citation:
ama: Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows.; 2020.
apa: Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows.
bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
chicago: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level
Synthesis Tool Flows, 2020.
ieee: V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis
Tool Flows. 2020.
mla: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows. 2020.
short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '17063'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold
of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764.
doi:10.1145/3377929.3398106'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism
for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO
’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion},
publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim
and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “An Adaption Mechanism
for the Error Threshold of XCSF.” In GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion, 1756–64. New York, NY,
United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3398106.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the
Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi:
10.1145/3377929.3398106.'
mla: 'Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.”
GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference
Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: International Workshop on Learning Classifier Systems (IWLCS 2020)
start_date: 2020-07-08
date_created: 2020-05-27T14:14:58Z
date_updated: 2022-01-06T06:53:03Z
department:
- _id: '78'
doi: 10.1145/3377929.3398106
language:
- iso: eng
page: 1756-1764
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Adaption Mechanism for the Error Threshold of XCSF
type: conference
user_id: '477'
year: '2020'
...
---
_id: '17092'
abstract:
- lang: eng
text: Radiation tolerance in FPGAs is an important field of research particularly
for reliable computation in electronics used in aerospace and satellite missions.
The motivation behind this research is the degradation of reliability in FPGA
hardware due to single-event effects caused by radiation particles. Redundancy
is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive
applications. However, redundancy comes with an overhead in terms of excessive
area consumption, latency, and power dissipation. Moreover, the redundant circuit
implementations vary in structure and resource usage with the redundancy insertion
algorithms as well as number of used redundant stages. The radiation environment
varies during the operation time span of the mission depending on the orbit and
space weather conditions. Therefore, the overheads due to redundancy should also
be optimized at run-time with respect to the current radiation level. In this
paper, we propose a technique called Dynamic Reliability Management (DRM) that
utilizes the radiation data, interprets it, selects a suitable redundancy level,
and performs the run-time reconfiguration, thus varying the reliability levels
of the target computation modules. DRM is composed of two parts. The design-time
tool flow of DRM generates a library of various redundant implementations of the
circuit with different magnitudes of performance factors. The run-time tool flow,
while utilizing the radiation/error-rate data, selects a required redundancy level
and reconfigures the computation module with the corresponding redundant implementation.
Both parts of DRM have been verified by experimentation on various benchmarks.
The most significant finding we have from this experimentation is that the performance
can be scaled multiple times by using partial reconfiguration feature of DRM,
e.g., 7.7 and 3.7 times better performance results obtained for our data sorter
and matrix multiplier case studies compared with static reliability management
techniques. Therefore, DRM allows for maintaining a suitable trade-off between
computation reliability and performance overhead during run-time of an application.
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Meisner S, Platzner M. Dynamic Reliability Management for FPGA-Based
Systems. International Journal of Reconfigurable Computing. 2020:1-19.
doi:10.1155/2020/2808710
apa: Anwer, J., Meisner, S., & Platzner, M. (2020). Dynamic Reliability Management
for FPGA-Based Systems. International Journal of Reconfigurable Computing,
1–19. https://doi.org/10.1155/2020/2808710
bibtex: '@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management
for FPGA-Based Systems}, DOI={10.1155/2020/2808710},
journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb
and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }'
chicago: Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management for FPGA-Based Systems.” International Journal of Reconfigurable
Computing, 2020, 1–19. https://doi.org/10.1155/2020/2808710.
ieee: J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for
FPGA-Based Systems,” International Journal of Reconfigurable Computing,
pp. 1–19, 2020.
mla: Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.”
International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710.
short: J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable
Computing (2020) 1–19.
date_created: 2020-06-15T11:25:07Z
date_updated: 2022-01-06T06:53:04Z
department:
- _id: '78'
doi: 10.1155/2020/2808710
language:
- iso: eng
page: 1-19
publication: International Journal of Reconfigurable Computing
publication_identifier:
issn:
- 1687-7195
- 1687-7209
publication_status: published
status: public
title: Dynamic Reliability Management for FPGA-Based Systems
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '15836'
author:
- first_name: K.
full_name: Bellman, K.
last_name: Bellman
- first_name: N.
full_name: Dutt, N.
last_name: Dutt
- first_name: L.
full_name: Esterle, L.
last_name: Esterle
- first_name: A.
full_name: Herkersdorf, A.
last_name: Herkersdorf
- first_name: A.
full_name: Jantsch, A.
last_name: Jantsch
- first_name: C.
full_name: Landauer, C.
last_name: Landauer
- first_name: P.
full_name: R. Lewis, P.
last_name: R. Lewis
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: N.
full_name: TaheriNejad, N.
last_name: TaheriNejad
- first_name: K.
full_name: Tammemäe, K.
last_name: Tammemäe
citation:
ama: Bellman K, Dutt N, Esterle L, et al. Self-aware Cyber-Physical Systems. ACM
Transactions on Cyber-Physical Systems. 2020;Accepted for Publication:1-24.
apa: Bellman, K., Dutt, N., Esterle, L., Herkersdorf, A., Jantsch, A., Landauer,
C., … Tammemäe, K. (2020). Self-aware Cyber-Physical Systems. ACM Transactions
on Cyber-Physical Systems, Accepted for Publication, 1–24.
bibtex: '@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020,
title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication},
journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and
Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C.
and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020},
pages={1–24} }'
chicago: 'Bellman, K., N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, Marco Platzner, N. TaheriNejad, and K. Tammemäe. “Self-Aware Cyber-Physical
Systems.” ACM Transactions on Cyber-Physical Systems Accepted for Publication
(2020): 1–24.'
ieee: K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
mla: Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.
short: K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical
Systems Accepted for Publication (2020) 1–24.
date_created: 2020-02-06T15:05:45Z
date_updated: 2022-01-06T06:52:37Z
department:
- _id: '78'
language:
- iso: eng
page: 1-24
publication: ACM Transactions on Cyber-Physical Systems
status: public
title: Self-aware Cyber-Physical Systems
type: journal_article
user_id: '398'
volume: Accepted for Publication
year: '2020'
...
---
_id: '16213'
abstract:
- lang: eng
text: 'Automated synthesis of approximate circuits via functional approximations
is of prominent importance to provide efficiency in energy, runtime, and chip
area required to execute an application. Approximate circuits are usually obtained
either through analytical approximation methods leveraging approximate transformations
such as bit-width scaling or via iterative search-based optimization methods when
a library of approximate components, e.g., approximate adders and multipliers,
is available. For the latter, exploring the extremely large design space is challenging
in terms of both computations and quality of results. While the combination of
both methods can create more room for further approximations, the \textit{Design
Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such
a hybrid synthesis methodology that applies a low-cost analytical method followed
by parallel stochastic search-based optimization. We address the DSE challenge
through efficient pruning of the design space and skipping unnecessary expensive
testing and/or verification steps. The experimental results reveal up to 10.57x
area savings in comparison with both purely analytical or search-based approaches. '
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology
for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid
Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China:
ACM. https://doi.org/10.1145/3386263.3406952'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid
Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952},
booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan
and Platzner, Marco}, year={2020}, pages={421–426} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid
Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology
for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
mla: Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”
Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020,
ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.'
conference:
location: Beijing, China
name: ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
date_created: 2020-03-02T15:49:38Z
date_updated: 2022-01-06T06:52:45Z
department:
- _id: '78'
doi: 10.1145/3386263.3406952
language:
- iso: eng
page: 421-426
publication: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
publication_status: published
publisher: ACM
status: public
title: A Hybrid Synthesis Methodology for Approximate Circuits
type: conference
user_id: '64665'
year: '2020'
...
---
_id: '16363'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments
via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. New York, NY, United States:
Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126).
New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive
Error Threshold}, DOI={10.1145/3377929.3389968},
booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126}
}'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 125–26.
New York, NY, United States: Association for Computing Machinery (ACM), 2020.
https://doi.org/10.1145/3377929.3389968.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic
Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico,
2020, pp. 125–126.'
mla: 'Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via
an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Association for Computing Machinery (ACM),
2020, pp. 125–26, doi:10.1145/3377929.3389968.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: The Genetic and Evolutionary Computation Conference (GECCO 2020)
start_date: 2020-07-08
date_created: 2020-04-02T10:07:10Z
date_updated: 2022-01-06T06:52:49Z
department:
- _id: '78'
doi: 10.1145/3377929.3389968
language:
- iso: eng
page: 125-126
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold
type: conference
user_id: '477'
year: '2020'
...
---
_id: '20838'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020.'
date_created: 2020-12-23T09:07:11Z
date_updated: 2023-01-03T22:07:12Z
department:
- _id: '78'
doi: 10.1109/ipdpsw50202.2020.00012
language:
- iso: eng
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
isbn:
- '9781728174457'
publication_status: published
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
text: "Modern machine learning (ML) techniques continue to move into the embedded
system space because traditional centralized compute resources do not suit certain
application domains, for example in mobile or real-time environments. Google’s
TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
and makes ML inference accessible on resource-constrained devices. While it offers
the possibility to partially delegate computation to hardware accelerators, there
is no such “delegate” available to utilize the promising characteristics of reconfigurable
hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
a modular delegate framework, which allows accelerators within the programmable
logic to take over the execution of neural network layers. To facilitate the necessary
hardware/software codesign, the FPGA delegate is based on the operating system
for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
enables the instantiation of model-tailored accelerator architectures. In the
hardware back-end, a streaming-based prototype accelerator for the MobileNet model
family showcases the working order of the platform, but falls short of the desired
performance. Thus, it indicates the need for further exploration of alternative
accelerator designs, which the delegate could automatically synthesize to meet
a model’s demands."
author:
- first_name: Felix P.
full_name: Jentzsch, Felix P.
last_name: Jentzsch
citation:
ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture.; 2020.
apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture.
bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
}'
chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture, 2020.
ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture. 2020.
mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture. 2020.
short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '3585'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
volume={99}, DOI={10.1016/j.microrel.2019.04.003},
journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019):
277–90. https://doi.org/10.1016/j.microrel.2019.04.003.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Microelectronics Reliability, vol. 99, pp. 277–290, 2019.'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Microelectronics Reliability,
vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Microelectronics Reliability 99 (2019) 277–290.
date_created: 2018-07-20T14:08:49Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
doi: 10.1016/j.microrel.2019.04.003
intvolume: ' 99'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: 277-290
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Microelectronics Reliability
publication_identifier:
issn:
- 0026-2714
publication_status: published
publisher: Elsevier
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: journal_article
user_id: '49051'
volume: 99
year: '2019'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '10577'
abstract:
- lang: eng
text: "State-of-the-art frameworks for generating approximate circuits automatically
explore the search space in an iterative process - often greedily. Synthesis and
verification processes are invoked in each iteration to evaluate the found solutions
and to guide the search algorithm. As a result, a large number of approximate
circuits is subjected to analysis - leading to long runtimes - but only a few
approximate circuits might form an acceptable solution.\r\n\r\nIn this paper,
we present our Jump Search (JS) method which seeks to reduce the runtime of an
approximation process by reducing the number of expensive synthesis and verification
steps. To reduce the runtime, JS computes impact factors for each approximation
candidate in the circuit to create a selection of approximate circuits without
invoking synthesis or verification processes. We denote the selection as path
from which JS determines the final solution. In our experimental results, JS achieved
speed-ups of up to 57x while area savings remain comparable to the reference search
method, Simulated Annealing."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY,
USA: ACM; 2019. doi:10.1145/3299874.3317998'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19.
New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998'
bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New
York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits}, DOI={10.1145/3299874.3317998},
booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi,
Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner,
VA, USA, 2019.'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium
on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.'
short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY,
USA, 2019.'
conference:
end_date: 2019-05-11
location: Tysons Corner, VA, USA
name: ACM Great Lakes Symposium on VLSI (GLSVLSI)
start_date: 2019-05-09
date_created: 2019-07-08T15:13:10Z
date_updated: 2022-01-06T06:50:45Z
department:
- _id: '78'
doi: 10.1145/3299874.3317998
keyword:
- Approximate computing
- design automation
- parameter selection
- circuit synthesis
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19
publication_identifier:
isbn:
- '9781450362528'
publication_status: published
publisher: ACM
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: conference
user_id: '49051'
year: '2019'
...
---
_id: '11950'
abstract:
- lang: eng
text: Advances in electromyographic (EMG) sensor technology and machine learning
algorithms have led to an increased research effort into high density EMG-based
pattern recognition methods for prosthesis control. With the goal set on an autonomous
multi-movement prosthesis capable of performing training and classification of
an amputee’s EMG signals, the focus of this paper lies in the acceleration of
the embedded signal processing chain. We present two Xilinx Zynq-based architectures
for accelerating two inherently different high density EMG-based control algorithms.
The first hardware accelerated design achieves speed-ups of up to 4.8 over the
software-only solution, allowing for a processing delay lower than the sample
period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only
version and operates at a still satisfactory low processing delay of up to 15
ms while providing a higher reliability and robustness against electrode shift
and noisy channels.
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Florian
full_name: Kraus, Florian
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based
acceleration of robust high density myoelectric signal processing. Journal
of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004
apa: Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., &
Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric
signal processing. Journal of Parallel and Distributed Computing, 123,
77–89. https://doi.org/10.1016/j.jpdc.2018.07.004
bibtex: '@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based
acceleration of robust high density myoelectric signal processing}, volume={123},
DOI={10.1016/j.jpdc.2018.07.004},
journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier},
author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen,
Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89}
}'
chicago: 'Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen,
Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing
123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.'
ieee: A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner,
“Zynq-based acceleration of robust high density myoelectric signal processing,”
Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
mla: Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing,
vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.
short: A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner,
Journal of Parallel and Distributed Computing 123 (2019) 77–89.
date_created: 2019-07-12T13:13:55Z
date_updated: 2022-01-06T06:51:13Z
department:
- _id: '78'
doi: 10.1016/j.jpdc.2018.07.004
intvolume: ' 123'
keyword:
- High density electromyography
- FPGA acceleration
- Medical signal processing
- Pattern recognition
- Prosthetics
language:
- iso: eng
page: 77-89
publication: Journal of Parallel and Distributed Computing
publication_identifier:
issn:
- 0743-7315
publication_status: published
publisher: Elsevier
status: public
title: Zynq-based acceleration of robust high density myoelectric signal processing
type: journal_article
user_id: '398'
volume: 123
year: '2019'
...
---
_id: '12967'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Md Jubaer Hossain
full_name: Pantho, Md Jubaer Hossain
last_name: Pantho
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution
Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of
Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y
apa: Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An
Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube
Technology. Journal of Signal Processing Systems, 91(11), 1259–1272.
https://doi.org/10.1007/s11265-018-1435-y
bibtex: '@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology},
volume={91}, DOI={10.1007/s11265-018-1435-y},
number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier,
Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019},
pages={1259–1272} }'
chicago: 'Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews.
“An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory
Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019):
1259–72. https://doi.org/10.1007/s11265-018-1435-y.'
ieee: T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,”
Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
mla: Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based
on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems,
vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.
short: T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing
Systems 91 (2019) 1259–1272.
date_created: 2019-08-26T13:41:57Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1007/s11265-018-1435-y
intvolume: ' 91'
issue: '11'
language:
- iso: eng
page: 1259 - 1272
publication: Journal of Signal Processing Systems
publication_identifier:
issn:
- 1939-8018
- 1939-8115
publication_status: published
status: public
title: An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory
Cube Technology
type: journal_article
user_id: '49992'
volume: 91
year: '2019'
...
---
_id: '15422'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache
Translation Functions of the LEON3 Processor. In: World Congress on Nature
and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically
Inspired Computing. Springer; 2019.'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor. In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Springer.
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and
Biologically Inspired Computing}, title={Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress
on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances
in Nature and Biologically Inspired Computing} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific
L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and
Biologically Inspired Computing. Springer, 2019.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on
Nature and Biologically Inspired Computing (NaBIC), 2019.
mla: Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation
Functions of the LEON3 Processor.” World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.'
date_created: 2019-12-30T13:55:49Z
date_updated: 2022-01-06T06:52:25Z
department:
- _id: '78'
language:
- iso: eng
publication: World Congress on Nature and Biologically Inspired Computing (NaBIC)
publisher: Springer
series_title: Advances in Nature and Biologically Inspired Computing
status: public
title: Optimization of Application-specific L1 Cache Translation Functions of the
LEON3 Processor
type: conference
user_id: '398'
year: '2019'
...
---
_id: '15883'
author:
- first_name: Shankar
full_name: Kumar Jeyakumar, Shankar
last_name: Kumar Jeyakumar
citation:
ama: Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded
Platforms.; 2019.
apa: Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine
on embedded platforms.
bibtex: '@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector
Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019}
}'
chicago: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms, 2019.
ieee: S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on
embedded platforms. 2019.
mla: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms. 2019.
short: S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded
Platforms, 2019.
date_created: 2020-02-11T16:43:38Z
date_updated: 2022-01-06T06:52:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
title: Incremental learning with Support Vector Machine on embedded platforms
type: mastersthesis
user_id: '61186'
year: '2019'
...
---
_id: '15920'
abstract:
- lang: eng
text: "Secure hardware design is the most important aspect to be considered in addition
to functional correctness. Achieving hardware security in today’s globalized Integrated
Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
It provides an ap- proach to verify that the systems adhere to security properties
either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
Hardware(PCH) is an approach to verify a functional design prior to using it in
hardware. It is a two-party verification approach, where the target party, the
consumer requests new functionalities with pre-defined properties to the producer.
In response, the producer designs the IP (Intellectual Property) cores with the
requested functionalities that adhere to the consumer-defined properties. The
producer provides the IP cores and a proof certificate combined into a proof-carrying
bitstream to the consumer to verify it. If the verification is successful, the
consumer can use the IP cores in his hardware. In essence, the consumer can only
run verified IP cores. Correctly applied, PCH techniques can help consumers to
defend against many unintentional modifications and malicious alterations of the
modules they receive. There are numerous published examples of how to use PCH
to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
with functional equivalence checking for combinational or sequential circuits.
For non-functional properties, since opening new covert channels to leak secret
information from secure circuits is a viable attack vector for hardware trojans,
i.e., intentionally added malicious circuitry, IFT technique is employed to make
sure that secret/untrusted information never reaches any unclassified/trusted
outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
level enabling consumers to validate the trustworthiness of a module’s information
flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
full_name: Keerthipati, Monica
last_name: Keerthipati
citation:
ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking. Universität Paderborn; 2019.
apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn.
bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
Monica}, year={2019} }'
chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for
Information Flow Tracking. Universität Paderborn, 2019.
mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
full_name: Sabu, Nithin S.
last_name: Sabu
citation:
ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets.
Paderborn University; 2019.
apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University.
bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
}'
chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University, 2019.
ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Stefan
full_name: Böttcher, Stefan
last_name: Böttcher
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '15946'
author:
- first_name: Jinay
full_name: Mehta, Jinay
last_name: Mehta
citation:
ama: "Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip.; 2019."
apa: "Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip."
bibtex: "@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip}, author={Mehta, Jinay},
year={2019} }"
chicago: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
ieee: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
mla: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
short: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
date_created: 2020-02-20T14:47:12Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: "Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable
System-on-Chip"
type: mastersthesis
user_id: '398'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.
apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn.
bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
Paderborn}, author={Hansmeier, Tim}, year={2019} }'
chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '31067'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic
Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027'
apa: Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE
International Parallel and Distributed Processing Symposium Workshops (IPDPSW).
https://doi.org/10.1109/ipdpsw.2019.00027
bibtex: '@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027},
booktitle={2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner,
Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }'
chicago: Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas.
“An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”
In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027.
ieee: 'Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping
Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.'
mla: Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks
to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.
short: 'Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.'
date_created: 2022-05-05T07:42:26Z
date_updated: 2022-05-05T07:43:29Z
department:
- _id: '78'
doi: 10.1109/ipdpsw.2019.00027
language:
- iso: eng
publication: 2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_status: published
publisher: IEEE
status: public
title: An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
type: conference
user_id: '398'
year: '2019'
...
---
_id: '9913'
abstract:
- lang: eng
text: Reconfigurable hardware has received considerable attention as a platform
that enables dynamic hardware updates and thus is able to adapt new configurations
at runtime. However, due to their dynamic nature, e.g., field-programmable gate
arrays (FPGA) are subject to a constant possibility of attacks, since each new
configuration might be compromised. Trojans for reconfigurable hardware that evade
state-of-the-art detection techniques and even formal verification, are thus a
large threat to these devices. One such stealthy hardware Trojan, that is inserted
and activated in two stages by compromised electronic design automation (EDA)
tools, has recently been presented and shown to evade all forms of classical pre-configuration
detection techniques. This paper presents a successful pre-configuration countermeasure
against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level
Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent
module creators to infected EDA tools, and to prohibit malicious ones to sell
infected modules to unsuspecting customers.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz
P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer
Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10'
apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware
Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson,
A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing
(Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture
Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10},
booktitle={Applied Reconfigurable Computing}, publisher={Springer International
Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco},
editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger
and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in
Computer Science} }'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable
Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger
Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham:
Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus
the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing,
Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.'
mla: Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious
LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian
Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36,
doi:10.1007/978-3-030-17227-5_10.
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch,
R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International
Publishing, Cham, 2019, pp. 127–136.'
conference:
end_date: 2019-04-11
location: Darmstadt, Germany
name: 15th International Symposium on Applied Reconfigurable Computing (ARC 2019)
start_date: 2019-04-09
date_created: 2019-05-22T07:36:05Z
date_updated: 2023-05-15T08:13:37Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-030-17227-5_10
editor:
- first_name: Christian
full_name: Hochberger, Christian
last_name: Hochberger
- first_name: Brent
full_name: Nelson, Brent
last_name: Nelson
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Roger
full_name: Woods, Roger
last_name: Woods
- first_name: Pedro
full_name: Diniz, Pedro
last_name: Diniz
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:12:33Z
date_updated: 2023-05-11T09:12:33Z
file_id: '44749'
file_name: 978-3-030-17227-5_10.pdf
file_size: 661354
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:12:33Z
has_accepted_license: '1'
intvolume: ' 11444'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 127-136
place: Cham
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: Applied Reconfigurable Computing
publication_identifier:
isbn:
- 978-3-030-17227-5
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan
type: conference
user_id: '72764'
volume: 11444
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
citation:
ama: Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS. Universität Paderborn
apa: Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
}'
chicago: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA
Operated with ReconOS. Universität Paderborn, n.d.
ieee: C. Lienen, Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
mla: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated
with ReconOS. Universität Paderborn.
short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
content_type: application/pdf
creator: clienen
date_created: 2020-07-01T11:46:49Z
date_updated: 2021-02-13T16:46:58Z
file_id: '17351'
file_name: thesis_main.pdf
file_size: 5920668
relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '12871'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published
online 2019. doi:10.1007/s00287-019-01187-w
apa: Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik
Spektrum. https://doi.org/10.1007/s00287-019-01187-w
bibtex: '@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w},
journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian},
year={2019} }'
chicago: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.
ieee: 'M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum,
2019, doi: 10.1007/s00287-019-01187-w.'
mla: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019, doi:10.1007/s00287-019-01187-w.
short: M. Platzner, C. Plessl, Informatik Spektrum (2019).
date_created: 2019-07-22T12:42:44Z
date_updated: 2023-09-26T11:45:57Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/s00287-019-01187-w
file:
- access_level: open_access
content_type: application/pdf
creator: plessl
date_created: 2019-07-22T12:45:02Z
date_updated: 2019-07-22T12:45:02Z
file_id: '12872'
file_name: plessl19_informatik_spektrum.pdf
file_size: 248360
relation: main_file
file_date_updated: 2019-07-22T12:45:02Z
has_accepted_license: '1'
language:
- iso: ger
oa: '1'
publication: Informatik Spektrum
publication_identifier:
issn:
- 0170-6012
- 1432-122X
publication_status: published
quality_controlled: '1'
status: public
title: FPGAs im Rechenzentrum
type: journal_article
user_id: '15278'
year: '2019'
...
---
_id: '52478'
author:
- first_name: Jinay D
full_name: Mehta, Jinay D
last_name: Mehta
citation:
ama: Mehta JD. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip.; 2019.
apa: Mehta, J. D. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip.
bibtex: '@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D},
year={2019} }'
chicago: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
ieee: J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip. 2019.
mla: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip. 2019.
short: J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
date_created: 2024-03-11T15:57:13Z
date_updated: 2024-03-11T15:57:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
title: Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable
System-on-Chip
type: mastersthesis
user_id: '74287'
year: '2019'
...
---
_id: '3362'
abstract:
- lang: eng
text: Profiling applications on a heterogeneous compute node is challenging since
the way to retrieve data from the resources and interpret them varies between
resource types and manufacturers. This holds especially true for measuring the
energy consumption. In this paper we present Ampehre, a novel open source measurement
framework that allows developers to gather comparable measurements from heterogeneous
compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture
of Ampehre and detail the measurement process on the example of energy measurements
on CPU and GPU. To characterize the probing effect, we quantitatively analyze
the trade-off between the accuracy of measurements and the CPU load imposed by
Ampehre. Based on this analysis, we are able to specify reasonable combinations
of sampling periods for the different resource types of a compute node.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes. In: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer
Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6'
apa: 'Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes. In Proceedings of the International
Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84).
Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6'
bibtex: '@inproceedings{Lösch_Wiens_Platzner_2018, place={Cham}, series={Lecture
Notes in Computer Science}, title={Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes}, volume={10793}, DOI={10.1007/978-3-319-77610-1_6},
booktitle={Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)}, publisher={Springer International Publishing}, author={Lösch,
Achim and Wiens, Alex and Platzner, Marco}, year={2018}, pages={73–84}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Lösch, Achim, Alex Wiens, and Marco Platzner. “Ampehre: An Open Source
Measurement Framework for Heterogeneous Compute Nodes.” In Proceedings of the
International Conference on Architecture of Computing Systems (ARCS), 10793:73–84.
Lecture Notes in Computer Science. Cham: Springer International Publishing, 2018.
https://doi.org/10.1007/978-3-319-77610-1_6.'
ieee: 'A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes,” in Proceedings of the International
Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793,
pp. 73–84.'
mla: 'Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous
Compute Nodes.” Proceedings of the International Conference on Architecture
of Computing Systems (ARCS), vol. 10793, Springer International Publishing,
2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.'
short: 'A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS), Springer International Publishing,
Cham, 2018, pp. 73–84.'
date_created: 2018-06-26T13:47:52Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-77610-1_6
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-06-26T13:58:28Z
date_updated: 2018-06-26T13:58:28Z
file_id: '3363'
file_name: loesch2017_arcs.pdf
file_size: 1114026
relation: main_file
success: 1
file_date_updated: 2018-06-26T13:58:28Z
has_accepted_license: '1'
intvolume: ' 10793'
page: 73-84
place: Cham
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)
publication_identifier:
isbn:
- '9783319776095'
- '9783319776101'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: 'Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes'
type: conference
user_id: '477'
volume: 10793
year: '2018'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
full_name: Schnuer, Jan-Philip
last_name: Schnuer
citation:
ama: Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn; 2018.
apa: Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn.
bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
year={2018} }'
chicago: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous
Compute Nodes. Universität Paderborn, 2018.
ieee: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn, 2018.
mla: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn, 2018.
short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
full_name: Croce, Marcel
last_name: Croce
citation:
ama: Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn; 2018.
apa: Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs.
Universität Paderborn.
bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
chicago: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs.
Universität Paderborn, 2018.
ieee: M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität
Paderborn, 2018.
mla: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn, 2018.
short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3373'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: 'Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution
Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures,
Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer
International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13'
apa: 'Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator
for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini,
Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13'
bibtex: '@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in
Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking},
volume={10824}, DOI={10.1007/978-3-319-78890-6_13},
booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications}, publisher={Springer International Publishing}, author={Hansmeier,
Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based
Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes
in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.'
ieee: 'T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator
for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824,
pp. 153–165.'
mla: 'Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof
Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools,
and Applications, vol. 10824, Springer International Publishing, 2018, pp.
153–65, doi:10.1007/978-3-319-78890-6_13.'
short: 'T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, Springer International Publishing,
2018, pp. 153–165.'
conference:
end_date: 2018-05-04
location: Santorini, Greece
name: 'ARC: International Symposium on Applied Reconfigurable Computing'
start_date: 2018-05-02
date_created: 2018-06-27T09:30:24Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-319-78890-6_13
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T13:55:07Z
date_updated: 2018-11-02T13:55:07Z
file_id: '5257'
file_name: AnFPGAHMC-BasedAcceleratorForR.pdf
file_size: 612367
relation: main_file
success: 1
file_date_updated: 2018-11-02T13:55:07Z
has_accepted_license: '1'
intvolume: ' 10824'
language:
- iso: eng
page: 153-165
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: 'ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications'
publication_identifier:
isbn:
- '9783319788890'
- '9783319788906'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: An FPGA/HMC-Based Accelerator for Resolution Proof Checking
type: conference
user_id: '3118'
volume: 10824
year: '2018'
...
---
_id: '3586'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Third Workshop on Approximate Computing (AxC 2018).'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Third Workshop on Approximate Computing
(AxC 2018), n.d.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Third Workshop on Approximate Computing (AxC 2018). .'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Third Workshop on Approximate
Computing (AxC 2018).'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Third Workshop on Approximate Computing (AxC 2018) (n.d.).
date_created: 2018-07-20T14:10:46Z
date_updated: 2022-01-06T06:59:26Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-07-20T14:13:31Z
date_updated: 2018-07-20T14:13:31Z
file_id: '3587'
file_name: WitschenWMAP2018.pdf
file_size: 285348
relation: main_file
success: 1
file_date_updated: 2018-07-20T14:13:31Z
has_accepted_license: '1'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: '6'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Third Workshop on Approximate Computing (AxC 2018)
publication_status: accepted
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
text: Traditional cache design uses a consolidated block of memory address bits
to index a cache set, equivalent to the use of modulo functions. While this module-based
mapping scheme is widely used in contemporary cache structures due to the simplicity
of its hardware design and its good performance for sequences of consecutive addresses,
its use may not be satisfactory for a variety of application domains having different
characteristics.This thesis presents a new type of cache mapping scheme, motivated
by programmable capabilities combined with Nature-inspired optimization of reconfigurable
hardware. This research has focussed on an FPGA-based evolvable cache structure
of the first level cache in a multi-core processor architecture, able to dynamically
change cache indexing. To solve the challenge of reconfigurable cache mappings,
a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
elements is proposed. Focusing on optimization aspects at the system level, a
Performance Measurement Infrastructure is introduced that is able to monitor the
underlying microarchitectural metrics, and an adaptive evaluation strategy is
presented that leverages on Evolutionary Algorithms, that is not only capable
of evolving application-specific address-to-cache-index mappings for level one
split caches but also of reducing optimization times. Putting this all together
and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
of a system architecture reduces cache misses and improves performance over the
use of conventional caches.
- lang: ger
text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
(LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
citation:
ama: 'Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376'
apa: 'Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design
and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376'
bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
Design and Optimization}, DOI={10.17619/UNIPB/1-376},
publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
chicago: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.'
ieee: 'N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018.'
mla: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.'
short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '1165'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate
Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for
Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing
(WAPCO 2018).
bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying
Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018}
}'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making
the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate
Computing (WAPCO 2018), 2018.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying
Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018).
2018.
mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate
Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.
short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing
(WAPCO 2018) (2018).
date_created: 2018-02-01T14:24:54Z
date_updated: 2022-01-06T06:51:06Z
ddc:
- '000'
department:
- _id: '7'
- _id: '34'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-11-26T08:00:53Z
date_updated: 2018-11-26T08:00:53Z
file_id: '5821'
file_name: WitschenWP2018[1].pdf
file_size: 287224
relation: main_file
success: 1
file_date_updated: 2018-11-26T08:00:53Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 4th Workshop On Approximate Computing (WAPCO 2018)
status: public
title: Making the Case for Proof-carrying Approximate Circuits
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '5547'
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on
Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on
Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018.
doi:10.1109/asap.2018.8445098'
apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP). Milan,
Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098'
bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model
for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098},
booktitle={2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and
Platzner, Marco}, year={2018} }'
chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International
Conference on Application-Specific Systems, Architectures and Processors (ASAP).
IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.
ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution
on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP), Milan,
Italy, 2018.
mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference
on Application-Specific Systems, Architectures and Processors (ASAP), IEEE,
2018, doi:10.1109/asap.2018.8445098.
short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific
Systems, Architectures and Processors (ASAP), IEEE, 2018.'
conference:
end_date: 2018-07-12
location: Milan, Italy
name: The 29th Annual IEEE International Conference on Application-specific Systems,
Architectures and Processors
start_date: 2018-07-10
date_created: 2018-11-14T09:26:53Z
date_updated: 2022-01-06T07:01:59Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/asap.2018.8445098
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:40:42Z
date_updated: 2018-11-14T09:40:42Z
file_id: '5552'
file_name: loesch_asap2018.pdf
file_size: 2464949
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:40:42Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: 2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)
publication_identifier:
isbn:
- '9781538674796'
publication_status: published
publisher: IEEE
status: public
title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute
Nodes
type: conference
user_id: '43646'
year: '2018'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...
---
_id: '10782'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: Clausing L. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.
apa: Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum.
bibtex: '@book{Clausing_2018, title={Development of a Hardware / Software Codesign
for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum},
author={Clausing, Lennart}, year={2018} }'
chicago: Clausing, Lennart. Development of a Hardware / Software Codesign for
Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
ieee: L. Clausing, Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum, 2018.
mla: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
short: L. Clausing, Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.
date_created: 2019-07-10T12:13:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: Ruhr-University Bochum
status: public
title: Development of a Hardware / Software Codesign for sonification of LIDAR-based
sensor data
type: mastersthesis
user_id: '3118'
year: '2018'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...