---
_id: '16363'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments
via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. New York, NY, United States:
Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126).
New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive
Error Threshold}, DOI={10.1145/3377929.3389968},
booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126}
}'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 125–26.
New York, NY, United States: Association for Computing Machinery (ACM), 2020.
https://doi.org/10.1145/3377929.3389968.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic
Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico,
2020, pp. 125–126.'
mla: 'Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via
an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Association for Computing Machinery (ACM),
2020, pp. 125–26, doi:10.1145/3377929.3389968.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: The Genetic and Evolutionary Computation Conference (GECCO 2020)
start_date: 2020-07-08
date_created: 2020-04-02T10:07:10Z
date_updated: 2022-01-06T06:52:49Z
department:
- _id: '78'
doi: 10.1145/3377929.3389968
language:
- iso: eng
page: 125-126
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold
type: conference
user_id: '477'
year: '2020'
...
---
_id: '20838'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020.'
date_created: 2020-12-23T09:07:11Z
date_updated: 2023-01-03T22:07:12Z
department:
- _id: '78'
doi: 10.1109/ipdpsw50202.2020.00012
language:
- iso: eng
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
isbn:
- '9781728174457'
publication_status: published
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
text: "Modern machine learning (ML) techniques continue to move into the embedded
system space because traditional centralized compute resources do not suit certain
application domains, for example in mobile or real-time environments. Google’s
TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
and makes ML inference accessible on resource-constrained devices. While it offers
the possibility to partially delegate computation to hardware accelerators, there
is no such “delegate” available to utilize the promising characteristics of reconfigurable
hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
a modular delegate framework, which allows accelerators within the programmable
logic to take over the execution of neural network layers. To facilitate the necessary
hardware/software codesign, the FPGA delegate is based on the operating system
for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
enables the instantiation of model-tailored accelerator architectures. In the
hardware back-end, a streaming-based prototype accelerator for the MobileNet model
family showcases the working order of the platform, but falls short of the desired
performance. Thus, it indicates the need for further exploration of alternative
accelerator designs, which the delegate could automatically synthesize to meet
a model’s demands."
author:
- first_name: Felix P.
full_name: Jentzsch, Felix P.
last_name: Jentzsch
citation:
ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture.; 2020.
apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture.
bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
}'
chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture, 2020.
ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture. 2020.
mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture. 2020.
short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '3585'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
volume={99}, DOI={10.1016/j.microrel.2019.04.003},
journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019):
277–90. https://doi.org/10.1016/j.microrel.2019.04.003.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Microelectronics Reliability, vol. 99, pp. 277–290, 2019.'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Microelectronics Reliability,
vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Microelectronics Reliability 99 (2019) 277–290.
date_created: 2018-07-20T14:08:49Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
doi: 10.1016/j.microrel.2019.04.003
intvolume: ' 99'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: 277-290
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Microelectronics Reliability
publication_identifier:
issn:
- 0026-2714
publication_status: published
publisher: Elsevier
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: journal_article
user_id: '49051'
volume: 99
year: '2019'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '10577'
abstract:
- lang: eng
text: "State-of-the-art frameworks for generating approximate circuits automatically
explore the search space in an iterative process - often greedily. Synthesis and
verification processes are invoked in each iteration to evaluate the found solutions
and to guide the search algorithm. As a result, a large number of approximate
circuits is subjected to analysis - leading to long runtimes - but only a few
approximate circuits might form an acceptable solution.\r\n\r\nIn this paper,
we present our Jump Search (JS) method which seeks to reduce the runtime of an
approximation process by reducing the number of expensive synthesis and verification
steps. To reduce the runtime, JS computes impact factors for each approximation
candidate in the circuit to create a selection of approximate circuits without
invoking synthesis or verification processes. We denote the selection as path
from which JS determines the final solution. In our experimental results, JS achieved
speed-ups of up to 57x while area savings remain comparable to the reference search
method, Simulated Annealing."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY,
USA: ACM; 2019. doi:10.1145/3299874.3317998'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19.
New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998'
bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New
York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits}, DOI={10.1145/3299874.3317998},
booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi,
Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner,
VA, USA, 2019.'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium
on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.'
short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY,
USA, 2019.'
conference:
end_date: 2019-05-11
location: Tysons Corner, VA, USA
name: ACM Great Lakes Symposium on VLSI (GLSVLSI)
start_date: 2019-05-09
date_created: 2019-07-08T15:13:10Z
date_updated: 2022-01-06T06:50:45Z
department:
- _id: '78'
doi: 10.1145/3299874.3317998
keyword:
- Approximate computing
- design automation
- parameter selection
- circuit synthesis
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19
publication_identifier:
isbn:
- '9781450362528'
publication_status: published
publisher: ACM
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: conference
user_id: '49051'
year: '2019'
...
---
_id: '11950'
abstract:
- lang: eng
text: Advances in electromyographic (EMG) sensor technology and machine learning
algorithms have led to an increased research effort into high density EMG-based
pattern recognition methods for prosthesis control. With the goal set on an autonomous
multi-movement prosthesis capable of performing training and classification of
an amputee’s EMG signals, the focus of this paper lies in the acceleration of
the embedded signal processing chain. We present two Xilinx Zynq-based architectures
for accelerating two inherently different high density EMG-based control algorithms.
The first hardware accelerated design achieves speed-ups of up to 4.8 over the
software-only solution, allowing for a processing delay lower than the sample
period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only
version and operates at a still satisfactory low processing delay of up to 15
ms while providing a higher reliability and robustness against electrode shift
and noisy channels.
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Florian
full_name: Kraus, Florian
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based
acceleration of robust high density myoelectric signal processing. Journal
of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004
apa: Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., &
Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric
signal processing. Journal of Parallel and Distributed Computing, 123,
77–89. https://doi.org/10.1016/j.jpdc.2018.07.004
bibtex: '@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based
acceleration of robust high density myoelectric signal processing}, volume={123},
DOI={10.1016/j.jpdc.2018.07.004},
journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier},
author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen,
Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89}
}'
chicago: 'Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen,
Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing
123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.'
ieee: A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner,
“Zynq-based acceleration of robust high density myoelectric signal processing,”
Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
mla: Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing,
vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.
short: A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner,
Journal of Parallel and Distributed Computing 123 (2019) 77–89.
date_created: 2019-07-12T13:13:55Z
date_updated: 2022-01-06T06:51:13Z
department:
- _id: '78'
doi: 10.1016/j.jpdc.2018.07.004
intvolume: ' 123'
keyword:
- High density electromyography
- FPGA acceleration
- Medical signal processing
- Pattern recognition
- Prosthetics
language:
- iso: eng
page: 77-89
publication: Journal of Parallel and Distributed Computing
publication_identifier:
issn:
- 0743-7315
publication_status: published
publisher: Elsevier
status: public
title: Zynq-based acceleration of robust high density myoelectric signal processing
type: journal_article
user_id: '398'
volume: 123
year: '2019'
...
---
_id: '12967'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Md Jubaer Hossain
full_name: Pantho, Md Jubaer Hossain
last_name: Pantho
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution
Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of
Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y
apa: Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An
Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube
Technology. Journal of Signal Processing Systems, 91(11), 1259–1272.
https://doi.org/10.1007/s11265-018-1435-y
bibtex: '@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology},
volume={91}, DOI={10.1007/s11265-018-1435-y},
number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier,
Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019},
pages={1259–1272} }'
chicago: 'Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews.
“An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory
Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019):
1259–72. https://doi.org/10.1007/s11265-018-1435-y.'
ieee: T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,”
Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
mla: Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based
on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems,
vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.
short: T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing
Systems 91 (2019) 1259–1272.
date_created: 2019-08-26T13:41:57Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1007/s11265-018-1435-y
intvolume: ' 91'
issue: '11'
language:
- iso: eng
page: 1259 - 1272
publication: Journal of Signal Processing Systems
publication_identifier:
issn:
- 1939-8018
- 1939-8115
publication_status: published
status: public
title: An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory
Cube Technology
type: journal_article
user_id: '49992'
volume: 91
year: '2019'
...
---
_id: '15422'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache
Translation Functions of the LEON3 Processor. In: World Congress on Nature
and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically
Inspired Computing. Springer; 2019.'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor. In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Springer.
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and
Biologically Inspired Computing}, title={Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress
on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances
in Nature and Biologically Inspired Computing} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific
L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and
Biologically Inspired Computing. Springer, 2019.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on
Nature and Biologically Inspired Computing (NaBIC), 2019.
mla: Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation
Functions of the LEON3 Processor.” World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.'
date_created: 2019-12-30T13:55:49Z
date_updated: 2022-01-06T06:52:25Z
department:
- _id: '78'
language:
- iso: eng
publication: World Congress on Nature and Biologically Inspired Computing (NaBIC)
publisher: Springer
series_title: Advances in Nature and Biologically Inspired Computing
status: public
title: Optimization of Application-specific L1 Cache Translation Functions of the
LEON3 Processor
type: conference
user_id: '398'
year: '2019'
...
---
_id: '15883'
author:
- first_name: Shankar
full_name: Kumar Jeyakumar, Shankar
last_name: Kumar Jeyakumar
citation:
ama: Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded
Platforms.; 2019.
apa: Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine
on embedded platforms.
bibtex: '@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector
Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019}
}'
chicago: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms, 2019.
ieee: S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on
embedded platforms. 2019.
mla: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms. 2019.
short: S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded
Platforms, 2019.
date_created: 2020-02-11T16:43:38Z
date_updated: 2022-01-06T06:52:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
title: Incremental learning with Support Vector Machine on embedded platforms
type: mastersthesis
user_id: '61186'
year: '2019'
...
---
_id: '15920'
abstract:
- lang: eng
text: "Secure hardware design is the most important aspect to be considered in addition
to functional correctness. Achieving hardware security in today’s globalized Integrated
Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
It provides an ap- proach to verify that the systems adhere to security properties
either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
Hardware(PCH) is an approach to verify a functional design prior to using it in
hardware. It is a two-party verification approach, where the target party, the
consumer requests new functionalities with pre-defined properties to the producer.
In response, the producer designs the IP (Intellectual Property) cores with the
requested functionalities that adhere to the consumer-defined properties. The
producer provides the IP cores and a proof certificate combined into a proof-carrying
bitstream to the consumer to verify it. If the verification is successful, the
consumer can use the IP cores in his hardware. In essence, the consumer can only
run verified IP cores. Correctly applied, PCH techniques can help consumers to
defend against many unintentional modifications and malicious alterations of the
modules they receive. There are numerous published examples of how to use PCH
to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
with functional equivalence checking for combinational or sequential circuits.
For non-functional properties, since opening new covert channels to leak secret
information from secure circuits is a viable attack vector for hardware trojans,
i.e., intentionally added malicious circuitry, IFT technique is employed to make
sure that secret/untrusted information never reaches any unclassified/trusted
outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
level enabling consumers to validate the trustworthiness of a module’s information
flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
full_name: Keerthipati, Monica
last_name: Keerthipati
citation:
ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking. Universität Paderborn; 2019.
apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn.
bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
Monica}, year={2019} }'
chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for
Information Flow Tracking. Universität Paderborn, 2019.
mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
full_name: Sabu, Nithin S.
last_name: Sabu
citation:
ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets.
Paderborn University; 2019.
apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University.
bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
}'
chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University, 2019.
ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Stefan
full_name: Böttcher, Stefan
last_name: Böttcher
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '15946'
author:
- first_name: Jinay
full_name: Mehta, Jinay
last_name: Mehta
citation:
ama: "Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip.; 2019."
apa: "Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip."
bibtex: "@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip}, author={Mehta, Jinay},
year={2019} }"
chicago: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
ieee: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
mla: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
short: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
date_created: 2020-02-20T14:47:12Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: "Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable
System-on-Chip"
type: mastersthesis
user_id: '398'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.
apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn.
bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
Paderborn}, author={Hansmeier, Tim}, year={2019} }'
chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '31067'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic
Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027'
apa: Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE
International Parallel and Distributed Processing Symposium Workshops (IPDPSW).
https://doi.org/10.1109/ipdpsw.2019.00027
bibtex: '@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027},
booktitle={2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner,
Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }'
chicago: Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas.
“An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”
In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027.
ieee: 'Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping
Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.'
mla: Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks
to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.
short: 'Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.'
date_created: 2022-05-05T07:42:26Z
date_updated: 2022-05-05T07:43:29Z
department:
- _id: '78'
doi: 10.1109/ipdpsw.2019.00027
language:
- iso: eng
publication: 2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_status: published
publisher: IEEE
status: public
title: An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
type: conference
user_id: '398'
year: '2019'
...
---
_id: '9913'
abstract:
- lang: eng
text: Reconfigurable hardware has received considerable attention as a platform
that enables dynamic hardware updates and thus is able to adapt new configurations
at runtime. However, due to their dynamic nature, e.g., field-programmable gate
arrays (FPGA) are subject to a constant possibility of attacks, since each new
configuration might be compromised. Trojans for reconfigurable hardware that evade
state-of-the-art detection techniques and even formal verification, are thus a
large threat to these devices. One such stealthy hardware Trojan, that is inserted
and activated in two stages by compromised electronic design automation (EDA)
tools, has recently been presented and shown to evade all forms of classical pre-configuration
detection techniques. This paper presents a successful pre-configuration countermeasure
against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level
Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent
module creators to infected EDA tools, and to prohibit malicious ones to sell
infected modules to unsuspecting customers.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz
P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer
Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10'
apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware
Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson,
A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing
(Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture
Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10},
booktitle={Applied Reconfigurable Computing}, publisher={Springer International
Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco},
editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger
and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in
Computer Science} }'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable
Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger
Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham:
Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus
the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing,
Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.'
mla: Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious
LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian
Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36,
doi:10.1007/978-3-030-17227-5_10.
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch,
R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International
Publishing, Cham, 2019, pp. 127–136.'
conference:
end_date: 2019-04-11
location: Darmstadt, Germany
name: 15th International Symposium on Applied Reconfigurable Computing (ARC 2019)
start_date: 2019-04-09
date_created: 2019-05-22T07:36:05Z
date_updated: 2023-05-15T08:13:37Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-030-17227-5_10
editor:
- first_name: Christian
full_name: Hochberger, Christian
last_name: Hochberger
- first_name: Brent
full_name: Nelson, Brent
last_name: Nelson
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Roger
full_name: Woods, Roger
last_name: Woods
- first_name: Pedro
full_name: Diniz, Pedro
last_name: Diniz
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:12:33Z
date_updated: 2023-05-11T09:12:33Z
file_id: '44749'
file_name: 978-3-030-17227-5_10.pdf
file_size: 661354
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:12:33Z
has_accepted_license: '1'
intvolume: ' 11444'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 127-136
place: Cham
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: Applied Reconfigurable Computing
publication_identifier:
isbn:
- 978-3-030-17227-5
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan
type: conference
user_id: '72764'
volume: 11444
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
citation:
ama: Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS. Universität Paderborn
apa: Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
}'
chicago: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA
Operated with ReconOS. Universität Paderborn, n.d.
ieee: C. Lienen, Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
mla: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated
with ReconOS. Universität Paderborn.
short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
content_type: application/pdf
creator: clienen
date_created: 2020-07-01T11:46:49Z
date_updated: 2021-02-13T16:46:58Z
file_id: '17351'
file_name: thesis_main.pdf
file_size: 5920668
relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '12871'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published
online 2019. doi:10.1007/s00287-019-01187-w
apa: Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik
Spektrum. https://doi.org/10.1007/s00287-019-01187-w
bibtex: '@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w},
journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian},
year={2019} }'
chicago: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.
ieee: 'M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum,
2019, doi: 10.1007/s00287-019-01187-w.'
mla: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019, doi:10.1007/s00287-019-01187-w.
short: M. Platzner, C. Plessl, Informatik Spektrum (2019).
date_created: 2019-07-22T12:42:44Z
date_updated: 2023-09-26T11:45:57Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/s00287-019-01187-w
file:
- access_level: open_access
content_type: application/pdf
creator: plessl
date_created: 2019-07-22T12:45:02Z
date_updated: 2019-07-22T12:45:02Z
file_id: '12872'
file_name: plessl19_informatik_spektrum.pdf
file_size: 248360
relation: main_file
file_date_updated: 2019-07-22T12:45:02Z
has_accepted_license: '1'
language:
- iso: ger
oa: '1'
publication: Informatik Spektrum
publication_identifier:
issn:
- 0170-6012
- 1432-122X
publication_status: published
quality_controlled: '1'
status: public
title: FPGAs im Rechenzentrum
type: journal_article
user_id: '15278'
year: '2019'
...
---
_id: '52478'
author:
- first_name: Jinay D
full_name: Mehta, Jinay D
last_name: Mehta
citation:
ama: Mehta JD. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip.; 2019.
apa: Mehta, J. D. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip.
bibtex: '@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D},
year={2019} }'
chicago: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
ieee: J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip. 2019.
mla: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip. 2019.
short: J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
date_created: 2024-03-11T15:57:13Z
date_updated: 2024-03-11T15:57:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
title: Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable
System-on-Chip
type: mastersthesis
user_id: '74287'
year: '2019'
...
---
_id: '3362'
abstract:
- lang: eng
text: Profiling applications on a heterogeneous compute node is challenging since
the way to retrieve data from the resources and interpret them varies between
resource types and manufacturers. This holds especially true for measuring the
energy consumption. In this paper we present Ampehre, a novel open source measurement
framework that allows developers to gather comparable measurements from heterogeneous
compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture
of Ampehre and detail the measurement process on the example of energy measurements
on CPU and GPU. To characterize the probing effect, we quantitatively analyze
the trade-off between the accuracy of measurements and the CPU load imposed by
Ampehre. Based on this analysis, we are able to specify reasonable combinations
of sampling periods for the different resource types of a compute node.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes. In: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer
Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6'
apa: 'Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes. In Proceedings of the International
Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84).
Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6'
bibtex: '@inproceedings{Lösch_Wiens_Platzner_2018, place={Cham}, series={Lecture
Notes in Computer Science}, title={Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes}, volume={10793}, DOI={10.1007/978-3-319-77610-1_6},
booktitle={Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)}, publisher={Springer International Publishing}, author={Lösch,
Achim and Wiens, Alex and Platzner, Marco}, year={2018}, pages={73–84}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Lösch, Achim, Alex Wiens, and Marco Platzner. “Ampehre: An Open Source
Measurement Framework for Heterogeneous Compute Nodes.” In Proceedings of the
International Conference on Architecture of Computing Systems (ARCS), 10793:73–84.
Lecture Notes in Computer Science. Cham: Springer International Publishing, 2018.
https://doi.org/10.1007/978-3-319-77610-1_6.'
ieee: 'A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes,” in Proceedings of the International
Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793,
pp. 73–84.'
mla: 'Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous
Compute Nodes.” Proceedings of the International Conference on Architecture
of Computing Systems (ARCS), vol. 10793, Springer International Publishing,
2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.'
short: 'A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS), Springer International Publishing,
Cham, 2018, pp. 73–84.'
date_created: 2018-06-26T13:47:52Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-77610-1_6
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-06-26T13:58:28Z
date_updated: 2018-06-26T13:58:28Z
file_id: '3363'
file_name: loesch2017_arcs.pdf
file_size: 1114026
relation: main_file
success: 1
file_date_updated: 2018-06-26T13:58:28Z
has_accepted_license: '1'
intvolume: ' 10793'
page: 73-84
place: Cham
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)
publication_identifier:
isbn:
- '9783319776095'
- '9783319776101'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: 'Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes'
type: conference
user_id: '477'
volume: 10793
year: '2018'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
full_name: Schnuer, Jan-Philip
last_name: Schnuer
citation:
ama: Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn; 2018.
apa: Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn.
bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
year={2018} }'
chicago: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous
Compute Nodes. Universität Paderborn, 2018.
ieee: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn, 2018.
mla: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn, 2018.
short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
full_name: Croce, Marcel
last_name: Croce
citation:
ama: Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn; 2018.
apa: Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs.
Universität Paderborn.
bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
chicago: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs.
Universität Paderborn, 2018.
ieee: M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität
Paderborn, 2018.
mla: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn, 2018.
short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3373'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: 'Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution
Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures,
Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer
International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13'
apa: 'Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator
for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini,
Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13'
bibtex: '@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in
Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking},
volume={10824}, DOI={10.1007/978-3-319-78890-6_13},
booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications}, publisher={Springer International Publishing}, author={Hansmeier,
Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based
Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes
in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.'
ieee: 'T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator
for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824,
pp. 153–165.'
mla: 'Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof
Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools,
and Applications, vol. 10824, Springer International Publishing, 2018, pp.
153–65, doi:10.1007/978-3-319-78890-6_13.'
short: 'T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, Springer International Publishing,
2018, pp. 153–165.'
conference:
end_date: 2018-05-04
location: Santorini, Greece
name: 'ARC: International Symposium on Applied Reconfigurable Computing'
start_date: 2018-05-02
date_created: 2018-06-27T09:30:24Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-319-78890-6_13
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T13:55:07Z
date_updated: 2018-11-02T13:55:07Z
file_id: '5257'
file_name: AnFPGAHMC-BasedAcceleratorForR.pdf
file_size: 612367
relation: main_file
success: 1
file_date_updated: 2018-11-02T13:55:07Z
has_accepted_license: '1'
intvolume: ' 10824'
language:
- iso: eng
page: 153-165
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: 'ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications'
publication_identifier:
isbn:
- '9783319788890'
- '9783319788906'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: An FPGA/HMC-Based Accelerator for Resolution Proof Checking
type: conference
user_id: '3118'
volume: 10824
year: '2018'
...
---
_id: '3586'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Third Workshop on Approximate Computing (AxC 2018).'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Third Workshop on Approximate Computing
(AxC 2018), n.d.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Third Workshop on Approximate Computing (AxC 2018). .'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Third Workshop on Approximate
Computing (AxC 2018).'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Third Workshop on Approximate Computing (AxC 2018) (n.d.).
date_created: 2018-07-20T14:10:46Z
date_updated: 2022-01-06T06:59:26Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-07-20T14:13:31Z
date_updated: 2018-07-20T14:13:31Z
file_id: '3587'
file_name: WitschenWMAP2018.pdf
file_size: 285348
relation: main_file
success: 1
file_date_updated: 2018-07-20T14:13:31Z
has_accepted_license: '1'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: '6'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Third Workshop on Approximate Computing (AxC 2018)
publication_status: accepted
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
text: Traditional cache design uses a consolidated block of memory address bits
to index a cache set, equivalent to the use of modulo functions. While this module-based
mapping scheme is widely used in contemporary cache structures due to the simplicity
of its hardware design and its good performance for sequences of consecutive addresses,
its use may not be satisfactory for a variety of application domains having different
characteristics.This thesis presents a new type of cache mapping scheme, motivated
by programmable capabilities combined with Nature-inspired optimization of reconfigurable
hardware. This research has focussed on an FPGA-based evolvable cache structure
of the first level cache in a multi-core processor architecture, able to dynamically
change cache indexing. To solve the challenge of reconfigurable cache mappings,
a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
elements is proposed. Focusing on optimization aspects at the system level, a
Performance Measurement Infrastructure is introduced that is able to monitor the
underlying microarchitectural metrics, and an adaptive evaluation strategy is
presented that leverages on Evolutionary Algorithms, that is not only capable
of evolving application-specific address-to-cache-index mappings for level one
split caches but also of reducing optimization times. Putting this all together
and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
of a system architecture reduces cache misses and improves performance over the
use of conventional caches.
- lang: ger
text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
(LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
citation:
ama: 'Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376'
apa: 'Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design
and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376'
bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
Design and Optimization}, DOI={10.17619/UNIPB/1-376},
publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
chicago: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.'
ieee: 'N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018.'
mla: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.'
short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '1165'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate
Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for
Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing
(WAPCO 2018).
bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying
Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018}
}'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making
the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate
Computing (WAPCO 2018), 2018.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying
Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018).
2018.
mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate
Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.
short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing
(WAPCO 2018) (2018).
date_created: 2018-02-01T14:24:54Z
date_updated: 2022-01-06T06:51:06Z
ddc:
- '000'
department:
- _id: '7'
- _id: '34'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-11-26T08:00:53Z
date_updated: 2018-11-26T08:00:53Z
file_id: '5821'
file_name: WitschenWP2018[1].pdf
file_size: 287224
relation: main_file
success: 1
file_date_updated: 2018-11-26T08:00:53Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 4th Workshop On Approximate Computing (WAPCO 2018)
status: public
title: Making the Case for Proof-carrying Approximate Circuits
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '5547'
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on
Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on
Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018.
doi:10.1109/asap.2018.8445098'
apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP). Milan,
Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098'
bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model
for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098},
booktitle={2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and
Platzner, Marco}, year={2018} }'
chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International
Conference on Application-Specific Systems, Architectures and Processors (ASAP).
IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.
ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution
on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP), Milan,
Italy, 2018.
mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference
on Application-Specific Systems, Architectures and Processors (ASAP), IEEE,
2018, doi:10.1109/asap.2018.8445098.
short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific
Systems, Architectures and Processors (ASAP), IEEE, 2018.'
conference:
end_date: 2018-07-12
location: Milan, Italy
name: The 29th Annual IEEE International Conference on Application-specific Systems,
Architectures and Processors
start_date: 2018-07-10
date_created: 2018-11-14T09:26:53Z
date_updated: 2022-01-06T07:01:59Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/asap.2018.8445098
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:40:42Z
date_updated: 2018-11-14T09:40:42Z
file_id: '5552'
file_name: loesch_asap2018.pdf
file_size: 2464949
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:40:42Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: 2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)
publication_identifier:
isbn:
- '9781538674796'
publication_status: published
publisher: IEEE
status: public
title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute
Nodes
type: conference
user_id: '43646'
year: '2018'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...
---
_id: '10782'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: Clausing L. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.
apa: Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum.
bibtex: '@book{Clausing_2018, title={Development of a Hardware / Software Codesign
for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum},
author={Clausing, Lennart}, year={2018} }'
chicago: Clausing, Lennart. Development of a Hardware / Software Codesign for
Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
ieee: L. Clausing, Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum, 2018.
mla: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
short: L. Clausing, Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.
date_created: 2019-07-10T12:13:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: Ruhr-University Bochum
status: public
title: Development of a Hardware / Software Codesign for sonification of LIDAR-based
sensor data
type: mastersthesis
user_id: '3118'
year: '2018'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '12965'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh Ben
full_name: Abdallah, Riadh Ben
last_name: Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Zhiwu
full_name: Li, Zhiwu
last_name: Li
- first_name: Khalid
full_name: Alnowibet, Khalid
last_name: Alnowibet
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852'
apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner,
M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded
Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852'
bibtex: '@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints}, DOI={10.1109/access.2018.2799852},
journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui,
Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018},
pages={14078–14092} }'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet,
and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92.
https://doi.org/10.1109/access.2018.2799852.'
ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner,
“R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.'
mla: 'Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92,
doi:10.1109/access.2018.2799852.'
short: I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE
Access (2018) 14078–14092.
date_created: 2019-08-26T13:33:00Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1109/access.2018.2799852
language:
- iso: eng
page: 14078-14092
publication: IEEE Access
publication_identifier:
issn:
- 2169-3536
publication_status: published
status: public
title: 'R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints'
type: journal_article
user_id: '398'
year: '2018'
...
---
_id: '3580'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn; 2017.
apa: Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn.
bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution
Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017}
}'
chicago: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
ieee: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn, 2017.
mla: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität
Paderborn, 2017.
date_created: 2018-07-20T13:44:34Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: An FPGA Accelerator for Checking Resolution Proofs
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn; 2017.
apa: Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn.
bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
year={2017} }'
chicago: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate
Circuits. Universität Paderborn, 2017.
ieee: L. M. Witschen, A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
mla: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '74'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn; 2017.
apa: Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn.
bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017}
}'
chicago: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten. Universität Paderborn, 2017.
ieee: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
mla: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten,
Universität Paderborn, 2017.
date_created: 2017-10-17T12:41:05Z
date_updated: 2022-01-06T07:03:36Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '9919'
abstract:
- lang: eng
text: This is a study of a combined load restoration and generator start-up procedure.
The procedure is structured into three stages according to the power system status
and the goal of load restoration. Moreover, for each load restoration stage, the
proposed algorithm determines a load restoration sequence by considering renewable
energy such as solar and wind park to achieve objective functions. The validity
and performance of the proposed algorithm is demonstrated through simulations
using IEEE-39 network.
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology
Considering Renewable Energies. Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES). 2017;94:287-299. doi:10.1016/j.ijepes.2017.07.007
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration
Methodology Considering Renewable Energies. Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), 94, 287–299. https://doi.org/10.1016/j.ijepes.2017.07.007
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration
Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007},
journal={Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017},
pages={287–299} }'
chicago: 'Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System
Restoration Methodology Considering Renewable Energies.” Elsevier International
Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017): 287–99.
https://doi.org/10.1016/j.ijepes.2017.07.007.'
ieee: C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration
Methodology Considering Renewable Energies,” Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017.
mla: Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering
Renewable Energies.” Elsevier International Journal of Electrical Power and
Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.
short: C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES) 94 (2017) 287–299.
date_created: 2019-05-22T13:14:20Z
date_updated: 2019-10-06T21:56:18Z
department:
- _id: '78'
doi: 10.1016/j.ijepes.2017.07.007
intvolume: ' 94'
keyword:
- Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations
language:
- iso: eng
page: 287-299
publication: Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)
publication_status: published
status: public
title: Three-Stage Power System Restoration Methodology Considering Renewable Energies
type: journal_article
user_id: '3118'
volume: 94
year: '2017'
...
---
_id: '65'
abstract:
- lang: eng
text: Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators
have strongly gained interested in the last years. Applications differ in their
execution characteristics and can therefore benefit from such heterogeneous resources
in terms of performance or energy consumption. While performance optimization
has been the only goal for a long time, nowadays research is more and more focusing
on techniques to minimize energy consumption due to rising electricity costs.This
paper presents reMinMin, a novel static list scheduling approach for optimizing
the total energy consumption for a set of tasks executed on a heterogeneous compute
node. reMinMin bases on a new energy model that differentiates between static
and dynamic energy components and covers effects of accelerator tasks on the host
CPU. The required energy values are retrieved by measurements on the real computing
system. In order to evaluate reMinMin, we compare it with two reference implementations
on three task sets with different degrees of heterogeneity. In our experiments,
MinMin is consistently better than a scheduler optimizing for dynamic energy only,
which requires up to 19.43% more energy, and very close to optimal schedules.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE
International Conference on Application-Specific Systems, Architectures and Processors
(ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272'
apa: 'Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements. In Proceedings of the
28th Annual IEEE International Conference on Application-specific Systems, Architectures
and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272'
bibtex: '@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272},
booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner,
Marco}, year={2017} }'
chicago: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” In Proceedings of the
28th Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.'
ieee: 'A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE
International Conference on Application-specific Systems, Architectures and Processors
(ASAP), 2017.'
mla: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th
Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.'
short: 'A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International
Conference on Application-Specific Systems, Architectures and Processors (ASAP),
2017.'
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:08Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ASAP.2017.7995272
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:37:55Z
date_updated: 2018-11-14T09:37:55Z
file_id: '5550'
file_name: loesch_asap2017.pdf
file_size: 467545
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:37:55Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)
status: public
title: 'reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on
Real Measurements'
type: conference
user_id: '477'
year: '2017'
...
---
_id: '68'
abstract:
- lang: eng
text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically
reconfigurable hardware systems. The producer of a hardware module spends huge
effort when creating a proof for a safety policy. The proof is then transferred
as a certificate together with the configuration bitstream to the consumer of
the hardware module, who can quickly verify the given proof. Previous work utilized
SAT solvers and resolution traces to set up a PCH technology and corresponding
tool flows. In this article, we present a novel technology for PCH based on inductive
invariants. For sequential circuits, our approach is fundamentally stronger than
the previous SAT-based one since we avoid the limitations of bounded unrolling.
We contrast our technology to existing ones and show that it fits into previously
proposed tool flows. We conduct experiments with four categories of benchmark
circuits and report consumer and producer runtime and peak memory consumption,
as well as the size of the certificates and the distribution of the workload between
producer and consumer. Experiments clearly show that our new induction-based technology
is superior for sequential circuits, whereas the previous SAT-based technology
is the better choice for combinational circuits.
author:
- first_name: Tobias
full_name: Isenberg, Tobias
last_name: Isenberg
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via
Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems.
2017;(4):61:1--61:23. doi:10.1145/3054743
apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying
Hardware via Inductive Invariants. ACM Transactions on Design Automation of
Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743
bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying
Hardware via Inductive Invariants}, DOI={10.1145/3054743},
number={4}, journal={ACM Transactions on Design Automation of Electronic Systems},
publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike
and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }'
chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema.
“Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design
Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.'
ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware
via Inductive Invariants,” ACM Transactions on Design Automation of Electronic
Systems, no. 4, pp. 61:1--61:23, 2017.
mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”
ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM,
2017, pp. 61:1--61:23, doi:10.1145/3054743.
short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design
Automation of Electronic Systems (2017) 61:1--61:23.
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:20Z
ddc:
- '000'
department:
- _id: '77'
- _id: '78'
doi: 10.1145/3054743
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T16:08:17Z
date_updated: 2018-11-02T16:08:17Z
file_id: '5324'
file_name: a61-isenberg.pdf
file_size: 806356
relation: main_file
success: 1
file_date_updated: 2018-11-02T16:08:17Z
has_accepted_license: '1'
issue: '4'
language:
- iso: eng
page: 61:1--61:23
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: ACM Transactions on Design Automation of Electronic Systems
publisher: ACM
status: public
title: Proof-Carrying Hardware via Inductive Invariants
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10600'
author:
- first_name: Philip
full_name: H.W. Leong, Philip
last_name: H.W. Leong
- first_name: Hideharu
full_name: Amano, Hideharu
last_name: Amano
- first_name: Jason
full_name: Anderson, Jason
last_name: Anderson
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
- first_name: Jo\~{a}o
full_name: M.P. Cardoso, Jo\~{a}o
last_name: M.P. Cardoso
- first_name: Oliver
full_name: Diessel, Oliver
last_name: Diessel
- first_name: Guy
full_name: Gogniat, Guy
last_name: Gogniat
- first_name: Mike
full_name: Hutton, Mike
last_name: Hutton
- first_name: JunKyu
full_name: Lee, JunKyu
last_name: Lee
- first_name: Wayne
full_name: Luk, Wayne
last_name: Luk
- first_name: Patrick
full_name: Lysaght, Patrick
last_name: Lysaght
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Viktor
full_name: K. Prasanna, Viktor
last_name: K. Prasanna
- first_name: Tero
full_name: Rissa, Tero
last_name: Rissa
- first_name: Cristina
full_name: Silvano, Cristina
last_name: Silvano
- first_name: Hayden
full_name: So, Hayden
last_name: So
- first_name: Yu
full_name: Wang, Yu
last_name: Wang
citation:
ama: H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference
– Significant Papers. ACM Transactions on Reconfigurable Technology and Systems.
2017. doi:10.1145/2996468
apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel,
O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant
Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468
bibtex: '@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et
al._2017, title={The First 25 Years of the FPL Conference – Significant Papers},
DOI={10.1145/2996468}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip
and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o
and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk,
Wayne and et al.}, year={2017} }'
chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~{a}o
M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL
Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology
and Systems, 2017. https://doi.org/10.1145/2996468.
ieee: P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant
Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.
mla: H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant
Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017,
doi:10.1145/2996468.
short: P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel,
G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna,
T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology
and Systems (2017).
date_created: 2019-07-10T09:22:27Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1145/2996468
language:
- iso: eng
publication: ACM Transactions on Reconfigurable Technology and Systems
status: public
title: The First 25 Years of the FPL Conference – Significant Papers
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10601'
author:
- first_name: Ronald
full_name: F. DeMara, Ronald
last_name: F. DeMara
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Marco
full_name: Ottavi, Marco
last_name: Ottavi
citation:
ama: 'F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. 2017.
doi:10.1109/TETC.2016.2641599'
apa: 'F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599'
bibtex: '@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599},
journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco},
year={2017} }'
chicago: 'F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable
Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.
https://doi.org/10.1109/TETC.2016.2641599.'
ieee: 'R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.'
mla: 'F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics:
From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers
and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.'
short: R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and
IEEE Transactions on Emerging Topics in Computing (2017).
date_created: 2019-07-10T09:22:28Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TETC.2016.2641599
language:
- iso: eng
publication: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing
status: public
title: 'Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures
(guest editorial)'
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10611'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172.
doi:10.1016/j.micpro.2017.06.002
apa: Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus. Microprocessors and Microsystems,
160–172. https://doi.org/10.1016/j.micpro.2017.06.002
bibtex: '@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002},
journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer,
Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.
ieee: J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus,” Microprocessors and Microsystems, pp.
160–172, 2017.
mla: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.
short: J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.
date_created: 2019-07-10T09:23:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1016/j.micpro.2017.06.002
language:
- iso: eng
page: 160-172
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: Evaluating fault-tolerance of redundant FPGA structures using Boolean difference
calculus
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10613'
author:
- first_name: Christian
full_name: Kaltschmidt, Christian
last_name: Kaltschmidt
citation:
ama: Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University; 2017.
apa: Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University.
bibtex: '@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System
for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt,
Christian}, year={2017} }'
chicago: Kaltschmidt, Christian. An AR-Based Training and Assessment System for
Myoelectrical Prosthetic Control. Paderborn University, 2017.
ieee: C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
mla: Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
short: C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control, Paderborn University, 2017.
date_created: 2019-07-10T09:25:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: An AR-based Training and Assessment System for Myoelectrical Prosthetic Control
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '10630'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based
dynamically reconfigurable high density myoelectric prosthesis controller. In:
Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137'
apa: Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner,
M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137
bibtex: '@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller},
DOI={10.23919/DATE.2017.7927137},
booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander
and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner,
Marco}, year={2017} }'
chicago: Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens,
and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric
Prosthesis Controller.” In Design, Automation and Test in Europe (DATE),
2017. https://doi.org/10.23919/DATE.2017.7927137.
ieee: A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,”
in Design, Automation and Test in Europe (DATE), 2017.
mla: Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High
Density Myoelectric Prosthesis Controller.” Design, Automation and Test in
Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.
short: 'A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design,
Automation and Test in Europe (DATE), 2017.'
date_created: 2019-07-10T11:02:56Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927137
language:
- iso: eng
publication: Design, Automation and Test in Europe (DATE)
status: public
title: A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10666'
author:
- first_name: Umair
full_name: Riaz, Umair
last_name: Riaz
citation:
ama: Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University; 2017.
apa: Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University.
bibtex: '@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions
on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017}
}'
chicago: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
ieee: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University, 2017.
mla: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
short: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA,
Paderborn University, 2017.
date_created: 2019-07-10T11:15:10Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Acceleration of Industrial Analytics Functions on a Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2017'
...
---
_id: '10672'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Ishraq Ibne
full_name: Ashraf, Ishraq Ibne
last_name: Ashraf
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification
of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor.
In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096'
apa: 'Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE).
https://doi.org/10.23919/DATE.2017.7927096'
bibtex: '@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor}, DOI={10.23919/DATE.2017.7927096},
booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho,
Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017}
}'
chicago: 'Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate
Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for
the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe
Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.'
ieee: 'N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE),
2017.'
mla: 'Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses:
A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design,
Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.'
short: 'N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation
and Test in Europe Conf. (DATE), 2017.'
date_created: 2019-07-10T11:17:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927096
language:
- iso: eng
publication: Proc. Design, Automation and Test in Europe Conf. (DATE)
status: public
title: 'Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis
System for the LEON3 Multi-core Processor'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10692'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology
Considering Renewable Energies. Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES). 2017.
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration
Methodology Considering Renewable Energies. Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES).
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration
Methodology Considering Renewable Energies}, journal={Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann,
Paul and Braun, Martin}, year={2017} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System
Restoration Methodology Considering Renewable Energies.” Elsevier International
Journal of Electrical Power and Energy Systems (IJEPES), 2017.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration
Methodology Considering Renewable Energies,” Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), 2017.
mla: Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering
Renewable Energies.” Elsevier International Journal of Electrical Power and
Energy Systems (IJEPES), 2017.
short: C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES) (2017).
date_created: 2019-07-10T11:29:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
publication: Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)
status: public
title: Three-Stage Power System Restoration Methodology Considering Renewable Energies
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10708'
author:
- first_name: Andreas
full_name: Dietrich, Andreas
last_name: Dietrich
citation:
ama: Dietrich A. Reconfigurable Cryptographic Services. Paderborn University;
2017.
apa: Dietrich, A. (2017). Reconfigurable Cryptographic Services. Paderborn
University.
bibtex: '@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn
University}, author={Dietrich, Andreas}, year={2017} }'
chicago: Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn
University, 2017.
ieee: A. Dietrich, Reconfigurable Cryptographic Services. Paderborn University,
2017.
mla: Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn
University, 2017.
short: A. Dietrich, Reconfigurable Cryptographic Services, Paderborn University,
2017.
date_created: 2019-07-10T11:43:32Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Reconfigurable Cryptographic Services
type: mastersthesis
user_id: '3118'
year: '2017'
...
---
_id: '10740'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel
Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Fast Network Restoration by
Partitioning of Parallel Black Start Zones. The Journal of Engineering,
19pp. https://doi.org/10.1049/joe.2017.0032
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning
of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032},
journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and
Braun, Martin}, year={2017}, pages={19pp} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Fast Network Restoration
by Partitioning of Parallel Black Start Zones.” The Journal of Engineering,
2017, 19pp. https://doi.org/10.1049/joe.2017.0032.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning
of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.
mla: Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black
Start Zones.” The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032.
short: C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017) 19pp.
date_created: 2019-07-10T11:59:38Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1049/joe.2017.0032
page: 19pp
publication: The Journal of Engineering
status: public
title: Fast Network Restoration by Partitioning of Parallel Black Start Zones
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10759'
author:
- first_name: Giovanni
full_name: Squillero, Giovanni
last_name: Squillero
- first_name: Paolo
full_name: Burelli, Paolo
last_name: Burelli
- first_name: Antonio
full_name: M. Mora, Antonio
last_name: M. Mora
- first_name: Alexandros
full_name: Agapitos, Alexandros
last_name: Agapitos
- first_name: William
full_name: S. Bush, William
last_name: S. Bush
- first_name: Stefano
full_name: Cagnoni, Stefano
last_name: Cagnoni
- first_name: Carlos
full_name: Cotta, Carlos
last_name: Cotta
- first_name: Ivanoe
full_name: De Falco, Ivanoe
last_name: De Falco
- first_name: Antonio
full_name: Della Cioppa, Antonio
last_name: Della Cioppa
- first_name: Federico
full_name: Divina, Federico
last_name: Divina
- first_name: A.E.
full_name: Eiben, A.E.
last_name: Eiben
- first_name: Anna
full_name: I. Esparcia-Alc{\'a}zar, Anna
last_name: I. Esparcia-Alc{\'a}zar
- first_name: Francisco
full_name: Fern{\'a}ndez de Vega, Francisco
last_name: Fern{\'a}ndez de Vega
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Evert
full_name: Haasdijk, Evert
last_name: Haasdijk
- first_name: J.
full_name: Ignacio Hidalgo, J.
last_name: Ignacio Hidalgo
- first_name: Michael
full_name: Kampouridis, Michael
last_name: Kampouridis
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Michalis
full_name: Mavrovouniotis, Michalis
last_name: Mavrovouniotis
- first_name: Trung
full_name: Thanh Nguyen, Trung
last_name: Thanh Nguyen
- first_name: Robert
full_name: Schaefer, Robert
last_name: Schaefer
- first_name: Kevin
full_name: Sim, Kevin
last_name: Sim
- first_name: Ernesto
full_name: Tarantino, Ernesto
last_name: Tarantino
- first_name: Neil
full_name: Urquhart, Neil
last_name: Urquhart
- first_name: Mengjie
full_name: Zhang (editors), Mengjie
last_name: Zhang (editors)
citation:
ama: Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation
- 20th European Conference, EvoApplications. Springer; 2017.
apa: Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni,
S., … Zhang (editors), M. (2017). Applications of Evolutionary Computation
- 20th European Conference, EvoApplications. Springer.
bibtex: '@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della
Cioppa_Divina_et al._2017, series={Lecture Notes in Computer Science}, title={Applications
of Evolutionary Computation - 20th European Conference, EvoApplications}, publisher={Springer},
author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos,
Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De
Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2017},
collection={Lecture Notes in Computer Science} }'
chicago: Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos,
William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary
Computation - 20th European Conference, EvoApplications. Lecture Notes in
Computer Science. Springer, 2017.
ieee: G. Squillero et al., Applications of Evolutionary Computation -
20th European Conference, EvoApplications. Springer, 2017.
mla: Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th
European Conference, EvoApplications. Springer, 2017.
short: G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni,
C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\’a}zar,
F. Fern{\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis,
P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino,
N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 20th
European Conference, EvoApplications, Springer, 2017.
date_created: 2019-07-10T12:06:37Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 20th European Conference, EvoApplications
type: book
user_id: '3118'
year: '2017'
...
---
_id: '10760'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Roman
full_name: Kalkreuth, Roman
last_name: Kalkreuth
citation:
ama: 'Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical
Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German
Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26'
apa: 'Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic
Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26'
bibtex: '@inproceedings{Kaufmann_Kalkreuth_2017, title={Parametrizing Cartesian
Genetic Programming: An Empirical Study}, DOI={10.1007/978-3-319-67190-1_26},
booktitle={KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference
on AI}, publisher={Springer International Publishing}, author={Kaufmann, Paul
and Kalkreuth, Roman}, year={2017} }'
chicago: 'Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic
Programming: An Empirical Study.” In KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI. Springer International Publishing, 2017.
https://doi.org/10.1007/978-3-319-67190-1_26.'
ieee: 'P. Kaufmann and R. Kalkreuth, “Parametrizing Cartesian Genetic Programming:
An Empirical Study,” in KI 2017: Advances in Artificial Intelligence: 40th
Annual German Conference on AI, 2017.'
mla: 'Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming:
An Empirical Study.” KI 2017: Advances in Artificial Intelligence: 40th Annual
German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.'
short: 'P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI, Springer International Publishing, 2017.'
date_created: 2019-07-10T12:06:38Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1007/978-3-319-67190-1_26
language:
- iso: eng
publication: 'KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference
on AI'
publisher: Springer International Publishing
status: public
title: 'Parametrizing Cartesian Genetic Programming: An Empirical Study'
type: conference
user_id: '3118'
year: '2017'
...