---
_id: '12967'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Md Jubaer Hossain
full_name: Pantho, Md Jubaer Hossain
last_name: Pantho
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution
Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of
Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y
apa: Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An
Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube
Technology. Journal of Signal Processing Systems, 91(11), 1259–1272.
https://doi.org/10.1007/s11265-018-1435-y
bibtex: '@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology},
volume={91}, DOI={10.1007/s11265-018-1435-y},
number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier,
Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019},
pages={1259–1272} }'
chicago: 'Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews.
“An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory
Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019):
1259–72. https://doi.org/10.1007/s11265-018-1435-y.'
ieee: T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,”
Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
mla: Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based
on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems,
vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.
short: T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing
Systems 91 (2019) 1259–1272.
date_created: 2019-08-26T13:41:57Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1007/s11265-018-1435-y
intvolume: ' 91'
issue: '11'
language:
- iso: eng
page: 1259 - 1272
publication: Journal of Signal Processing Systems
publication_identifier:
issn:
- 1939-8018
- 1939-8115
publication_status: published
status: public
title: An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory
Cube Technology
type: journal_article
user_id: '49992'
volume: 91
year: '2019'
...
---
_id: '15422'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache
Translation Functions of the LEON3 Processor. In: World Congress on Nature
and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically
Inspired Computing. Springer; 2019.'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor. In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Springer.
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and
Biologically Inspired Computing}, title={Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress
on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances
in Nature and Biologically Inspired Computing} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific
L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and
Biologically Inspired Computing. Springer, 2019.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on
Nature and Biologically Inspired Computing (NaBIC), 2019.
mla: Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation
Functions of the LEON3 Processor.” World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.'
date_created: 2019-12-30T13:55:49Z
date_updated: 2022-01-06T06:52:25Z
department:
- _id: '78'
language:
- iso: eng
publication: World Congress on Nature and Biologically Inspired Computing (NaBIC)
publisher: Springer
series_title: Advances in Nature and Biologically Inspired Computing
status: public
title: Optimization of Application-specific L1 Cache Translation Functions of the
LEON3 Processor
type: conference
user_id: '398'
year: '2019'
...
---
_id: '15883'
author:
- first_name: Shankar
full_name: Kumar Jeyakumar, Shankar
last_name: Kumar Jeyakumar
citation:
ama: Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded
Platforms.; 2019.
apa: Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine
on embedded platforms.
bibtex: '@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector
Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019}
}'
chicago: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms, 2019.
ieee: S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on
embedded platforms. 2019.
mla: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms. 2019.
short: S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded
Platforms, 2019.
date_created: 2020-02-11T16:43:38Z
date_updated: 2022-01-06T06:52:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
title: Incremental learning with Support Vector Machine on embedded platforms
type: mastersthesis
user_id: '61186'
year: '2019'
...
---
_id: '15920'
abstract:
- lang: eng
text: "Secure hardware design is the most important aspect to be considered in addition
to functional correctness. Achieving hardware security in today’s globalized Integrated
Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
It provides an ap- proach to verify that the systems adhere to security properties
either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
Hardware(PCH) is an approach to verify a functional design prior to using it in
hardware. It is a two-party verification approach, where the target party, the
consumer requests new functionalities with pre-defined properties to the producer.
In response, the producer designs the IP (Intellectual Property) cores with the
requested functionalities that adhere to the consumer-defined properties. The
producer provides the IP cores and a proof certificate combined into a proof-carrying
bitstream to the consumer to verify it. If the verification is successful, the
consumer can use the IP cores in his hardware. In essence, the consumer can only
run verified IP cores. Correctly applied, PCH techniques can help consumers to
defend against many unintentional modifications and malicious alterations of the
modules they receive. There are numerous published examples of how to use PCH
to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
with functional equivalence checking for combinational or sequential circuits.
For non-functional properties, since opening new covert channels to leak secret
information from secure circuits is a viable attack vector for hardware trojans,
i.e., intentionally added malicious circuitry, IFT technique is employed to make
sure that secret/untrusted information never reaches any unclassified/trusted
outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
level enabling consumers to validate the trustworthiness of a module’s information
flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
full_name: Keerthipati, Monica
last_name: Keerthipati
citation:
ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking. Universität Paderborn; 2019.
apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn.
bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
Monica}, year={2019} }'
chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for
Information Flow Tracking. Universität Paderborn, 2019.
mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
full_name: Sabu, Nithin S.
last_name: Sabu
citation:
ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets.
Paderborn University; 2019.
apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University.
bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
}'
chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University, 2019.
ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Stefan
full_name: Böttcher, Stefan
last_name: Böttcher
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '15946'
author:
- first_name: Jinay
full_name: Mehta, Jinay
last_name: Mehta
citation:
ama: "Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip.; 2019."
apa: "Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip."
bibtex: "@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip}, author={Mehta, Jinay},
year={2019} }"
chicago: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
ieee: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
mla: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
short: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
date_created: 2020-02-20T14:47:12Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: "Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable
System-on-Chip"
type: mastersthesis
user_id: '398'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.
apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn.
bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
Paderborn}, author={Hansmeier, Tim}, year={2019} }'
chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '31067'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic
Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027'
apa: Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE
International Parallel and Distributed Processing Symposium Workshops (IPDPSW).
https://doi.org/10.1109/ipdpsw.2019.00027
bibtex: '@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027},
booktitle={2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner,
Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }'
chicago: Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas.
“An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”
In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027.
ieee: 'Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping
Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.'
mla: Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks
to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.
short: 'Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.'
date_created: 2022-05-05T07:42:26Z
date_updated: 2022-05-05T07:43:29Z
department:
- _id: '78'
doi: 10.1109/ipdpsw.2019.00027
language:
- iso: eng
publication: 2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_status: published
publisher: IEEE
status: public
title: An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
type: conference
user_id: '398'
year: '2019'
...
---
_id: '52478'
author:
- first_name: Jinay D
full_name: Mehta, Jinay D
last_name: Mehta
citation:
ama: Mehta JD. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip.; 2019.
apa: Mehta, J. D. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip.
bibtex: '@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D},
year={2019} }'
chicago: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
ieee: J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Reconfigurable System-on-Chip. 2019.
mla: Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip. 2019.
short: J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Reconfigurable System-on-Chip, 2019.
date_created: 2024-03-11T15:57:13Z
date_updated: 2024-03-11T15:57:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
title: Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable
System-on-Chip
type: mastersthesis
user_id: '74287'
year: '2019'
...
---
_id: '9913'
abstract:
- lang: eng
text: Reconfigurable hardware has received considerable attention as a platform
that enables dynamic hardware updates and thus is able to adapt new configurations
at runtime. However, due to their dynamic nature, e.g., field-programmable gate
arrays (FPGA) are subject to a constant possibility of attacks, since each new
configuration might be compromised. Trojans for reconfigurable hardware that evade
state-of-the-art detection techniques and even formal verification, are thus a
large threat to these devices. One such stealthy hardware Trojan, that is inserted
and activated in two stages by compromised electronic design automation (EDA)
tools, has recently been presented and shown to evade all forms of classical pre-configuration
detection techniques. This paper presents a successful pre-configuration countermeasure
against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level
Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent
module creators to infected EDA tools, and to prohibit malicious ones to sell
infected modules to unsuspecting customers.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz
P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer
Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10'
apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware
Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson,
A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing
(Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture
Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy
Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10},
booktitle={Applied Reconfigurable Computing}, publisher={Springer International
Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco},
editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger
and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in
Computer Science} }'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable
Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger
Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham:
Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus
the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing,
Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.'
mla: Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious
LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian
Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36,
doi:10.1007/978-3-030-17227-5_10.
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch,
R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International
Publishing, Cham, 2019, pp. 127–136.'
conference:
end_date: 2019-04-11
location: Darmstadt, Germany
name: 15th International Symposium on Applied Reconfigurable Computing (ARC 2019)
start_date: 2019-04-09
date_created: 2019-05-22T07:36:05Z
date_updated: 2023-05-15T08:13:37Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-030-17227-5_10
editor:
- first_name: Christian
full_name: Hochberger, Christian
last_name: Hochberger
- first_name: Brent
full_name: Nelson, Brent
last_name: Nelson
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Roger
full_name: Woods, Roger
last_name: Woods
- first_name: Pedro
full_name: Diniz, Pedro
last_name: Diniz
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:12:33Z
date_updated: 2023-05-11T09:12:33Z
file_id: '44749'
file_name: 978-3-030-17227-5_10.pdf
file_size: 661354
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:12:33Z
has_accepted_license: '1'
intvolume: ' 11444'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 127-136
place: Cham
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: Applied Reconfigurable Computing
publication_identifier:
isbn:
- 978-3-030-17227-5
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan
type: conference
user_id: '72764'
volume: 11444
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
citation:
ama: Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS. Universität Paderborn
apa: Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
}'
chicago: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA
Operated with ReconOS. Universität Paderborn, n.d.
ieee: C. Lienen, Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
mla: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated
with ReconOS. Universität Paderborn.
short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
content_type: application/pdf
creator: clienen
date_created: 2020-07-01T11:46:49Z
date_updated: 2021-02-13T16:46:58Z
file_id: '17351'
file_name: thesis_main.pdf
file_size: 5920668
relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
license: https://creativecommons.org/licenses/by/4.0/
oa: '1'
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '12871'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published
online 2019. doi:10.1007/s00287-019-01187-w
apa: Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik
Spektrum. https://doi.org/10.1007/s00287-019-01187-w
bibtex: '@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w},
journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian},
year={2019} }'
chicago: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.
ieee: 'M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum,
2019, doi: 10.1007/s00287-019-01187-w.'
mla: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik
Spektrum, 2019, doi:10.1007/s00287-019-01187-w.
short: M. Platzner, C. Plessl, Informatik Spektrum (2019).
date_created: 2019-07-22T12:42:44Z
date_updated: 2023-09-26T11:45:57Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/s00287-019-01187-w
file:
- access_level: open_access
content_type: application/pdf
creator: plessl
date_created: 2019-07-22T12:45:02Z
date_updated: 2019-07-22T12:45:02Z
file_id: '12872'
file_name: plessl19_informatik_spektrum.pdf
file_size: 248360
relation: main_file
file_date_updated: 2019-07-22T12:45:02Z
has_accepted_license: '1'
language:
- iso: ger
oa: '1'
publication: Informatik Spektrum
publication_identifier:
issn:
- 0170-6012
- 1432-122X
publication_status: published
quality_controlled: '1'
status: public
title: FPGAs im Rechenzentrum
type: journal_article
user_id: '15278'
year: '2019'
...
---
_id: '3362'
abstract:
- lang: eng
text: Profiling applications on a heterogeneous compute node is challenging since
the way to retrieve data from the resources and interpret them varies between
resource types and manufacturers. This holds especially true for measuring the
energy consumption. In this paper we present Ampehre, a novel open source measurement
framework that allows developers to gather comparable measurements from heterogeneous
compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture
of Ampehre and detail the measurement process on the example of energy measurements
on CPU and GPU. To characterize the probing effect, we quantitatively analyze
the trade-off between the accuracy of measurements and the CPU load imposed by
Ampehre. Based on this analysis, we are able to specify reasonable combinations
of sampling periods for the different resource types of a compute node.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Wiens A, Platzner M. Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes. In: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS). Vol 10793. Lecture Notes in Computer
Science. Cham: Springer International Publishing; 2018:73-84. doi:10.1007/978-3-319-77610-1_6'
apa: 'Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes. In Proceedings of the International
Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84).
Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6'
bibtex: '@inproceedings{Lösch_Wiens_Platzner_2018, place={Cham}, series={Lecture
Notes in Computer Science}, title={Ampehre: An Open Source Measurement Framework
for Heterogeneous Compute Nodes}, volume={10793}, DOI={10.1007/978-3-319-77610-1_6},
booktitle={Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)}, publisher={Springer International Publishing}, author={Lösch,
Achim and Wiens, Alex and Platzner, Marco}, year={2018}, pages={73–84}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Lösch, Achim, Alex Wiens, and Marco Platzner. “Ampehre: An Open Source
Measurement Framework for Heterogeneous Compute Nodes.” In Proceedings of the
International Conference on Architecture of Computing Systems (ARCS), 10793:73–84.
Lecture Notes in Computer Science. Cham: Springer International Publishing, 2018.
https://doi.org/10.1007/978-3-319-77610-1_6.'
ieee: 'A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement
Framework for Heterogeneous Compute Nodes,” in Proceedings of the International
Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793,
pp. 73–84.'
mla: 'Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous
Compute Nodes.” Proceedings of the International Conference on Architecture
of Computing Systems (ARCS), vol. 10793, Springer International Publishing,
2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.'
short: 'A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference
on Architecture of Computing Systems (ARCS), Springer International Publishing,
Cham, 2018, pp. 73–84.'
date_created: 2018-06-26T13:47:52Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-77610-1_6
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-06-26T13:58:28Z
date_updated: 2018-06-26T13:58:28Z
file_id: '3363'
file_name: loesch2017_arcs.pdf
file_size: 1114026
relation: main_file
success: 1
file_date_updated: 2018-06-26T13:58:28Z
has_accepted_license: '1'
intvolume: ' 10793'
page: 73-84
place: Cham
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: Proceedings of the International Conference on Architecture of Computing
Systems (ARCS)
publication_identifier:
isbn:
- '9783319776095'
- '9783319776101'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: 'Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes'
type: conference
user_id: '477'
volume: 10793
year: '2018'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
full_name: Schnuer, Jan-Philip
last_name: Schnuer
citation:
ama: Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn; 2018.
apa: Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn.
bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
year={2018} }'
chicago: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous
Compute Nodes. Universität Paderborn, 2018.
ieee: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn, 2018.
mla: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn, 2018.
short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
full_name: Croce, Marcel
last_name: Croce
citation:
ama: Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn; 2018.
apa: Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs.
Universität Paderborn.
bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
chicago: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs.
Universität Paderborn, 2018.
ieee: M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität
Paderborn, 2018.
mla: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn, 2018.
short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3373'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: 'Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution
Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures,
Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer
International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13'
apa: 'Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator
for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini,
Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13'
bibtex: '@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in
Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking},
volume={10824}, DOI={10.1007/978-3-319-78890-6_13},
booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications}, publisher={Springer International Publishing}, author={Hansmeier,
Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based
Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes
in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.'
ieee: 'T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator
for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing.
Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824,
pp. 153–165.'
mla: 'Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof
Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools,
and Applications, vol. 10824, Springer International Publishing, 2018, pp.
153–65, doi:10.1007/978-3-319-78890-6_13.'
short: 'T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable
Computing. Architectures, Tools, and Applications, Springer International Publishing,
2018, pp. 153–165.'
conference:
end_date: 2018-05-04
location: Santorini, Greece
name: 'ARC: International Symposium on Applied Reconfigurable Computing'
start_date: 2018-05-02
date_created: 2018-06-27T09:30:24Z
date_updated: 2022-01-06T06:59:13Z
ddc:
- '000'
department:
- _id: '78'
doi: 10.1007/978-3-319-78890-6_13
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T13:55:07Z
date_updated: 2018-11-02T13:55:07Z
file_id: '5257'
file_name: AnFPGAHMC-BasedAcceleratorForR.pdf
file_size: 612367
relation: main_file
success: 1
file_date_updated: 2018-11-02T13:55:07Z
has_accepted_license: '1'
intvolume: ' 10824'
language:
- iso: eng
page: 153-165
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication: 'ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and
Applications'
publication_identifier:
isbn:
- '9783319788890'
- '9783319788906'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: An FPGA/HMC-Based Accelerator for Resolution Proof Checking
type: conference
user_id: '3118'
volume: 10824
year: '2018'
...
---
_id: '3586'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Third Workshop on Approximate Computing (AxC 2018).'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Third Workshop on Approximate Computing
(AxC 2018), n.d.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Third Workshop on Approximate Computing (AxC 2018). .'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Third Workshop on Approximate
Computing (AxC 2018).'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Third Workshop on Approximate Computing (AxC 2018) (n.d.).
date_created: 2018-07-20T14:10:46Z
date_updated: 2022-01-06T06:59:26Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-07-20T14:13:31Z
date_updated: 2018-07-20T14:13:31Z
file_id: '3587'
file_name: WitschenWMAP2018.pdf
file_size: 285348
relation: main_file
success: 1
file_date_updated: 2018-07-20T14:13:31Z
has_accepted_license: '1'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: '6'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Third Workshop on Approximate Computing (AxC 2018)
publication_status: accepted
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
text: Traditional cache design uses a consolidated block of memory address bits
to index a cache set, equivalent to the use of modulo functions. While this module-based
mapping scheme is widely used in contemporary cache structures due to the simplicity
of its hardware design and its good performance for sequences of consecutive addresses,
its use may not be satisfactory for a variety of application domains having different
characteristics.This thesis presents a new type of cache mapping scheme, motivated
by programmable capabilities combined with Nature-inspired optimization of reconfigurable
hardware. This research has focussed on an FPGA-based evolvable cache structure
of the first level cache in a multi-core processor architecture, able to dynamically
change cache indexing. To solve the challenge of reconfigurable cache mappings,
a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
elements is proposed. Focusing on optimization aspects at the system level, a
Performance Measurement Infrastructure is introduced that is able to monitor the
underlying microarchitectural metrics, and an adaptive evaluation strategy is
presented that leverages on Evolutionary Algorithms, that is not only capable
of evolving application-specific address-to-cache-index mappings for level one
split caches but also of reducing optimization times. Putting this all together
and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
of a system architecture reduces cache misses and improves performance over the
use of conventional caches.
- lang: ger
text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
(LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
citation:
ama: 'Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376'
apa: 'Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design
and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376'
bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
Design and Optimization}, DOI={10.17619/UNIPB/1-376},
publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
chicago: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.'
ieee: 'N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018.'
mla: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.'
short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '1165'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate
Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for
Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing
(WAPCO 2018).
bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying
Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018}
}'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making
the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate
Computing (WAPCO 2018), 2018.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying
Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018).
2018.
mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate
Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.
short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing
(WAPCO 2018) (2018).
date_created: 2018-02-01T14:24:54Z
date_updated: 2022-01-06T06:51:06Z
ddc:
- '000'
department:
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- _id: '34'
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file:
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content_type: application/pdf
creator: tobias82
date_created: 2018-11-26T08:00:53Z
date_updated: 2018-11-26T08:00:53Z
file_id: '5821'
file_name: WitschenWP2018[1].pdf
file_size: 287224
relation: main_file
success: 1
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has_accepted_license: '1'
language:
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project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 4th Workshop On Approximate Computing (WAPCO 2018)
status: public
title: Making the Case for Proof-carrying Approximate Circuits
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '5547'
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on
Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on
Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018.
doi:10.1109/asap.2018.8445098'
apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP). Milan,
Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098'
bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model
for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098},
booktitle={2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and
Platzner, Marco}, year={2018} }'
chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International
Conference on Application-Specific Systems, Architectures and Processors (ASAP).
IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.
ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution
on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP), Milan,
Italy, 2018.
mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference
on Application-Specific Systems, Architectures and Processors (ASAP), IEEE,
2018, doi:10.1109/asap.2018.8445098.
short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific
Systems, Architectures and Processors (ASAP), IEEE, 2018.'
conference:
end_date: 2018-07-12
location: Milan, Italy
name: The 29th Annual IEEE International Conference on Application-specific Systems,
Architectures and Processors
start_date: 2018-07-10
date_created: 2018-11-14T09:26:53Z
date_updated: 2022-01-06T07:01:59Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/asap.2018.8445098
file:
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content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:40:42Z
date_updated: 2018-11-14T09:40:42Z
file_id: '5552'
file_name: loesch_asap2018.pdf
file_size: 2464949
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:40:42Z
has_accepted_license: '1'
language:
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project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: 2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)
publication_identifier:
isbn:
- '9781538674796'
publication_status: published
publisher: IEEE
status: public
title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute
Nodes
type: conference
user_id: '43646'
year: '2018'
...