---
_id: '1165'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate
Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for
Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing
(WAPCO 2018).
bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying
Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018}
}'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making
the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate
Computing (WAPCO 2018), 2018.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying
Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018).
2018.
mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate
Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.
short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing
(WAPCO 2018) (2018).
date_created: 2018-02-01T14:24:54Z
date_updated: 2022-01-06T06:51:06Z
ddc:
- '000'
department:
- _id: '7'
- _id: '34'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-11-26T08:00:53Z
date_updated: 2018-11-26T08:00:53Z
file_id: '5821'
file_name: WitschenWP2018[1].pdf
file_size: 287224
relation: main_file
success: 1
file_date_updated: 2018-11-26T08:00:53Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 4th Workshop On Approximate Computing (WAPCO 2018)
status: public
title: Making the Case for Proof-carrying Approximate Circuits
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '5547'
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on
Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on
Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018.
doi:10.1109/asap.2018.8445098'
apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP). Milan,
Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098'
bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model
for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098},
booktitle={2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and
Platzner, Marco}, year={2018} }'
chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International
Conference on Application-Specific Systems, Architectures and Processors (ASAP).
IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.
ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution
on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP), Milan,
Italy, 2018.
mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference
on Application-Specific Systems, Architectures and Processors (ASAP), IEEE,
2018, doi:10.1109/asap.2018.8445098.
short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific
Systems, Architectures and Processors (ASAP), IEEE, 2018.'
conference:
end_date: 2018-07-12
location: Milan, Italy
name: The 29th Annual IEEE International Conference on Application-specific Systems,
Architectures and Processors
start_date: 2018-07-10
date_created: 2018-11-14T09:26:53Z
date_updated: 2022-01-06T07:01:59Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/asap.2018.8445098
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:40:42Z
date_updated: 2018-11-14T09:40:42Z
file_id: '5552'
file_name: loesch_asap2018.pdf
file_size: 2464949
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:40:42Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: 2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)
publication_identifier:
isbn:
- '9781538674796'
publication_status: published
publisher: IEEE
status: public
title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute
Nodes
type: conference
user_id: '43646'
year: '2018'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...
---
_id: '10782'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: Clausing L. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.
apa: Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum.
bibtex: '@book{Clausing_2018, title={Development of a Hardware / Software Codesign
for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum},
author={Clausing, Lennart}, year={2018} }'
chicago: Clausing, Lennart. Development of a Hardware / Software Codesign for
Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
ieee: L. Clausing, Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum, 2018.
mla: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
short: L. Clausing, Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.
date_created: 2019-07-10T12:13:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: Ruhr-University Bochum
status: public
title: Development of a Hardware / Software Codesign for sonification of LIDAR-based
sensor data
type: mastersthesis
user_id: '3118'
year: '2018'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '12965'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh Ben
full_name: Abdallah, Riadh Ben
last_name: Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Zhiwu
full_name: Li, Zhiwu
last_name: Li
- first_name: Khalid
full_name: Alnowibet, Khalid
last_name: Alnowibet
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852'
apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner,
M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded
Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852'
bibtex: '@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints}, DOI={10.1109/access.2018.2799852},
journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui,
Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018},
pages={14078–14092} }'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet,
and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92.
https://doi.org/10.1109/access.2018.2799852.'
ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner,
“R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.'
mla: 'Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92,
doi:10.1109/access.2018.2799852.'
short: I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE
Access (2018) 14078–14092.
date_created: 2019-08-26T13:33:00Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1109/access.2018.2799852
language:
- iso: eng
page: 14078-14092
publication: IEEE Access
publication_identifier:
issn:
- 2169-3536
publication_status: published
status: public
title: 'R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints'
type: journal_article
user_id: '398'
year: '2018'
...
---
_id: '3580'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn; 2017.
apa: Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn.
bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution
Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017}
}'
chicago: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
ieee: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn, 2017.
mla: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität
Paderborn, 2017.
date_created: 2018-07-20T13:44:34Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: An FPGA Accelerator for Checking Resolution Proofs
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn; 2017.
apa: Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn.
bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
year={2017} }'
chicago: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate
Circuits. Universität Paderborn, 2017.
ieee: L. M. Witschen, A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
mla: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '74'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn; 2017.
apa: Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn.
bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017}
}'
chicago: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten. Universität Paderborn, 2017.
ieee: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
mla: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten,
Universität Paderborn, 2017.
date_created: 2017-10-17T12:41:05Z
date_updated: 2022-01-06T07:03:36Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '9919'
abstract:
- lang: eng
text: This is a study of a combined load restoration and generator start-up procedure.
The procedure is structured into three stages according to the power system status
and the goal of load restoration. Moreover, for each load restoration stage, the
proposed algorithm determines a load restoration sequence by considering renewable
energy such as solar and wind park to achieve objective functions. The validity
and performance of the proposed algorithm is demonstrated through simulations
using IEEE-39 network.
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology
Considering Renewable Energies. Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES). 2017;94:287-299. doi:10.1016/j.ijepes.2017.07.007
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration
Methodology Considering Renewable Energies. Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), 94, 287–299. https://doi.org/10.1016/j.ijepes.2017.07.007
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration
Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007},
journal={Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017},
pages={287–299} }'
chicago: 'Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System
Restoration Methodology Considering Renewable Energies.” Elsevier International
Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017): 287–99.
https://doi.org/10.1016/j.ijepes.2017.07.007.'
ieee: C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration
Methodology Considering Renewable Energies,” Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017.
mla: Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering
Renewable Energies.” Elsevier International Journal of Electrical Power and
Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.
short: C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES) 94 (2017) 287–299.
date_created: 2019-05-22T13:14:20Z
date_updated: 2019-10-06T21:56:18Z
department:
- _id: '78'
doi: 10.1016/j.ijepes.2017.07.007
intvolume: ' 94'
keyword:
- Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations
language:
- iso: eng
page: 287-299
publication: Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)
publication_status: published
status: public
title: Three-Stage Power System Restoration Methodology Considering Renewable Energies
type: journal_article
user_id: '3118'
volume: 94
year: '2017'
...
---
_id: '65'
abstract:
- lang: eng
text: Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators
have strongly gained interested in the last years. Applications differ in their
execution characteristics and can therefore benefit from such heterogeneous resources
in terms of performance or energy consumption. While performance optimization
has been the only goal for a long time, nowadays research is more and more focusing
on techniques to minimize energy consumption due to rising electricity costs.This
paper presents reMinMin, a novel static list scheduling approach for optimizing
the total energy consumption for a set of tasks executed on a heterogeneous compute
node. reMinMin bases on a new energy model that differentiates between static
and dynamic energy components and covers effects of accelerator tasks on the host
CPU. The required energy values are retrieved by measurements on the real computing
system. In order to evaluate reMinMin, we compare it with two reference implementations
on three task sets with different degrees of heterogeneity. In our experiments,
MinMin is consistently better than a scheduler optimizing for dynamic energy only,
which requires up to 19.43% more energy, and very close to optimal schedules.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE
International Conference on Application-Specific Systems, Architectures and Processors
(ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272'
apa: 'Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements. In Proceedings of the
28th Annual IEEE International Conference on Application-specific Systems, Architectures
and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272'
bibtex: '@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272},
booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner,
Marco}, year={2017} }'
chicago: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” In Proceedings of the
28th Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.'
ieee: 'A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE
International Conference on Application-specific Systems, Architectures and Processors
(ASAP), 2017.'
mla: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th
Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.'
short: 'A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International
Conference on Application-Specific Systems, Architectures and Processors (ASAP),
2017.'
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:08Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ASAP.2017.7995272
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:37:55Z
date_updated: 2018-11-14T09:37:55Z
file_id: '5550'
file_name: loesch_asap2017.pdf
file_size: 467545
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:37:55Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)
status: public
title: 'reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on
Real Measurements'
type: conference
user_id: '477'
year: '2017'
...
---
_id: '68'
abstract:
- lang: eng
text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically
reconfigurable hardware systems. The producer of a hardware module spends huge
effort when creating a proof for a safety policy. The proof is then transferred
as a certificate together with the configuration bitstream to the consumer of
the hardware module, who can quickly verify the given proof. Previous work utilized
SAT solvers and resolution traces to set up a PCH technology and corresponding
tool flows. In this article, we present a novel technology for PCH based on inductive
invariants. For sequential circuits, our approach is fundamentally stronger than
the previous SAT-based one since we avoid the limitations of bounded unrolling.
We contrast our technology to existing ones and show that it fits into previously
proposed tool flows. We conduct experiments with four categories of benchmark
circuits and report consumer and producer runtime and peak memory consumption,
as well as the size of the certificates and the distribution of the workload between
producer and consumer. Experiments clearly show that our new induction-based technology
is superior for sequential circuits, whereas the previous SAT-based technology
is the better choice for combinational circuits.
author:
- first_name: Tobias
full_name: Isenberg, Tobias
last_name: Isenberg
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via
Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems.
2017;(4):61:1--61:23. doi:10.1145/3054743
apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying
Hardware via Inductive Invariants. ACM Transactions on Design Automation of
Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743
bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying
Hardware via Inductive Invariants}, DOI={10.1145/3054743},
number={4}, journal={ACM Transactions on Design Automation of Electronic Systems},
publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike
and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }'
chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema.
“Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design
Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.'
ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware
via Inductive Invariants,” ACM Transactions on Design Automation of Electronic
Systems, no. 4, pp. 61:1--61:23, 2017.
mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”
ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM,
2017, pp. 61:1--61:23, doi:10.1145/3054743.
short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design
Automation of Electronic Systems (2017) 61:1--61:23.
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:20Z
ddc:
- '000'
department:
- _id: '77'
- _id: '78'
doi: 10.1145/3054743
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T16:08:17Z
date_updated: 2018-11-02T16:08:17Z
file_id: '5324'
file_name: a61-isenberg.pdf
file_size: 806356
relation: main_file
success: 1
file_date_updated: 2018-11-02T16:08:17Z
has_accepted_license: '1'
issue: '4'
language:
- iso: eng
page: 61:1--61:23
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: ACM Transactions on Design Automation of Electronic Systems
publisher: ACM
status: public
title: Proof-Carrying Hardware via Inductive Invariants
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10600'
author:
- first_name: Philip
full_name: H.W. Leong, Philip
last_name: H.W. Leong
- first_name: Hideharu
full_name: Amano, Hideharu
last_name: Amano
- first_name: Jason
full_name: Anderson, Jason
last_name: Anderson
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
- first_name: Jo\~{a}o
full_name: M.P. Cardoso, Jo\~{a}o
last_name: M.P. Cardoso
- first_name: Oliver
full_name: Diessel, Oliver
last_name: Diessel
- first_name: Guy
full_name: Gogniat, Guy
last_name: Gogniat
- first_name: Mike
full_name: Hutton, Mike
last_name: Hutton
- first_name: JunKyu
full_name: Lee, JunKyu
last_name: Lee
- first_name: Wayne
full_name: Luk, Wayne
last_name: Luk
- first_name: Patrick
full_name: Lysaght, Patrick
last_name: Lysaght
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Viktor
full_name: K. Prasanna, Viktor
last_name: K. Prasanna
- first_name: Tero
full_name: Rissa, Tero
last_name: Rissa
- first_name: Cristina
full_name: Silvano, Cristina
last_name: Silvano
- first_name: Hayden
full_name: So, Hayden
last_name: So
- first_name: Yu
full_name: Wang, Yu
last_name: Wang
citation:
ama: H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference
– Significant Papers. ACM Transactions on Reconfigurable Technology and Systems.
2017. doi:10.1145/2996468
apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel,
O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant
Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468
bibtex: '@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et
al._2017, title={The First 25 Years of the FPL Conference – Significant Papers},
DOI={10.1145/2996468}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip
and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o
and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk,
Wayne and et al.}, year={2017} }'
chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~{a}o
M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL
Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology
and Systems, 2017. https://doi.org/10.1145/2996468.
ieee: P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant
Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.
mla: H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant
Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017,
doi:10.1145/2996468.
short: P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel,
G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna,
T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology
and Systems (2017).
date_created: 2019-07-10T09:22:27Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1145/2996468
language:
- iso: eng
publication: ACM Transactions on Reconfigurable Technology and Systems
status: public
title: The First 25 Years of the FPL Conference – Significant Papers
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10601'
author:
- first_name: Ronald
full_name: F. DeMara, Ronald
last_name: F. DeMara
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Marco
full_name: Ottavi, Marco
last_name: Ottavi
citation:
ama: 'F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. 2017.
doi:10.1109/TETC.2016.2641599'
apa: 'F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599'
bibtex: '@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599},
journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco},
year={2017} }'
chicago: 'F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable
Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.
https://doi.org/10.1109/TETC.2016.2641599.'
ieee: 'R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.'
mla: 'F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics:
From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers
and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.'
short: R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and
IEEE Transactions on Emerging Topics in Computing (2017).
date_created: 2019-07-10T09:22:28Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TETC.2016.2641599
language:
- iso: eng
publication: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing
status: public
title: 'Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures
(guest editorial)'
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10611'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172.
doi:10.1016/j.micpro.2017.06.002
apa: Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus. Microprocessors and Microsystems,
160–172. https://doi.org/10.1016/j.micpro.2017.06.002
bibtex: '@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002},
journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer,
Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.
ieee: J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus,” Microprocessors and Microsystems, pp.
160–172, 2017.
mla: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.
short: J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.
date_created: 2019-07-10T09:23:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1016/j.micpro.2017.06.002
language:
- iso: eng
page: 160-172
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: Evaluating fault-tolerance of redundant FPGA structures using Boolean difference
calculus
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10613'
author:
- first_name: Christian
full_name: Kaltschmidt, Christian
last_name: Kaltschmidt
citation:
ama: Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University; 2017.
apa: Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University.
bibtex: '@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System
for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt,
Christian}, year={2017} }'
chicago: Kaltschmidt, Christian. An AR-Based Training and Assessment System for
Myoelectrical Prosthetic Control. Paderborn University, 2017.
ieee: C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
mla: Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
short: C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control, Paderborn University, 2017.
date_created: 2019-07-10T09:25:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: An AR-based Training and Assessment System for Myoelectrical Prosthetic Control
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '10630'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based
dynamically reconfigurable high density myoelectric prosthesis controller. In:
Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137'
apa: Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner,
M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137
bibtex: '@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller},
DOI={10.23919/DATE.2017.7927137},
booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander
and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner,
Marco}, year={2017} }'
chicago: Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens,
and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric
Prosthesis Controller.” In Design, Automation and Test in Europe (DATE),
2017. https://doi.org/10.23919/DATE.2017.7927137.
ieee: A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,”
in Design, Automation and Test in Europe (DATE), 2017.
mla: Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High
Density Myoelectric Prosthesis Controller.” Design, Automation and Test in
Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.
short: 'A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design,
Automation and Test in Europe (DATE), 2017.'
date_created: 2019-07-10T11:02:56Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927137
language:
- iso: eng
publication: Design, Automation and Test in Europe (DATE)
status: public
title: A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10666'
author:
- first_name: Umair
full_name: Riaz, Umair
last_name: Riaz
citation:
ama: Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University; 2017.
apa: Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University.
bibtex: '@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions
on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017}
}'
chicago: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
ieee: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University, 2017.
mla: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
short: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA,
Paderborn University, 2017.
date_created: 2019-07-10T11:15:10Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Acceleration of Industrial Analytics Functions on a Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2017'
...
---
_id: '10672'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Ishraq Ibne
full_name: Ashraf, Ishraq Ibne
last_name: Ashraf
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification
of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor.
In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096'
apa: 'Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE).
https://doi.org/10.23919/DATE.2017.7927096'
bibtex: '@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor}, DOI={10.23919/DATE.2017.7927096},
booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho,
Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017}
}'
chicago: 'Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate
Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for
the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe
Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.'
ieee: 'N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE),
2017.'
mla: 'Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses:
A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design,
Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.'
short: 'N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation
and Test in Europe Conf. (DATE), 2017.'
date_created: 2019-07-10T11:17:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927096
language:
- iso: eng
publication: Proc. Design, Automation and Test in Europe Conf. (DATE)
status: public
title: 'Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis
System for the LEON3 Multi-core Processor'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...