---
_id: '65'
abstract:
- lang: eng
text: Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators
have strongly gained interested in the last years. Applications differ in their
execution characteristics and can therefore benefit from such heterogeneous resources
in terms of performance or energy consumption. While performance optimization
has been the only goal for a long time, nowadays research is more and more focusing
on techniques to minimize energy consumption due to rising electricity costs.This
paper presents reMinMin, a novel static list scheduling approach for optimizing
the total energy consumption for a set of tasks executed on a heterogeneous compute
node. reMinMin bases on a new energy model that differentiates between static
and dynamic energy components and covers effects of accelerator tasks on the host
CPU. The required energy values are retrieved by measurements on the real computing
system. In order to evaluate reMinMin, we compare it with two reference implementations
on three task sets with different degrees of heterogeneity. In our experiments,
MinMin is consistently better than a scheduler optimizing for dynamic energy only,
which requires up to 19.43% more energy, and very close to optimal schedules.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE
International Conference on Application-Specific Systems, Architectures and Processors
(ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272'
apa: 'Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements. In Proceedings of the
28th Annual IEEE International Conference on Application-specific Systems, Architectures
and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272'
bibtex: '@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272},
booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner,
Marco}, year={2017} }'
chicago: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” In Proceedings of the
28th Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.'
ieee: 'A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE
International Conference on Application-specific Systems, Architectures and Processors
(ASAP), 2017.'
mla: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th
Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.'
short: 'A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International
Conference on Application-Specific Systems, Architectures and Processors (ASAP),
2017.'
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:08Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ASAP.2017.7995272
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:37:55Z
date_updated: 2018-11-14T09:37:55Z
file_id: '5550'
file_name: loesch_asap2017.pdf
file_size: 467545
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:37:55Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)
status: public
title: 'reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on
Real Measurements'
type: conference
user_id: '477'
year: '2017'
...
---
_id: '68'
abstract:
- lang: eng
text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically
reconfigurable hardware systems. The producer of a hardware module spends huge
effort when creating a proof for a safety policy. The proof is then transferred
as a certificate together with the configuration bitstream to the consumer of
the hardware module, who can quickly verify the given proof. Previous work utilized
SAT solvers and resolution traces to set up a PCH technology and corresponding
tool flows. In this article, we present a novel technology for PCH based on inductive
invariants. For sequential circuits, our approach is fundamentally stronger than
the previous SAT-based one since we avoid the limitations of bounded unrolling.
We contrast our technology to existing ones and show that it fits into previously
proposed tool flows. We conduct experiments with four categories of benchmark
circuits and report consumer and producer runtime and peak memory consumption,
as well as the size of the certificates and the distribution of the workload between
producer and consumer. Experiments clearly show that our new induction-based technology
is superior for sequential circuits, whereas the previous SAT-based technology
is the better choice for combinational circuits.
author:
- first_name: Tobias
full_name: Isenberg, Tobias
last_name: Isenberg
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via
Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems.
2017;(4):61:1--61:23. doi:10.1145/3054743
apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying
Hardware via Inductive Invariants. ACM Transactions on Design Automation of
Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743
bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying
Hardware via Inductive Invariants}, DOI={10.1145/3054743},
number={4}, journal={ACM Transactions on Design Automation of Electronic Systems},
publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike
and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }'
chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema.
“Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design
Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.'
ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware
via Inductive Invariants,” ACM Transactions on Design Automation of Electronic
Systems, no. 4, pp. 61:1--61:23, 2017.
mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”
ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM,
2017, pp. 61:1--61:23, doi:10.1145/3054743.
short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design
Automation of Electronic Systems (2017) 61:1--61:23.
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:20Z
ddc:
- '000'
department:
- _id: '77'
- _id: '78'
doi: 10.1145/3054743
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T16:08:17Z
date_updated: 2018-11-02T16:08:17Z
file_id: '5324'
file_name: a61-isenberg.pdf
file_size: 806356
relation: main_file
success: 1
file_date_updated: 2018-11-02T16:08:17Z
has_accepted_license: '1'
issue: '4'
language:
- iso: eng
page: 61:1--61:23
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: ACM Transactions on Design Automation of Electronic Systems
publisher: ACM
status: public
title: Proof-Carrying Hardware via Inductive Invariants
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10600'
author:
- first_name: Philip
full_name: H.W. Leong, Philip
last_name: H.W. Leong
- first_name: Hideharu
full_name: Amano, Hideharu
last_name: Amano
- first_name: Jason
full_name: Anderson, Jason
last_name: Anderson
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
- first_name: Jo\~{a}o
full_name: M.P. Cardoso, Jo\~{a}o
last_name: M.P. Cardoso
- first_name: Oliver
full_name: Diessel, Oliver
last_name: Diessel
- first_name: Guy
full_name: Gogniat, Guy
last_name: Gogniat
- first_name: Mike
full_name: Hutton, Mike
last_name: Hutton
- first_name: JunKyu
full_name: Lee, JunKyu
last_name: Lee
- first_name: Wayne
full_name: Luk, Wayne
last_name: Luk
- first_name: Patrick
full_name: Lysaght, Patrick
last_name: Lysaght
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Viktor
full_name: K. Prasanna, Viktor
last_name: K. Prasanna
- first_name: Tero
full_name: Rissa, Tero
last_name: Rissa
- first_name: Cristina
full_name: Silvano, Cristina
last_name: Silvano
- first_name: Hayden
full_name: So, Hayden
last_name: So
- first_name: Yu
full_name: Wang, Yu
last_name: Wang
citation:
ama: H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference
– Significant Papers. ACM Transactions on Reconfigurable Technology and Systems.
2017. doi:10.1145/2996468
apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel,
O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant
Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468
bibtex: '@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et
al._2017, title={The First 25 Years of the FPL Conference – Significant Papers},
DOI={10.1145/2996468}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip
and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o
and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk,
Wayne and et al.}, year={2017} }'
chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~{a}o
M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL
Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology
and Systems, 2017. https://doi.org/10.1145/2996468.
ieee: P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant
Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.
mla: H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant
Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017,
doi:10.1145/2996468.
short: P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel,
G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna,
T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology
and Systems (2017).
date_created: 2019-07-10T09:22:27Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1145/2996468
language:
- iso: eng
publication: ACM Transactions on Reconfigurable Technology and Systems
status: public
title: The First 25 Years of the FPL Conference – Significant Papers
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10601'
author:
- first_name: Ronald
full_name: F. DeMara, Ronald
last_name: F. DeMara
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Marco
full_name: Ottavi, Marco
last_name: Ottavi
citation:
ama: 'F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. 2017.
doi:10.1109/TETC.2016.2641599'
apa: 'F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599'
bibtex: '@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599},
journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco},
year={2017} }'
chicago: 'F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable
Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.
https://doi.org/10.1109/TETC.2016.2641599.'
ieee: 'R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.'
mla: 'F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics:
From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers
and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.'
short: R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and
IEEE Transactions on Emerging Topics in Computing (2017).
date_created: 2019-07-10T09:22:28Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TETC.2016.2641599
language:
- iso: eng
publication: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing
status: public
title: 'Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures
(guest editorial)'
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10611'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172.
doi:10.1016/j.micpro.2017.06.002
apa: Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus. Microprocessors and Microsystems,
160–172. https://doi.org/10.1016/j.micpro.2017.06.002
bibtex: '@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002},
journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer,
Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.
ieee: J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus,” Microprocessors and Microsystems, pp.
160–172, 2017.
mla: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.
short: J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.
date_created: 2019-07-10T09:23:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1016/j.micpro.2017.06.002
language:
- iso: eng
page: 160-172
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: Evaluating fault-tolerance of redundant FPGA structures using Boolean difference
calculus
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10613'
author:
- first_name: Christian
full_name: Kaltschmidt, Christian
last_name: Kaltschmidt
citation:
ama: Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University; 2017.
apa: Kaltschmidt, C. (2017). An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University.
bibtex: '@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System
for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt,
Christian}, year={2017} }'
chicago: Kaltschmidt, Christian. An AR-Based Training and Assessment System for
Myoelectrical Prosthetic Control. Paderborn University, 2017.
ieee: C. Kaltschmidt, An AR-based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
mla: Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control. Paderborn University, 2017.
short: C. Kaltschmidt, An AR-Based Training and Assessment System for Myoelectrical
Prosthetic Control, Paderborn University, 2017.
date_created: 2019-07-10T09:25:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: An AR-based Training and Assessment System for Myoelectrical Prosthetic Control
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '10630'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based
dynamically reconfigurable high density myoelectric prosthesis controller. In:
Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137'
apa: Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner,
M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137
bibtex: '@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller},
DOI={10.23919/DATE.2017.7927137},
booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander
and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner,
Marco}, year={2017} }'
chicago: Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens,
and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric
Prosthesis Controller.” In Design, Automation and Test in Europe (DATE),
2017. https://doi.org/10.23919/DATE.2017.7927137.
ieee: A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,”
in Design, Automation and Test in Europe (DATE), 2017.
mla: Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High
Density Myoelectric Prosthesis Controller.” Design, Automation and Test in
Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.
short: 'A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design,
Automation and Test in Europe (DATE), 2017.'
date_created: 2019-07-10T11:02:56Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927137
language:
- iso: eng
publication: Design, Automation and Test in Europe (DATE)
status: public
title: A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10666'
author:
- first_name: Umair
full_name: Riaz, Umair
last_name: Riaz
citation:
ama: Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University; 2017.
apa: Riaz, U. (2017). Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University.
bibtex: '@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions
on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017}
}'
chicago: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
ieee: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA.
Paderborn University, 2017.
mla: Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform
FPGA. Paderborn University, 2017.
short: U. Riaz, Acceleration of Industrial Analytics Functions on a Platform FPGA,
Paderborn University, 2017.
date_created: 2019-07-10T11:15:10Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Acceleration of Industrial Analytics Functions on a Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2017'
...
---
_id: '10672'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Ishraq Ibne
full_name: Ashraf, Ishraq Ibne
last_name: Ashraf
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification
of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor.
In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096'
apa: 'Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE).
https://doi.org/10.23919/DATE.2017.7927096'
bibtex: '@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor}, DOI={10.23919/DATE.2017.7927096},
booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho,
Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017}
}'
chicago: 'Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate
Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for
the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe
Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.'
ieee: 'N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE),
2017.'
mla: 'Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses:
A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design,
Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.'
short: 'N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation
and Test in Europe Conf. (DATE), 2017.'
date_created: 2019-07-10T11:17:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927096
language:
- iso: eng
publication: Proc. Design, Automation and Test in Europe Conf. (DATE)
status: public
title: 'Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis
System for the LEON3 Multi-core Processor'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10692'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology
Considering Renewable Energies. Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES). 2017.
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration
Methodology Considering Renewable Energies. Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES).
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration
Methodology Considering Renewable Energies}, journal={Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann,
Paul and Braun, Martin}, year={2017} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System
Restoration Methodology Considering Renewable Energies.” Elsevier International
Journal of Electrical Power and Energy Systems (IJEPES), 2017.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration
Methodology Considering Renewable Energies,” Elsevier International Journal
of Electrical Power and Energy Systems (IJEPES), 2017.
mla: Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering
Renewable Energies.” Elsevier International Journal of Electrical Power and
Energy Systems (IJEPES), 2017.
short: C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical
Power and Energy Systems (IJEPES) (2017).
date_created: 2019-07-10T11:29:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
publication: Elsevier International Journal of Electrical Power and Energy Systems
(IJEPES)
status: public
title: Three-Stage Power System Restoration Methodology Considering Renewable Energies
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10708'
author:
- first_name: Andreas
full_name: Dietrich, Andreas
last_name: Dietrich
citation:
ama: Dietrich A. Reconfigurable Cryptographic Services. Paderborn University;
2017.
apa: Dietrich, A. (2017). Reconfigurable Cryptographic Services. Paderborn
University.
bibtex: '@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn
University}, author={Dietrich, Andreas}, year={2017} }'
chicago: Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn
University, 2017.
ieee: A. Dietrich, Reconfigurable Cryptographic Services. Paderborn University,
2017.
mla: Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn
University, 2017.
short: A. Dietrich, Reconfigurable Cryptographic Services, Paderborn University,
2017.
date_created: 2019-07-10T11:43:32Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Reconfigurable Cryptographic Services
type: mastersthesis
user_id: '3118'
year: '2017'
...
---
_id: '10740'
author:
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Martin
full_name: Braun, Martin
last_name: Braun
citation:
ama: Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel
Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032
apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Fast Network Restoration by
Partitioning of Parallel Black Start Zones. The Journal of Engineering,
19pp. https://doi.org/10.1049/joe.2017.0032
bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning
of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032},
journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and
Braun, Martin}, year={2017}, pages={19pp} }'
chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Fast Network Restoration
by Partitioning of Parallel Black Start Zones.” The Journal of Engineering,
2017, 19pp. https://doi.org/10.1049/joe.2017.0032.
ieee: C. Shen, P. Kaufmann, and M. Braun, “Fast Network Restoration by Partitioning
of Parallel Black Start Zones,” The Journal of Engineering, p. 19pp, 2017.
mla: Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black
Start Zones.” The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032.
short: C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017) 19pp.
date_created: 2019-07-10T11:59:38Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1049/joe.2017.0032
page: 19pp
publication: The Journal of Engineering
status: public
title: Fast Network Restoration by Partitioning of Parallel Black Start Zones
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10759'
author:
- first_name: Giovanni
full_name: Squillero, Giovanni
last_name: Squillero
- first_name: Paolo
full_name: Burelli, Paolo
last_name: Burelli
- first_name: Antonio
full_name: M. Mora, Antonio
last_name: M. Mora
- first_name: Alexandros
full_name: Agapitos, Alexandros
last_name: Agapitos
- first_name: William
full_name: S. Bush, William
last_name: S. Bush
- first_name: Stefano
full_name: Cagnoni, Stefano
last_name: Cagnoni
- first_name: Carlos
full_name: Cotta, Carlos
last_name: Cotta
- first_name: Ivanoe
full_name: De Falco, Ivanoe
last_name: De Falco
- first_name: Antonio
full_name: Della Cioppa, Antonio
last_name: Della Cioppa
- first_name: Federico
full_name: Divina, Federico
last_name: Divina
- first_name: A.E.
full_name: Eiben, A.E.
last_name: Eiben
- first_name: Anna
full_name: I. Esparcia-Alc{\'a}zar, Anna
last_name: I. Esparcia-Alc{\'a}zar
- first_name: Francisco
full_name: Fern{\'a}ndez de Vega, Francisco
last_name: Fern{\'a}ndez de Vega
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Evert
full_name: Haasdijk, Evert
last_name: Haasdijk
- first_name: J.
full_name: Ignacio Hidalgo, J.
last_name: Ignacio Hidalgo
- first_name: Michael
full_name: Kampouridis, Michael
last_name: Kampouridis
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Michalis
full_name: Mavrovouniotis, Michalis
last_name: Mavrovouniotis
- first_name: Trung
full_name: Thanh Nguyen, Trung
last_name: Thanh Nguyen
- first_name: Robert
full_name: Schaefer, Robert
last_name: Schaefer
- first_name: Kevin
full_name: Sim, Kevin
last_name: Sim
- first_name: Ernesto
full_name: Tarantino, Ernesto
last_name: Tarantino
- first_name: Neil
full_name: Urquhart, Neil
last_name: Urquhart
- first_name: Mengjie
full_name: Zhang (editors), Mengjie
last_name: Zhang (editors)
citation:
ama: Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation
- 20th European Conference, EvoApplications. Springer; 2017.
apa: Squillero, G., Burelli, P., M. Mora, A., Agapitos, A., S. Bush, W., Cagnoni,
S., … Zhang (editors), M. (2017). Applications of Evolutionary Computation
- 20th European Conference, EvoApplications. Springer.
bibtex: '@book{Squillero_Burelli_M. Mora_Agapitos_S. Bush_Cagnoni_Cotta_De Falco_Della
Cioppa_Divina_et al._2017, series={Lecture Notes in Computer Science}, title={Applications
of Evolutionary Computation - 20th European Conference, EvoApplications}, publisher={Springer},
author={Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos,
Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De
Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2017},
collection={Lecture Notes in Computer Science} }'
chicago: Squillero, Giovanni, Paolo Burelli, Antonio M. Mora, Alexandros Agapitos,
William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary
Computation - 20th European Conference, EvoApplications. Lecture Notes in
Computer Science. Springer, 2017.
ieee: G. Squillero et al., Applications of Evolutionary Computation -
20th European Conference, EvoApplications. Springer, 2017.
mla: Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th
European Conference, EvoApplications. Springer, 2017.
short: G. Squillero, P. Burelli, A. M. Mora, A. Agapitos, W. S. Bush, S. Cagnoni,
C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\’a}zar,
F. Fern{\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis,
P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino,
N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 20th
European Conference, EvoApplications, Springer, 2017.
date_created: 2019-07-10T12:06:37Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 20th European Conference, EvoApplications
type: book
user_id: '3118'
year: '2017'
...
---
_id: '10760'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Roman
full_name: Kalkreuth, Roman
last_name: Kalkreuth
citation:
ama: 'Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical
Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German
Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26'
apa: 'Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic
Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26'
bibtex: '@inproceedings{Kaufmann_Kalkreuth_2017, title={Parametrizing Cartesian
Genetic Programming: An Empirical Study}, DOI={10.1007/978-3-319-67190-1_26},
booktitle={KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference
on AI}, publisher={Springer International Publishing}, author={Kaufmann, Paul
and Kalkreuth, Roman}, year={2017} }'
chicago: 'Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic
Programming: An Empirical Study.” In KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI. Springer International Publishing, 2017.
https://doi.org/10.1007/978-3-319-67190-1_26.'
ieee: 'P. Kaufmann and R. Kalkreuth, “Parametrizing Cartesian Genetic Programming:
An Empirical Study,” in KI 2017: Advances in Artificial Intelligence: 40th
Annual German Conference on AI, 2017.'
mla: 'Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming:
An Empirical Study.” KI 2017: Advances in Artificial Intelligence: 40th Annual
German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.'
short: 'P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence:
40th Annual German Conference on AI, Springer International Publishing, 2017.'
date_created: 2019-07-10T12:06:38Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1007/978-3-319-67190-1_26
language:
- iso: eng
publication: 'KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference
on AI'
publisher: Springer International Publishing
status: public
title: 'Parametrizing Cartesian Genetic Programming: An Empirical Study'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10761'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic
Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive
Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380'
apa: 'Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for
Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380'
bibtex: '@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology
for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches}, DOI={10.1109/AHS.2017.8046380},
booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann,
Paul and Ho, Nam and Platzner, Marco}, year={2017} }'
chicago: 'Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for
Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches.” In Adaptive Hardware and Systems (AHS). IEEE, 2017. https://doi.org/10.1109/AHS.2017.8046380.'
ieee: 'P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex
Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,”
in Adaptive Hardware and Systems (AHS), 2017.'
mla: 'Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic
Functions: A Case Study in Metaheuristic Optimization of Caches.” Adaptive
Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.'
short: 'P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS),
IEEE, 2017.'
date_created: 2019-07-10T12:07:01Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/AHS.2017.8046380
language:
- iso: eng
publication: Adaptive Hardware and Systems (AHS)
publisher: IEEE
status: public
title: 'Evaluation Methodology for Complex Non-deterministic Functions: A Case Study
in Metaheuristic Optimization of Caches'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10762'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Roman
full_name: Kalkreuth, Roman
last_name: Kalkreuth
citation:
ama: 'Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian
Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium.
ACM; 2017. doi:10.1145/3067695.3075980'
apa: Kaufmann, P., & Kalkreuth, R. (2017). An Empirical Study on the Parametrization
of Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO),
Compendium. ACM. https://doi.org/10.1145/3067695.3075980
bibtex: '@inproceedings{Kaufmann_Kalkreuth_2017, title={An Empirical Study on the
Parametrization of Cartesian Genetic Programming}, DOI={10.1145/3067695.3075980},
booktitle={Genetic and Evolutionary Computation (GECCO), Compendium}, publisher={ACM},
author={Kaufmann, Paul and Kalkreuth, Roman}, year={2017} }'
chicago: Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization
of Cartesian Genetic Programming.” In Genetic and Evolutionary Computation
(GECCO), Compendium. ACM, 2017. https://doi.org/10.1145/3067695.3075980.
ieee: P. Kaufmann and R. Kalkreuth, “An Empirical Study on the Parametrization of
Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO),
Compendium, 2017.
mla: Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization
of Cartesian Genetic Programming.” Genetic and Evolutionary Computation (GECCO),
Compendium, ACM, 2017, doi:10.1145/3067695.3075980.
short: 'P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO),
Compendium, ACM, 2017.'
date_created: 2019-07-10T12:07:03Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1145/3067695.3075980
publication: Genetic and Evolutionary Computation (GECCO), Compendium
publisher: ACM
status: public
title: An Empirical Study on the Parametrization of Cartesian Genetic Programming
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10780'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Philipp
full_name: Hübner, Philipp
last_name: Hübner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
as design approach for visual sensor nodes. In: 12th International Symposium
on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8.
doi:10.1109/ReCoSoC.2017.8016147'
apa: Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational
self-awareness as design approach for visual sensor nodes. In 12th International
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
(pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147
bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147},
booktitle={12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
“Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
(ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.
ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
as design approach for visual sensor nodes,” in 12th International Symposium
on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp.
1–8.
mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric
Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.
short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '14893'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh Ben
full_name: Abdallah, Riadh Ben
last_name: Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology
for Reconfigurable Embedded Systems. In: Communications in Computer and Information
Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8'
apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign:
A Codesign Methodology for Reconfigurable Embedded Systems. In Communications
in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8'
bibtex: '@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign:
A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={10.1007/978-3-319-62569-0_8},
booktitle={Communications in Computer and Information Science}, publisher={Springer
}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner,
Marco}, year={2017} }'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner.
“I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In Communications
in Computer and Information Science. Cham: Springer , 2017. https://doi.org/10.1007/978-3-319-62569-0_8.'
ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign
Methodology for Reconfigurable Embedded Systems,” in Communications in Computer
and Information Science, 2017.'
mla: 'Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable
Embedded Systems.” Communications in Computer and Information Science,
Springer , 2017, doi:10.1007/978-3-319-62569-0_8.'
short: 'I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in
Computer and Information Science, Springer , Cham, 2017.'
date_created: 2019-11-12T08:33:13Z
date_updated: 2022-01-06T06:52:10Z
department:
- _id: '78'
doi: 10.1007/978-3-319-62569-0_8
language:
- iso: eng
place: Cham
publication: Communications in Computer and Information Science
publication_identifier:
isbn:
- '9783319625683'
- '9783319625690'
issn:
- 1865-0929
- 1865-0937
publication_status: published
publisher: 'Springer '
status: public
title: 'I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '222'
abstract:
- lang: eng
text: Virtual field programmable gate arrays (FPGA) are overlay architectures realized
on top of physical FPGAs. They are proposed to enhance or abstract away from the
physical FPGA for experimenting with novel architectures and design tool flows.
In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into
a complete configurable system-on-chip. Such an embedding is required to fully
harness the potential of virtual FPGAs, in particular to give the virtual circuits
access to main memory and operating system services, and to enable a concurrent
operation of virtualized and non-virtualized circuitry. We discuss our extension
to ZUMA and its embedding into the ReconOS operating system for hardware/software
systems. Furthermore, we present an open source tool flow to synthesize configurations
for the virtual FPGA, along with an analysis of the area and delay overheads involved.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for
Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers &
Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005
apa: Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and
Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.
Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005
bibtex: '@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design
Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip},
DOI={10.1016/j.compeleceng.2016.04.005},
journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema,
Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122}
}'
chicago: Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and
Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.”
Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005.
ieee: T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool
Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers
& Electrical Engineering, pp. 112--122, 2016.
mla: Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding
a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical
Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.
short: T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering
(2016) 112--122.
date_created: 2017-10-17T12:41:35Z
date_updated: 2022-01-06T06:55:29Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1016/j.compeleceng.2016.04.005
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:36:08Z
date_updated: 2018-03-21T10:36:08Z
file_id: '1511'
file_name: 222-1-s2.0-S0045790616300684-main.pdf
file_size: 931048
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:36:08Z
has_accepted_license: '1'
language:
- iso: eng
page: 112--122
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Computers & Electrical Engineering
publisher: Elsevier
status: public
title: An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable
System-on-Chip
type: journal_article
user_id: '477'
year: '2016'
...