---
_id: '10624'
abstract:
- lang: eng
text: "The use of heterogeneous computing resources, such as graphics processing
units or other specialized co-processors, has become widespread in recent years
because of their performance and energy efficiency advantages. Operating system
approaches that are limited to optimizing CPU usage are no longer sufficient for
the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling
task preemption on these architectures and migration of tasks between different
resource types at run-time is not only key to improving the performance and energy
consumption but also to enabling automatic scheduling methods for heterogeneous
compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management
of heterogeneous resources and enabling tasks to migrate between diverse hardware.
It provides fundamental work towards future operating systems by discussing implications,
limitations, and chances of the heterogeneity and introducing solutions for energy-
and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous
systems by the use of a centralized scheduler are presented that show benefits
over existing approaches in varying case studies."
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
citation:
ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing. Berlin: Logos Verlag Berlin GmbH; 2015.'
apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of
Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag
Berlin GmbH}, author={Beisel, Tobias}, year={2015} }'
chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Logos Verlag Berlin GmbH, 2015.
short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing, Logos Verlag Berlin GmbH, Berlin, 2015.
date_created: 2019-07-10T09:36:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
- _id: '27'
- _id: '518'
language:
- iso: eng
page: '183'
place: Berlin
project:
- _id: '30'
grant_number: 01|H11004
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication_identifier:
isbn:
- 978-3-8325-4155-2
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing
type: dissertation
user_id: '3118'
year: '2015'
...
---
_id: '10668'
author:
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
citation:
ama: Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University; 2015.
apa: Hangmann, H. (2015). Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University.
bibtex: '@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for
FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015}
}'
chicago: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA
Devices. Paderborn University, 2015.
ieee: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University, 2015.
mla: Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices.
Paderborn University, 2015.
short: H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices, Paderborn
University, 2015.
date_created: 2019-07-10T11:15:13Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Evolution of Heat Flow Prediction Models for FPGA Devices
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10671'
author:
- first_name: Christian
full_name: Haupt, Christian
last_name: Haupt
citation:
ama: Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen.
Paderborn University; 2015.
apa: Haupt, C. (2015). Computer Vision basierte Klassifikation von HD EMG Signalen.
Paderborn University.
bibtex: '@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD
EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015}
}'
chicago: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG
Signalen. Paderborn University, 2015.
ieee: C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen.
Paderborn University, 2015.
mla: Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen.
Paderborn University, 2015.
short: C. Haupt, Computer Vision Basierte Klassifikation von HD EMG Signalen, Paderborn
University, 2015.
date_created: 2019-07-10T11:17:57Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: Computer Vision basierte Klassifikation von HD EMG Signalen
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10693'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Cong
full_name: Shen, Cong
last_name: Shen
citation:
ama: 'Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network
Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and
Evolutionary Computation (GECCO). ACM; 2015:409-416.'
apa: Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization
for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic
and Evolutionary Computation (GECCO) (pp. 409–416). ACM.
bibtex: '@inproceedings{Kaufmann_Shen_2015, title={Generator Start-up Sequences
Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing},
booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM}, author={Kaufmann,
Paul and Shen, Cong}, year={2015}, pages={409–416} }'
chicago: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization
for Network Restoration Using Genetic Algorithm and Simulated Annealing.” In Genetic
and Evolutionary Computation (GECCO), 409–16. ACM, 2015.
ieee: P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network
Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and
Evolutionary Computation (GECCO), 2015, pp. 409–416.
mla: Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for
Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic
and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.
short: 'P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO),
ACM, 2015, pp. 409–416.'
date_created: 2019-07-10T11:30:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
page: 409-416
publication: Genetic and Evolutionary Computation (GECCO)
publisher: ACM
status: public
title: Generator Start-up Sequences Optimization for Network Restoration Using Genetic
Algorithm and Simulated Annealing
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10711'
author:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Meisner S, Platzner M. Comparison of thread signatures for error detection
in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International
Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153'
apa: Meisner, S., & Platzner, M. (2015). Comparison of thread signatures for
error detection in hybrid multi-cores. In Field Programmable Technology (FPT),
2015 International Conference on (pp. 212–215). https://doi.org/10.1109/FPT.2015.7393153
bibtex: '@inproceedings{Meisner_Platzner_2015, series={FPT}, title={Comparison of
thread signatures for error detection in hybrid multi-cores}, DOI={10.1109/FPT.2015.7393153},
booktitle={Field Programmable Technology (FPT), 2015 International Conference
on}, author={Meisner, Sebastian and Platzner, Marco}, year={2015}, pages={212–215},
collection={FPT} }'
chicago: Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures
for Error Detection in Hybrid Multi-Cores.” In Field Programmable Technology
(FPT), 2015 International Conference On, 212–15. FPT, 2015. https://doi.org/10.1109/FPT.2015.7393153.
ieee: S. Meisner and M. Platzner, “Comparison of thread signatures for error detection
in hybrid multi-cores,” in Field Programmable Technology (FPT), 2015 International
Conference on, 2015, pp. 212–215.
mla: Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for
Error Detection in Hybrid Multi-Cores.” Field Programmable Technology (FPT),
2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.
short: 'S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International
Conference On, 2015, pp. 212–215.'
date_created: 2019-07-10T11:47:24Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPT.2015.7393153
language:
- iso: eng
page: 212-215
publication: Field Programmable Technology (FPT), 2015 International Conference on
series_title: FPT
status: public
title: Comparison of thread signatures for error detection in hybrid multi-cores
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10714'
author:
- first_name: Roland
full_name: Meißner, Roland
last_name: Meißner
citation:
ama: Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung
Virtueller FPGAs. Universität Paderborn; 2015.
apa: Meißner, R. (2015). Konzept und Implementation einer Benutzeroberfläche
zur Generierung virtueller FPGAs. Universität Paderborn.
bibtex: '@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche
zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner,
Roland}, year={2015} }'
chicago: Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche
Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.
ieee: R. Meißner, Konzept und Implementation einer Benutzeroberfläche zur Generierung
virtueller FPGAs. Universität Paderborn, 2015.
mla: Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur
Generierung Virtueller FPGAs. Universität Paderborn, 2015.
short: R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung
Virtueller FPGAs, Universität Paderborn, 2015.
date_created: 2019-07-10T11:48:25Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller
FPGAs
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '10726'
author:
- first_name: Thorbjörn
full_name: Posewsky, Thorbjörn
last_name: Posewsky
citation:
ama: Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform.
Paderborn University; 2015.
apa: Posewsky, T. (2015). Acceleration of Artificial Neural Networks on a Zynq
Platform. Paderborn University.
bibtex: '@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks
on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn},
year={2015} }'
chicago: Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a
Zynq Platform. Paderborn University, 2015.
ieee: T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform.
Paderborn University, 2015.
mla: Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq
Platform. Paderborn University, 2015.
short: T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform,
Paderborn University, 2015.
date_created: 2019-07-10T11:54:44Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Acceleration of Artificial Neural Networks on a Zynq Platform
type: mastersthesis
user_id: '3118'
year: '2015'
...
---
_id: '10757'
author:
- first_name: Antonio
full_name: M. Mora, Antonio
last_name: M. Mora
- first_name: Giovanni
full_name: Squillero, Giovanni
last_name: Squillero
- first_name: Alexandros
full_name: Agapitos, Alexandros
last_name: Agapitos
- first_name: Paolo
full_name: Burelli, Paolo
last_name: Burelli
- first_name: William
full_name: S. Bush, William
last_name: S. Bush
- first_name: Stefano
full_name: Cagnoni, Stefano
last_name: Cagnoni
- first_name: Carlos
full_name: Cotta, Carlos
last_name: Cotta
- first_name: Ivanoe
full_name: De Falco, Ivanoe
last_name: De Falco
- first_name: Antonio
full_name: Della Cioppa, Antonio
last_name: Della Cioppa
- first_name: Federico
full_name: Divina, Federico
last_name: Divina
- first_name: A.E.
full_name: Eiben, A.E.
last_name: Eiben
- first_name: Anna
full_name: I. Esparcia-Alc{\'a}zar, Anna
last_name: I. Esparcia-Alc{\'a}zar
- first_name: Francisco
full_name: Fern{\'a}ndez de Vega, Francisco
last_name: Fern{\'a}ndez de Vega
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Evert
full_name: Haasdijk, Evert
last_name: Haasdijk
- first_name: J.
full_name: Ignacio Hidalgo, J.
last_name: Ignacio Hidalgo
- first_name: Michael
full_name: Kampouridis, Michael
last_name: Kampouridis
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Michalis
full_name: Mavrovouniotis, Michalis
last_name: Mavrovouniotis
- first_name: Trung
full_name: Thanh Nguyen, Trung
last_name: Thanh Nguyen
- first_name: Robert
full_name: Schaefer, Robert
last_name: Schaefer
- first_name: Kevin
full_name: Sim, Kevin
last_name: Sim
- first_name: Ernesto
full_name: Tarantino, Ernesto
last_name: Tarantino
- first_name: Neil
full_name: Urquhart, Neil
last_name: Urquhart
- first_name: Mengjie
full_name: Zhang (editors), Mengjie
last_name: Zhang (editors)
citation:
ama: 'M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary
Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen,
Denmark: Springer; 2015.'
apa: 'M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni,
S., … Zhang (editors), M. (2015). Applications of Evolutionary Computation
- 18th European Conference, EvoApplications (Vol. 9028). Copenhagen, Denmark:
Springer.'
bibtex: '@book{M. Mora_Squillero_Agapitos_Burelli_S. Bush_Cagnoni_Cotta_De Falco_Della
Cioppa_Divina_et al._2015, place={Copenhagen, Denmark}, series={Lecture Notes
in Computer Science}, title={Applications of Evolutionary Computation - 18th European
Conference, EvoApplications}, volume={9028}, publisher={Springer}, author={M.
Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo
and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe
and Della Cioppa, Antonio and Divina, Federico and et al.}, year={2015}, collection={Lecture
Notes in Computer Science} }'
chicago: 'M. Mora, Antonio, Giovanni Squillero, Alexandros Agapitos, Paolo Burelli,
William S. Bush, Stefano Cagnoni, Carlos Cotta, et al. Applications of Evolutionary
Computation - 18th European Conference, EvoApplications. Vol. 9028. Lecture
Notes in Computer Science. Copenhagen, Denmark: Springer, 2015.'
ieee: 'A. M. Mora et al., Applications of Evolutionary Computation - 18th
European Conference, EvoApplications, vol. 9028. Copenhagen, Denmark: Springer,
2015.'
mla: M. Mora, Antonio, et al. Applications of Evolutionary Computation - 18th
European Conference, EvoApplications. Vol. 9028, Springer, 2015.
short: A. M. Mora, G. Squillero, A. Agapitos, P. Burelli, W. S. Bush, S. Cagnoni,
C. Cotta, I. De Falco, A. Della Cioppa, F. Divina, A.E. Eiben, A. I. Esparcia-Alc{\’a}zar,
F. Fern{\’a}ndez de Vega, K. Glette, E. Haasdijk, J. Ignacio Hidalgo, M. Kampouridis,
P. Kaufmann, M. Mavrovouniotis, T. Thanh Nguyen, R. Schaefer, K. Sim, E. Tarantino,
N. Urquhart, M. Zhang (editors), Applications of Evolutionary Computation - 18th
European Conference, EvoApplications, Springer, Copenhagen, Denmark, 2015.
date_created: 2019-07-10T12:06:35Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
intvolume: ' 9028'
place: Copenhagen, Denmark
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 18th European Conference, EvoApplications
type: book
user_id: '3118'
volume: 9028
year: '2015'
...
---
_id: '10765'
author:
- first_name: Philip
full_name: H.W. Leong, Philip
last_name: H.W. Leong
- first_name: Hideharu
full_name: Amano, Hideharu
last_name: Amano
- first_name: Jason
full_name: Anderson, Jason
last_name: Anderson
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
- first_name: Jo\~ao
full_name: M.P. Cardoso, Jo\~ao
last_name: M.P. Cardoso
- first_name: Oliver
full_name: Diessel, Oliver
last_name: Diessel
- first_name: Guy
full_name: Gogniat, Guy
last_name: Gogniat
- first_name: Mike
full_name: Hutton, Mike
last_name: Hutton
- first_name: JunKyu
full_name: Lee, JunKyu
last_name: Lee
- first_name: Wayne
full_name: Luk, Wayne
last_name: Luk
- first_name: Patrick
full_name: Lysaght, Patrick
last_name: Lysaght
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Viktor
full_name: K. Prasanna, Viktor
last_name: K. Prasanna
- first_name: Tero
full_name: Rissa, Tero
last_name: Rissa
- first_name: Cristina
full_name: Silvano, Cristina
last_name: Silvano
- first_name: Hayden
full_name: So, Hayden
last_name: So
- first_name: Yu
full_name: Wang, Yu
last_name: Wang
citation:
ama: 'H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first
25 years of the FPL conference. In: Proceedings of the 25th International Conference
on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3.
doi:10.1109/FPL.2015.7293747'
apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel,
O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference.
In Proceedings of the 25th International Conference on Field Programmable Logic
and Applications (FPL) (pp. 1–3). Imperial College. https://doi.org/10.1109/FPL.2015.7293747
bibtex: '@inproceedings{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et
al._2015, title={Significant papers from the first 25 years of the FPL conference},
DOI={10.1109/FPL.2015.7293747},
booktitle={Proceedings of the 25th International Conference on Field Programmable
Logic and Applications (FPL)}, publisher={Imperial College}, author={H.W. Leong,
Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso,
Jo\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and
Luk, Wayne and et al.}, year={2015}, pages={1–3} }'
chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~ao
M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “Significant Papers from the
First 25 Years of the FPL Conference.” In Proceedings of the 25th International
Conference on Field Programmable Logic and Applications (FPL), 1–3. Imperial
College, 2015. https://doi.org/10.1109/FPL.2015.7293747.
ieee: P. H.W. Leong et al., “Significant papers from the first 25 years of
the FPL conference,” in Proceedings of the 25th International Conference on
Field Programmable Logic and Applications (FPL), 2015, pp. 1–3.
mla: H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the
FPL Conference.” Proceedings of the 25th International Conference on Field
Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3,
doi:10.1109/FPL.2015.7293747.
short: 'P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel,
G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna,
T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International
Conference on Field Programmable Logic and Applications (FPL), Imperial College,
2015, pp. 1–3.'
date_created: 2019-07-10T12:07:53Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293747
language:
- iso: eng
page: 1-3
publication: Proceedings of the 25th International Conference on Field Programmable
Logic and Applications (FPL)
publisher: Imperial College
status: public
title: Significant papers from the first 25 years of the FPL conference
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10767'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh
full_name: Ben Abdallah, Riadh
last_name: Ben Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for
Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.
In: Proceedings of the 29th European Simulation and Modelling Conference (ESM).
; 2015.'
apa: Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2015). New Codesign
Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded
Software. In Proceedings of the 29th European Simulation and Modelling Conference
(ESM).
bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2015, title={New Codesign
Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded
Software}, booktitle={Proceedings of the 29th European Simulation and Modelling
Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed
and Platzner, Marco}, year={2015} }'
chicago: Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner.
“New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable
Embedded Software.” In Proceedings of the 29th European Simulation and Modelling
Conference (ESM), 2015.
ieee: I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions
for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,”
in Proceedings of the 29th European Simulation and Modelling Conference (ESM),
2015.
mla: Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning
of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th
European Simulation and Modelling Conference (ESM), 2015.
short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of
the 29th European Simulation and Modelling Conference (ESM), 2015.'
date_created: 2019-07-10T12:07:55Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 29th European Simulation and Modelling Conference
(ESM)
status: public
title: New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable
Embedded Software
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10770'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis
to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE
Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015).
From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon
Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126.
https://doi.org/10.1109/TNANO.2015.2482359
bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From
Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon
Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359},
number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh
Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015},
pages={1117–1126} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni
De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity
Silicon Nanowires.” IEEE Transactions on Nanotechnology 14, no. 6 (2015):
1117–26. https://doi.org/10.1109/TNANO.2015.2482359.'
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect
Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,”
IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault
Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on
Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.
short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions
on Nanotechnology 14 (2015) 1117–1126.
date_created: 2019-07-10T12:08:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/TNANO.2015.2482359
extern: '1'
intvolume: ' 14'
issue: '6'
language:
- iso: eng
page: 1117-1126
publication: IEEE Transactions on Nanotechnology
publisher: IEEE
status: public
title: From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity
Silicon Nanowires
type: journal_article
user_id: '3118'
volume: 14
year: '2015'
...
---
_id: '10771'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Jian
full_name: Zhang, Jian
last_name: Zhang
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
- first_name: Eduardo
full_name: Sanchez, Eduardo
last_name: Sanchez
- first_name: Matteo Sonza
full_name: Reorda, Matteo Sonza
last_name: Reorda
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E,
Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE;
2015:491-496. doi:10.1109/ISVLSI.2015.13'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez,
E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry
adder with controllable-polarity transistors. In 2015 IEEE Computer Society
Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015,
title={On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors}, DOI={10.1109/ISVLSI.2015.13},
booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE},
author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang,
Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza},
year={2015}, pages={491–496} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang,
Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design
of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.”
In 2015 IEEE Computer Society Annual Symposium on VLSI, 491–96. IEEE, 2015.
https://doi.org/10.1109/ISVLSI.2015.13.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez,
and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015,
pp. 491–496.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry
Adder with Controllable-Polarity Transistors.” 2015 IEEE Computer Society Annual
Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E.
Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI,
IEEE, 2015, pp. 491–496.'
date_created: 2019-07-10T12:08:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ISVLSI.2015.13
extern: '1'
language:
- iso: eng
page: 491-496
publication: 2015 IEEE Computer Society Annual Symposium on VLSI
publisher: IEEE
status: public
title: On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10772'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable
polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation
& Test in Europe Conference \& Exhibition. EDA Consortium; 2015:453-458.
doi:10.7873/DATE.2015.0428'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015).
Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings
of the 2015 Design, Automation & Test in Europe Conference \& Exhibition
(pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault
modeling in controllable polarity silicon nanowire circuits}, DOI={10.7873/DATE.2015.0428},
booktitle={Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi,
Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015},
pages={453–458} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni
De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.”
In Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition, 453–58. EDA Consortium, 2015. https://doi.org/10.7873/DATE.2015.0428.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling
in controllable polarity silicon nanowire circuits,” in Proceedings of the
2015 Design, Automation & Test in Europe Conference \& Exhibition,
2015, pp. 453–458.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity
Silicon Nanowire Circuits.” Proceedings of the 2015 Design, Automation &
Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453–58,
doi:10.7873/DATE.2015.0428.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings
of the 2015 Design, Automation & Test in Europe Conference \& Exhibition,
EDA Consortium, 2015, pp. 453–458.'
date_created: 2019-07-10T12:08:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.7873/DATE.2015.0428
extern: '1'
language:
- iso: eng
page: 453-458
publication: Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition
publisher: EDA Consortium
status: public
title: Fault modeling in controllable polarity silicon nanowire circuits
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10779'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
scheduling and allocation. In: 25th International Conference on Field Programmable
Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994'
apa: Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time
hardware tasks scheduling and allocation. In 25th International Conference
on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994
bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994},
booktitle={25th International Conference on Field Programmable Logic and Applications
(FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
and Khouas, Abdelhakim}, year={2015} }'
chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International
Conference on Field Programmable Logic and Applications (FPL). Imperial College,
2015. https://doi.org/10.1109/FPL.2015.7293994.
ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
tasks scheduling and allocation,” in 25th International Conference on Field
Programmable Logic and Applications (FPL), 2015.
mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
and Allocation.” 25th International Conference on Field Programmable Logic
and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.
short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
(FPL)
publication_identifier:
issn:
- 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '13153'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient
Reinforcement Learning. In: Advances in Computer Games: 14th International
Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected
Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1'
apa: 'Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree
Search with Policy-Gradient Reinforcement Learning. In Advances in Computer
Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July
1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing.
https://doi.org/10.1007/978-3-319-27992-3_1'
bibtex: '@inproceedings{Graf_Platzner_2015, title={Adaptive Playouts in Monte-Carlo
Tree Search with Policy-Gradient Reinforcement Learning}, DOI={10.1007/978-3-319-27992-3_1},
booktitle={Advances in Computer Games: 14th International Conference, ACG 2015,
Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, publisher={Springer
International Publishing}, author={Graf, Tobias and Platzner, Marco}, year={2015},
pages={1–11} }'
chicago: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree
Search with Policy-Gradient Reinforcement Learning.” In Advances in Computer
Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July
1-3, 2015, Revised Selected Papers, 1–11. Springer International Publishing,
2015. https://doi.org/10.1007/978-3-319-27992-3_1.'
ieee: 'T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with
Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th
International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised
Selected Papers, 2015, pp. 1–11.'
mla: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search
with Policy-Gradient Reinforcement Learning.” Advances in Computer Games: 14th
International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised
Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.'
short: 'T. Graf, M. Platzner, in: Advances in Computer Games: 14th International
Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected
Papers, Springer International Publishing, 2015, pp. 1–11.'
date_created: 2019-09-09T09:07:46Z
date_updated: 2022-01-06T06:51:29Z
department:
- _id: '78'
doi: 10.1007/978-3-319-27992-3_1
language:
- iso: eng
page: 1-11
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 'Advances in Computer Games: 14th International Conference, ACG 2015,
Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers'
publisher: Springer International Publishing
status: public
title: Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement
Learning
type: conference
user_id: '40778'
year: '2015'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '303'
abstract:
- lang: eng
text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use
on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling
existentsoftware to automatically utilize accelerators at runtime. BAARis based
on the LLVM Compiler Infrastructure and has aclient-server architecture. The client
runs the program to beaccelerated in an environment which allows program analysisand
profiling. Program parts which are identified as suitable forthe available accelerator
are exported and sent to the server.The server optimizes these program parts for
the acceleratorand provides RPC execution for the client. The client transformsits
program to utilize accelerated execution on the server foroffloaded program parts.
We evaluate our work with a proofof-concept implementation of BAAR that uses an
Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading,
parallelization and vectorization of suitable programparts. The practicality of
BAAR for real-world examples is shownbased on a study of stencil codes. Our results
show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints
over the same code compiled with the Intel Compiler atoptimization level O2 and
running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand
evaluation we outline future directions of research, e.g.,offloading more fine-granular
program parts than functions, amore sophisticated communication mechanism or introducing
onstack-replacement.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on
Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning
Computing Systems (ADAPT). ; 2015.'
apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores. Proceedings of the 5th International Workshop on
Adaptive Self-Tuning Computing Systems (ADAPT).
bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International
Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen,
Marvin and Plessl, Christian}, year={2015} }'
chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores.” In Proceedings of the 5th International
Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration
on Many-Cores,” 2015.
mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores.” Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.'
date_created: 2017-10-17T12:41:51Z
date_updated: 2023-09-26T13:29:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
external_id:
arxiv:
- '1412.3906'
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:46:46Z
date_updated: 2019-08-01T09:10:44Z
file_id: '1442'
file_name: 303-plessl15_adapt.pdf
file_size: 1176620
relation: main_file
file_date_updated: 2019-08-01T09:10:44Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning
Computing Systems (ADAPT)
quality_controlled: '1'
status: public
title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1773'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: J.
full_name: T. Anderson, J.
last_name: T. Anderson
- first_name: A.
full_name: Borga, A.
last_name: Borga
- first_name: H.
full_name: Boterenbrood, H.
last_name: Boterenbrood
- first_name: H.
full_name: Chen, H.
last_name: Chen
- first_name: K.
full_name: Chen, K.
last_name: Chen
- first_name: G.
full_name: Drake, G.
last_name: Drake
- first_name: D.
full_name: Francis, D.
last_name: Francis
- first_name: B.
full_name: Gorini, B.
last_name: Gorini
- first_name: F.
full_name: Lanni, F.
last_name: Lanni
- first_name: Giovanna
full_name: Lehmann-Miotto, Giovanna
last_name: Lehmann-Miotto
- first_name: L.
full_name: Levinson, L.
last_name: Levinson
- first_name: J.
full_name: Narevicius, J.
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A.
full_name: Roich, A.
last_name: Roich
- first_name: S.
full_name: Ryu, S.
last_name: Ryu
- first_name: F.
full_name: P. Schreuder, F.
last_name: P. Schreuder
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J.
full_name: Vermeulen, J.
last_name: Vermeulen
- first_name: J.
full_name: Zhang, J.
last_name: Zhang
citation:
ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015.
doi:10.1145/2675743.2771824'
apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen,
K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson,
L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli,
W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et
al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project
– Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824},
booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM},
author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H.
and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni,
F. and et al.}, year={2015} }'
chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K.
Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX
Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.
ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in
the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”
2015, doi: 10.1145/2675743.2771824.'
mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS
FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen,
G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J.
Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen,
J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM,
2015.'
date_created: 2018-03-23T14:09:33Z
date_updated: 2023-09-26T13:31:01Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/2675743.2771824
language:
- iso: eng
publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)
publisher: ACM
quality_controlled: '1'
status: public
title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis
and Optimization of a Memory-Bounded Algorithm
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1768'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Peter J.
full_name: Schreier, Peter J.
last_name: Schreier
citation:
ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing.
Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z'
apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort:
Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z'
bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate
Computing}, DOI={10.1007/s00287-015-0911-z},
number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl,
Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399}
}'
chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort:
Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.'
ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate
Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.'
mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik
Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.'
short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.
date_created: 2018-03-23T13:58:34Z
date_updated: 2023-09-26T13:30:22Z
department:
- _id: '27'
- _id: '518'
- _id: '263'
- _id: '78'
doi: 10.1007/s00287-015-0911-z
issue: '5'
keyword:
- approximate computing
- survey
language:
- iso: eng
page: 396-399
publication: Informatik Spektrum
publisher: Springer
quality_controlled: '1'
status: public
title: 'Aktuelles Schlagwort: Approximate Computing'
type: journal_article
user_id: '15278'
year: '2015'
...