---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '347'
abstract:
- lang: eng
text: Dynamic thread duplication is a known redundancy technique for multi-cores.
The approach duplicates a thread under observation for some time period and compares
the signatures of the two threads to detect errors. Hybrid multi-cores, typically
implemented on platform FPGAs, enable the unique option of running the thread
under observation and its copy in different modalities, i.e., software and hardware.
We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing.
In this paper we present the concept of thread shadowing and an implementation
on a multi-threaded hybrid multi-core architecture. We report on experiments with
a block-processing application and demonstrate the overheads, detection latencies
and coverage for a range of thread shadowing modes. The results show that trans-modal
thread shadowing, although bearing long detection latencies, offers attractive
coverage at a low overhead.
author:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid
Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP,
Bertels K, eds. Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer;
2014:283-290. doi:10.1007/978-3-319-05960-0_30'
apa: 'Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio,
J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer.
https://doi.org/10.1007/978-3-319-05960-0_30'
bibtex: '@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer
Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores
for Error Detection}, DOI={10.1007/978-3-319-05960-0_30},
booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner,
Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso,
JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic
Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the
10th International Symposium on Applied Reconfigurable Computing (ARC), edited
by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels,
283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.'
ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on
Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.'
mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer
et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.'
short: 'S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso,
K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.'
date_created: 2017-10-17T12:41:59Z
date_updated: 2022-01-06T06:59:18Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-05960-0_30
editor:
- first_name: Diana
full_name: Goehringer, Diana
last_name: Goehringer
- first_name: MarcoDomenico
full_name: Santambrogio, MarcoDomenico
last_name: Santambrogio
- first_name: JoãoM.P.
full_name: Cardoso, JoãoM.P.
last_name: Cardoso
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:26:16Z
date_updated: 2018-03-20T07:26:16Z
file_id: '1417'
file_name: 347-meisner13_xx_SFB1__1_.pdf
file_size: 1168877
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:26:16Z
has_accepted_license: '1'
language:
- iso: eng
page: 283-290
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: 'Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error
Detection'
type: conference
user_id: '398'
year: '2014'
...
---
_id: '1782'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science.
Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2'
apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in
Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25).
Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2'
bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture
Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2},
number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer},
author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25},
collection={Lecture Notes in Computer Science} }'
chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection
in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25.
Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.'
ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf.
on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games
(CG), Springer, Switzerland, 2014, pp. 14–25.'
date_created: 2018-03-26T13:50:37Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1007/978-3-319-09165-5_2
issue: '8427'
page: 14-25
place: Switzerland
publication: Proc. Conf. on Computers and Games (CG)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: On Semeai Detection in Monte-Carlo Go
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '399'
abstract:
- lang: eng
text: Ensuring memory access security is a challenge for reconfigurable systems
with multiple cores. Previous work introduced access monitors attached to the
memory subsystem to ensure that the cores adhere to pre-defined protocols when
accessing memory. In this paper, we combine access monitors with a formal runtime
verification technique known as proof-carrying hardware to guarantee memory security.
We extend previous work on proof-carrying hardware by covering sequential circuits
and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an
embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach
and the capabilities of the prototype, which constitutes the first realization
of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA
are measured as 2x-10x, depending on the resource type. The delay overhead is
substantial with almost 100x, but this is an extremely pessimistic estimate that
will be lowered once accurate timing analysis for FPGA overlays become available.
Finally, reconfiguration time for the virtual FPGA is about one order of magnitude
lower than for the native Zynq fabric.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers:
Combining Formal Verification with Monitoring. In: Proceedings of the International
Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771'
apa: 'Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in
Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings
of the International Conference on Field-Programmable Technology (FPT) (pp.
167–174). https://doi.org/10.1109/FPT.2014.7082771'
bibtex: '@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security
in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco},
year={2014}, pages={167–174} }'
chicago: 'Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security
in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In
Proceedings of the International Conference on Field-Programmable Technology
(FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771.'
ieee: 'T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable
Computers: Combining Formal Verification with Monitoring,” in Proceedings of
the International Conference on Field-Programmable Technology (FPT), 2014,
pp. 167–174.'
mla: 'Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining
Formal Verification with Monitoring.” Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.'
short: 'T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.'
date_created: 2017-10-17T12:42:09Z
date_updated: 2022-01-06T07:00:05Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/FPT.2014.7082771
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T06:57:44Z
date_updated: 2018-03-20T06:57:44Z
file_id: '1380'
file_name: 399-wiersema14_fpt_IEEE_approved.pdf
file_size: 404328
relation: main_file
success: 1
file_date_updated: 2018-03-20T06:57:44Z
has_accepted_license: '1'
language:
- iso: eng
page: 167-174
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
status: public
title: 'Memory Security in Reconfigurable Computers: Combining Formal Verification
with Monitoring'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '408'
abstract:
- lang: eng
text: Verification of hardware and software usually proceeds separately, software
analysis relying on the correctness of processors executing instructions. This
assumption is valid as long as the software runs on standard CPUs that have been
extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption.In
this paper we present an approach for integrating software analyses with hardware
verification, specifically targeting custom instruction set extensions. We propose
three different techniques for deriving the properties to be proven for the hardware
implementation of a custom instruction in order to support software analyses.
The techniques are designed to explore the trade-off between generality and efficiency
and span from proving functional equivalence over checking the rules of a particular
analysis domain to verifying actual pre and post conditions resulting from program
analysis. We demonstrate and compare the three techniques on example programs
with custom instructions, using stateof-the-art software and hardware verification
techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
citation:
ama: 'Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware
Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International
Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19'
apa: Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating
Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings
of the 11th International Conference on Integrated Formal Methods (iFM) (pp.
307–322). https://doi.org/10.1007/978-3-319-10181-1_19
bibtex: '@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating
Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19},
booktitle={Proceedings of the 11th International Conference on Integrated Formal
Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema,
Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors},
year={2014}, pages={307–322}, collection={LNCS} }'
chicago: Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim.
“Integrating Software and Hardware Verification.” In Proceedings of the 11th
International Conference on Integrated Formal Methods (IFM), edited by Elvira
Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19.
ieee: M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software
and Hardware Verification,” in Proceedings of the 11th International Conference
on Integrated Formal Methods (iFM), 2014, pp. 307–322.
mla: Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.”
Proceedings of the 11th International Conference on Integrated Formal Methods
(IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.
short: 'M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski
(Eds.), Proceedings of the 11th International Conference on Integrated Formal
Methods (IFM), 2014, pp. 307–322.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2022-01-06T07:00:14Z
ddc:
- '040'
department:
- _id: '77'
- _id: '78'
doi: 10.1007/978-3-319-10181-1_19
editor:
- first_name: Elvira
full_name: Albert, Elvira
last_name: Albert
- first_name: Emil
full_name: Sekerinski, Emil
last_name: Sekerinski
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:35:28Z
date_updated: 2018-03-16T11:35:28Z
file_id: '1364'
file_name: 408-jakobs14_ifm.pdf
file_size: 561325
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:35:28Z
has_accepted_license: '1'
language:
- iso: eng
page: 307-322
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the 11th International Conference on Integrated Formal
Methods (iFM)
series_title: LNCS
status: public
title: Integrating Software and Hardware Verification
type: conference
user_id: '477'
year: '2014'
...
---
_id: '433'
abstract:
- lang: eng
text: Virtual FPGAs are overlay architectures realized on top of physical FPGAs.
They are proposed to enhance or abstract away from the physical FPGA for experimenting
with novel architectures and design tool flows. In this paper, we present an embedding
of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip.
Such an embedding is required to fully harness the potential of virtual FPGAs,
in particular to give the virtual circuits access to main memory and operating
system services, and to enable a concurrent operation of virtualized and non-virtualized
circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS
operating system for hardware/software systems. Furthermore, we present an open
source tool flow to synthesize configurations for the virtual FPGA.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable
Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514'
apa: 'Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig)
(pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514'
bibtex: '@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={10.1109/ReConFig.2014.7032514},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner,
Marco}, year={2014}, pages={1–6} }'
chicago: 'Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays
into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In Proceedings of the
International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–6, 2014. https://doi.org/10.1109/ReConFig.2014.7032514.'
ieee: 'T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into
Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.'
mla: 'Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip:
ReconOS Meets ZUMA.” Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514.'
short: 'T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.'
date_created: 2017-10-17T12:42:16Z
date_updated: 2022-01-06T07:00:56Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ReConFig.2014.7032514
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:30:58Z
date_updated: 2018-03-16T11:30:58Z
file_id: '1355'
file_name: 433-wiersema14_reconfig_IEEE_approved.pdf
file_size: 369333
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:30:58Z
has_accepted_license: '1'
language:
- iso: eng
page: '1-6 '
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
status: public
title: 'Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '10602'
author:
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Schaefers L, Platzner M. A Novel Technique and its Application to Computer
Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374.
doi:10.1109/TCIAIG.2014.2346997
apa: Schaefers, L., & Platzner, M. (2014). A Novel Technique and its Application
to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games,
6(3), 361–374. https://doi.org/10.1109/TCIAIG.2014.2346997
bibtex: '@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application
to Computer Go}, volume={6}, DOI={10.1109/TCIAIG.2014.2346997},
number={3}, journal={IEEE Transactions on Computational Intelligence and AI in
Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374}
}'
chicago: 'Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application
to Computer Go.” IEEE Transactions on Computational Intelligence and AI in
Games 6, no. 3 (2014): 361–74. https://doi.org/10.1109/TCIAIG.2014.2346997.'
ieee: L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer
Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol.
6, no. 3, pp. 361–374, 2014.
mla: Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application
to Computer Go.” IEEE Transactions on Computational Intelligence and AI in
Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.
short: L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence
and AI in Games 6 (2014) 361–374.
date_created: 2019-07-10T09:22:43Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TCIAIG.2014.2346997
intvolume: ' 6'
issue: '3'
language:
- iso: eng
page: 361-374
publication: IEEE Transactions on Computational Intelligence and AI in Games
status: public
title: A Novel Technique and its Application to Computer Go
type: journal_article
user_id: '3118'
volume: 6
year: '2014'
...
---
_id: '10603'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE
Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174
apa: Giefers, H., & Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core.
IEEE Transactions on Computers, 63(12), 2919–2932. https://doi.org/10.1109/TC.2013.174
bibtex: '@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh
Many-Core}, volume={63}, DOI={10.1109/TC.2013.174},
number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner
and Platzner, Marco}, year={2014}, pages={2919–2932} }'
chicago: 'Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh
Many-Core.” IEEE Transactions on Computers 63, no. 12 (2014): 2919–32.
https://doi.org/10.1109/TC.2013.174.'
ieee: H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,”
IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.
mla: Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.”
IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.
short: H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.
date_created: 2019-07-10T09:22:44Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TC.2013.174
intvolume: ' 63'
issue: '12'
language:
- iso: eng
page: 2919 - 2932
publication: IEEE Transactions on Computers
status: public
title: An FPGA-based Reconfigurable Mesh Many-Core
type: journal_article
user_id: '398'
volume: 63
year: '2014'
...
---
_id: '10621'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
citation:
ama: 'Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated
Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW).
RAW. ; 2014. doi:10.1109/IPDPSW.2014.37'
apa: 'Anwer, J., Platzner, M., & Meisner, S. (2014). FPGA Redundancy Configurations:
An Automated Design Space Exploration. In Reconfigurable Architectures Workshop
(RAW). https://doi.org/10.1109/IPDPSW.2014.37'
bibtex: '@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy
Configurations: An Automated Design Space Exploration}, DOI={10.1109/IPDPSW.2014.37},
booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb
and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }'
chicago: 'Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy
Configurations: An Automated Design Space Exploration.” In Reconfigurable Architectures
Workshop (RAW). RAW, 2014. https://doi.org/10.1109/IPDPSW.2014.37.'
ieee: 'J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An
Automated Design Space Exploration,” in Reconfigurable Architectures Workshop
(RAW), 2014.'
mla: 'Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design
Space Exploration.” Reconfigurable Architectures Workshop (RAW), 2014,
doi:10.1109/IPDPSW.2014.37.'
short: 'J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop
(RAW), 2014.'
date_created: 2019-07-10T09:32:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/IPDPSW.2014.37
language:
- iso: eng
publication: Reconfigurable Architectures Workshop (RAW)
series_title: RAW
status: public
title: 'FPGA Redundancy Configurations: An Automated Design Space Exploration'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10627'
author:
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
citation:
ama: Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board. Paderborn University; 2014.
apa: Bockhorn, A. (2014). Echtzeit Klassifikation von sEMG Signalen mit einem
low-cost DSP Evaluation Board. Paderborn University.
bibtex: '@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit
einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn,
Arne}, year={2014} }'
chicago: Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem
Low-Cost DSP Evaluation Board. Paderborn University, 2014.
ieee: A. Bockhorn, Echtzeit Klassifikation von sEMG Signalen mit einem low-cost
DSP Evaluation Board. Paderborn University, 2014.
mla: Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board. Paderborn University, 2014.
short: A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
DSP Evaluation Board, Paderborn University, 2014.
date_created: 2019-07-10T09:40:25Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation
Board
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10632'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. A computer vision-based approach to high density
EMG pattern recognition using structural similarity. In: Proc. MyoElectric
Controls Symposium (MEC). ; 2014.'
apa: Boschmann, A., & Platzner, M. (2014). A computer vision-based approach
to high density EMG pattern recognition using structural similarity. In Proc.
MyoElectric Controls Symposium (MEC).
bibtex: '@inproceedings{Boschmann_Platzner_2014, title={A computer vision-based
approach to high density EMG pattern recognition using structural similarity},
booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander
and Platzner, Marco}, year={2014} }'
chicago: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
to High Density EMG Pattern Recognition Using Structural Similarity.” In Proc.
MyoElectric Controls Symposium (MEC), 2014.
ieee: A. Boschmann and M. Platzner, “A computer vision-based approach to high density
EMG pattern recognition using structural similarity,” in Proc. MyoElectric
Controls Symposium (MEC), 2014.
mla: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
to High Density EMG Pattern Recognition Using Structural Similarity.” Proc.
MyoElectric Controls Symposium (MEC), 2014.
short: 'A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC),
2014.'
date_created: 2019-07-10T11:02:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. MyoElectric Controls Symposium (MEC)
status: public
title: A computer vision-based approach to high density EMG pattern recognition using
structural similarity
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10633'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing
electrode displacement effect using structural similarity. In: Proc. IEEE Int.
Conf. Eng. Med. Biolog. (EMBC). ; 2014.'
apa: 'Boschmann, A., & Platzner, M. (2014). Towards robust HD EMG pattern recognition:
Reducing electrode displacement effect using structural similarity. In Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC).'
bibtex: '@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern
recognition: Reducing electrode displacement effect using structural similarity},
booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann,
Alexander and Platzner, Marco}, year={2014} }'
chicago: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern
Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.”
In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
ieee: 'A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition:
Reducing electrode displacement effect using structural similarity,” in Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
mla: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition:
Reducing Electrode Displacement Effect Using Structural Similarity.” Proc.
IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.'
short: 'A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC),
2014.'
date_created: 2019-07-10T11:02:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)
status: public
title: 'Towards robust HD EMG pattern recognition: Reducing electrode displacement
effect using structural similarity'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10640'
author:
- first_name: Marcel
full_name: Brand, Marcel
last_name: Brand
citation:
ama: Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University; 2014.
apa: Brand, M. (2014). A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University.
bibtex: '@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as
a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel},
year={2014} }'
chicago: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
ieee: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
mla: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array. Paderborn University, 2014.
short: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained
Array, Paderborn University, 2014.
date_created: 2019-07-10T11:03:41Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: A Generalized Loop Accelerator Implemented as a Coarse-Grained Array
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10645'
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
citation:
ama: Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores.
Paderborn University; 2014.
apa: Damschen, M. (2014). Easy-to-use-on-the-fly binary program acceleration
on many-cores. Paderborn University.
bibtex: '@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration
on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014}
}'
chicago: Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration
on Many-Cores. Paderborn University, 2014.
ieee: M. Damschen, Easy-to-use-on-the-fly binary program acceleration on many-cores.
Paderborn University, 2014.
mla: Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration on
Many-Cores. Paderborn University, 2014.
short: M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores,
Paderborn University, 2014.
date_created: 2019-07-10T11:08:47Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Easy-to-use-on-the-fly binary program acceleration on many-cores
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10654'
author:
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable
Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC).
; 2014.'
apa: Glette, K., & Kaufmann, P. (2014). Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System. In IEEE Congress on Evolutionary
Computation (CEC).
bibtex: '@inproceedings{Glette_Kaufmann_2014, title={Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System}, booktitle={IEEE Congress on Evolutionary
Computation (CEC)}, author={Glette, Kyrre and Kaufmann, Paul}, year={2014} }'
chicago: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration
for an Evolvable Hardware Classifier System.” In IEEE Congress on Evolutionary
Computation (CEC), 2014.
ieee: K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable
Hardware Classifier System,” in IEEE Congress on Evolutionary Computation (CEC),
2014.
mla: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for
an Evolvable Hardware Classifier System.” IEEE Congress on Evolutionary Computation
(CEC), 2014.
short: 'K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC),
2014.'
date_created: 2019-07-10T11:13:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
publication: IEEE Congress on Evolutionary Computation (CEC)
status: public
title: Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10665'
author:
- first_name: Christoph
full_name: Hagedorn, Christoph
last_name: Hagedorn
citation:
ama: Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University;
2014.
apa: Hagedorn, C. (2014). Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University.
bibtex: '@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn
University}, author={Hagedorn, Christoph}, year={2014} }'
chicago: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
ieee: C. Hagedorn, Entwicklung einer codegrößenoptimierten Softwarebibliothek
für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University,
2014.
mla: Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University,
2014.
short: C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014.
date_created: 2019-07-10T11:15:09Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
title: Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller
in netzunabhängigen Notleuchten
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10674'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437},
booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
}'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on
Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic
and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
platforms
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10677'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems
(ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches:
A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf.
on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719},
booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl.
Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014,
pp. 31–37, doi:10.1109/ICES.2014.7008719.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10679'
author:
- first_name: Fabian
full_name: König, Fabian
last_name: König
citation:
ama: König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese. Paderborn University; 2014.
apa: König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese. Paderborn University.
bibtex: '@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung
einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian},
year={2014} }'
chicago: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
ieee: F. König, EMG-basierte simultane und proportionale Online-Steuerung einer
virtuellen Prothese. Paderborn University, 2014.
mla: König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung
Einer Virtuellen Prothese. Paderborn University, 2014.
short: F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
Virtuellen Prothese, Paderborn University, 2014.
date_created: 2019-07-10T11:23:20Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
title: EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen
Prothese
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10701'
author:
- first_name: Benjamin
full_name: Koch, Benjamin
last_name: Koch
citation:
ama: Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University; 2014.
apa: Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University.
bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
year={2014} }'
chicago: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
ieee: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University, 2014.
mla: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University, 2014.
short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...