---
_id: '10774'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based
methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE
International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2013). A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS) (pp. 83–88). IEEE. https://doi.org/10.1109/DFT.2013.6653587
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2013,
title={A fast TCAD-based methodology for Variation analysis of emerging nano-devices},
DOI={10.1109/DFT.2013.6653587},
booktitle={2013 IEEE International Symposium on Defect and Fault Tolerance in
VLSI and Nanotechnology Systems (DFTS)}, publisher={IEEE}, author={Ghasemzadeh
Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli,
Giovanni}, year={2013}, pages={83–88} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “A Fast TCAD-Based Methodology for Variation Analysis
of Emerging Nano-Devices.” In 2013 IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 83–88. IEEE, 2013.
https://doi.org/10.1109/DFT.2013.6653587.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“A fast TCAD-based methodology for Variation analysis of emerging nano-devices,”
in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS), 2013, pp. 83–88.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation
Analysis of Emerging Nano-Devices.” 2013 IEEE International Symposium on Defect
and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013,
pp. 83–88, doi:10.1109/DFT.2013.6653587.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS), IEEE, 2013, pp. 83–88.'
date_created: 2019-07-10T12:10:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2013.6653587
extern: '1'
language:
- iso: eng
page: 83-88
publication: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS)
publisher: IEEE
status: public
title: A fast TCAD-based methodology for Variation analysis of emerging nano-devices
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10775'
author:
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study. In:
2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673'
apa: 'Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013).
Vertically-stacked silicon nanowire transistors with controllable polarity: A
robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6).
IEEE. https://doi.org/10.1109/LATW.2013.6562673'
bibtex: '@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study},
DOI={10.1109/LATW.2013.6562673},
booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon,
Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013},
pages={1–6} }'
chicago: 'Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni
De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable
Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW,
1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.'
ieee: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study,”
in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.'
mla: 'Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors
with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test
Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.'
short: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th
Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.'
date_created: 2019-07-10T12:10:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/LATW.2013.6562673
extern: '1'
language:
- iso: eng
page: 1-6
publication: 2013 14th Latin American Test Workshop-LATW
publisher: IEEE
status: public
title: 'Vertically-stacked silicon nanowire transistors with controllable polarity:
A robustness study'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '13645'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proceedings of the International Conference on Computers and Games (CG).
Springer; 2013.'
apa: Graf, T., Schäfers, L., & Platzner, M. (2013). On Semeai Detection in Monte-Carlo
Go. In Proceedings of the International Conference on Computers and Games (CG).
Springer.
bibtex: '@inproceedings{Graf_Schäfers_Platzner_2013, title={On Semeai Detection
in Monte-Carlo Go.}, booktitle={Proceedings of the International Conference on
Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schäfers,
Lars and Platzner, Marco}, year={2013} }'
chicago: Graf, Tobias, Lars Schäfers, and Marco Platzner. “On Semeai Detection in
Monte-Carlo Go.” In Proceedings of the International Conference on Computers
and Games (CG). Springer, 2013.
ieee: T. Graf, L. Schäfers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go.,” in Proceedings of the International Conference on Computers and Games
(CG), 2013.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings
of the International Conference on Computers and Games (CG), Springer, 2013.
short: 'T. Graf, L. Schäfers, M. Platzner, in: Proceedings of the International
Conference on Computers and Games (CG), Springer, 2013.'
date_created: 2019-10-04T22:50:51Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Conference on Computers and Games (CG)
publisher: Springer
status: public
title: On Semeai Detection in Monte-Carlo Go.
type: conference
user_id: '398'
year: '2013'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '505'
abstract:
- lang: eng
text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT
services that will be provided by assembling modular software components available
on world-wide markets. After suitable components have been found, they are automatically
integrated, configured and brought to execution in an On-The-Fly Compute Center.
We envision that these future compute centers will continue to leverage three
current trends in large scale computing which are an increasing amount of parallel
processing, a trend to use heterogeneous computing resources, and—in the light
of rising energy cost—energy-efficiency as a primary goal in the design and operation
of computing systems. In this paper, we point out three research challenges and
our current work in these areas.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
citation:
ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings
of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous
Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232'
apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide,
F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232'
bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232},
booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus
and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide,
Friedhelm}, year={2013} }'
chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm
Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology
for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.'
ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.'
mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for
Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.'
short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in:
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS), IEEE, 2013.'
date_created: 2017-10-17T12:42:30Z
date_updated: 2023-09-26T13:38:20Z
ddc:
- '040'
department:
- _id: '63'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISORC.2013.6913232
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T13:38:56Z
date_updated: 2018-03-15T13:38:56Z
file_id: '1308'
file_name: 505-Plessl13_seus.pdf
file_size: 1040834
relation: main_file
success: 1
file_date_updated: 2018-03-15T13:38:56Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services'
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '1787'
author:
- first_name: Tim
full_name: Suess, Tim
last_name: Suess
- first_name: Andrew
full_name: Schoenrock, Andrew
last_name: Schoenrock
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the
Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136'
apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro
Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel
and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136
bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington,
DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer},
DOI={10.1109/IPDPSW.2013.136},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and
Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }'
chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl.
“Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int.
Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington,
DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.'
ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining
on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.'
mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”
Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW),
IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.
short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society,
Washington, DC, USA, 2013, pp. 64–73.'
date_created: 2018-03-26T14:51:05Z
date_updated: 2023-09-26T13:38:05Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
- _id: '63'
doi: 10.1109/IPDPSW.2013.136
language:
- iso: eng
page: 64-73
place: Washington, DC, USA
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publication_identifier:
isbn:
- 978-0-7695-4979-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '2097'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial
matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology
(ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125'
apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of
an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field
Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation
of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation
of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on
Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012.
https://doi.org/10.1109/FPT.2012.6412125.
ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate
polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable
Technology (ICFPT), 2012, pp. 135–140.
mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an
Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2012, pp. 135–140.'
date_created: 2018-03-29T14:34:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/FPT.2012.6412125
page: 135-140
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: FPGA-based design and implementation of an approximate polynomial matrix EVD
algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2100'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind
signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG).
; 2012.'
apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive
blind signal separation algorithm. In Int. Architecture and Engineering Symp.
(ARCHENG).
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order
convolutive blind signal separation algorithm}, booktitle={Int. Architecture and
Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering
Symp. (ARCHENG), 2012.
ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive
blind signal separation algorithm,” in Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG),
2012.'
date_created: 2018-03-29T14:43:18Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
publication: Int. Architecture and Engineering Symp. (ARCHENG)
status: public
title: FPGA implementation of a second-order convolutive blind signal separation algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2103'
author:
- first_name: Martin
full_name: Wistuba, Martin
last_name: Wistuba
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction
Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence
and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143'
apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian
Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143
bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian
Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143},
booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE},
author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012},
pages={91–99} }'
chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian
Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.
ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction
Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence
and Games (CIG), 2012, pp. 91–99.
mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for
Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG),
IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.
short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.'
date_created: 2018-03-29T14:59:35Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/CIG.2012.6374143
page: 91-99
publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG)
publisher: IEEE
status: public
title: Comparison of Bayesian Move Prediction Systems for Computer Go
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2172'
author:
- first_name: Kris
full_name: Thielemans, Kris
last_name: Thielemans
- first_name: Charalampos
full_name: Tsoumpas, Charalampos
last_name: Tsoumpas
- first_name: Sanida
full_name: Mustafovic, Sanida
last_name: Mustafovic
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Pablo
full_name: Aguiar, Pablo
last_name: Aguiar
- first_name: Nikolaos
full_name: Dikaios, Nikolaos
last_name: Dikaios
- first_name: Matthew
full_name: W Jacobson, Matthew
last_name: W Jacobson
citation:
ama: 'Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic
Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883.
doi:10.1088/0031-9155/57/4/867'
apa: 'Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios,
N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction
Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867'
bibtex: '@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012,
title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57},
DOI={10.1088/0031-9155/57/4/867},
number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing},
author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and
Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew},
year={2012}, pages={867–883} }'
chicago: 'Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel,
Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic
Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no.
4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.'
ieee: 'K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction
Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883,
2012.'
mla: 'Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction
Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing,
2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.'
short: K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios,
M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883.
date_created: 2018-04-03T09:02:27Z
date_updated: 2022-01-06T06:55:12Z
department:
- _id: '27'
- _id: '78'
doi: 10.1088/0031-9155/57/4/867
intvolume: ' 57'
issue: '4'
page: 867-883
publication: Physics in Medicine and Biology
publisher: IOP Publishing
status: public
title: 'STIR: Software for Tomographic Image Reconstruction Release 2'
type: journal_article
user_id: '24135'
volume: 57
year: '2012'
...
---
_id: '2173'
author:
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
citation:
ama: Redif S, Kasap S. Parallel algorithm for computation of second-order sequential
best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343
apa: Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order
sequential best rotations. Int. Journal of Electronics, 100(12),
1646–1651. https://doi.org/10.1080/00207217.2012.751343
bibtex: '@article{Redif_Kasap_2012, title={Parallel algorithm for computation of
second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343},
number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis},
author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }'
chicago: 'Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of
Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100,
no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.'
ieee: S. Redif and S. Kasap, “Parallel algorithm for computation of second-order
sequential best rotations,” Int. Journal of Electronics, vol. 100, no.
12, pp. 1646–1651, 2012.
mla: Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order
Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no.
12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343.
short: S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651.
date_created: 2018-04-03T09:05:36Z
date_updated: 2022-01-06T06:55:12Z
department:
- _id: '27'
- _id: '78'
doi: 10.1080/00207217.2012.751343
intvolume: ' 100'
issue: '12'
page: 1646-1651
publication: Int. Journal of Electronics
publisher: Taylor & Francis
status: public
title: Parallel algorithm for computation of second-order sequential best rotations
type: journal_article
user_id: '24135'
volume: 100
year: '2012'
...
---
_id: '2174'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Khaled
full_name: Benkrid, Khaled
last_name: Benkrid
citation:
ama: Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular
Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers.
2012;7(6):1312-1328.
apa: Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation
for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of
Computers, 7(6), 1312–1328.
bibtex: '@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation
for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6},
journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap,
Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }'
chicago: 'Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation
for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of
Computers 7, no. 6 (2012): 1312–28.'
ieee: S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for
Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers,
vol. 7, no. 6, pp. 1312–1328, 2012.
mla: Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation
for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of
Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.
short: S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328.
date_created: 2018-04-03T09:08:00Z
date_updated: 2022-01-06T06:55:12Z
department:
- _id: '27'
- _id: '78'
intvolume: ' 7'
issue: '6'
page: 1312-1328
publication: Journal of Computers
publisher: Academy Publishers
status: public
title: Parallel Processor Design and Implementation for Molecular Dynamics Simulations
on a FPGA Parallel Computer
type: journal_article
user_id: '24135'
volume: 7
year: '2012'
...
---
_id: '586'
abstract:
- lang: eng
text: FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They
combine the computational power of application specific hardware with software-like
flexibility. At runtime, they can adjust their functionality by downloading new
hardware modules and integrating their functionality. Due to their growing capabilities,
the demands made to reconfigurable hardware grow. Their deployment in increasingly
security critical scenarios requires new ways of enforcing security since a failure
in security has severe consequences. Aside from financial losses, a loss of human
life and risks to national security are possible. With this work I present the
novel and groundbreaking concept of proof-carrying hardware. It is a method for
the verification of properties of hardware modules to guarantee security for a
target platform at runtime. The producer of a hardware module delivers based on
the consumer's safety policy a safety proof in combination with the reconfiguration
bitstream. The extensive computation of a proof is a contrast to the comparatively
undemanding checking of the proof. I present a prototype based on open-source
tools and an abstract FPGA architecture and bitstream format. The proof of the
usability of proof-carrying hardware provides the evaluation of the prototype
with the exemplary application of securing combinational and bounded sequential
equivalence of reference monitor modules for memory safety.
- lang: ger
text: FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr
wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit
einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität
anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität
integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare
Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue
Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende
Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von
Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit
stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor.
Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um
die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines
Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten,
einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige
Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen
Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend
auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt
Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware
erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung
von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen
zur Speichersicherheit.
author:
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
citation:
ama: 'Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn; 2012.'
apa: 'Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn.'
bibtex: '@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach
to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky,
Stephanie}, year={2012} }'
chicago: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to
Reconfigurable Hardware Security. Universität Paderborn, 2012.'
ieee: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn, 2012.'
mla: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn, 2012.'
short: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security, Universität Paderborn, 2012.'
date_created: 2017-10-17T12:42:46Z
date_updated: 2022-01-06T07:02:44Z
ddc:
- '040'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:38:19Z
date_updated: 2018-03-15T08:38:19Z
file_id: '1261'
file_name: 586-Drzevitzky-PhD_01.pdf
file_size: 1438436
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:38:19Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423
oa: '1'
page: '114'
project:
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security'
type: dissertation
user_id: '477'
year: '2012'
...
---
_id: '587'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
citation:
ama: Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for
Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.
apa: Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming
models for reconfigurable heterogeneous multi-cores. Awareness Magazine.
bibtex: '@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models
for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine},
author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus
and Lübbers, Enno}, year={2012} }'
chicago: Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno
Lübbers. Programming Models for Reconfigurable Heterogeneous Multi-Cores.
Awareness Magazine, 2012.
ieee: C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming
models for reconfigurable heterogeneous multi-cores. Awareness Magazine, 2012.
mla: Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous
Multi-Cores. Awareness Magazine, 2012.
short: C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models
for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.
date_created: 2017-10-17T12:42:46Z
date_updated: 2022-01-06T07:02:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:37:02Z
date_updated: 2018-03-15T08:37:02Z
file_id: '1260'
file_name: 587-2012_plessl_awareness_magazine.pdf
file_size: 353057
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:37:02Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Awareness Magazine
status: public
title: Programming models for reconfigurable heterogeneous multi-cores
type: misc
user_id: '398'
year: '2012'
...
---
_id: '10636'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern
recognition based myoelectric control caused by electrode shift using a high density
electrode array. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ;
2012.'
apa: Boschmann, A., & Platzner, M. (2012). Reducing classification accuracy
degradation of pattern recognition based myoelectric control caused by electrode
shift using a high density electrode array. In Proc. IEEE Int. Conf. Eng. Med.
Biolog. (EMBC).
bibtex: '@inproceedings{Boschmann_Platzner_2012, title={Reducing classification
accuracy degradation of pattern recognition based myoelectric control caused by
electrode shift using a high density electrode array}, booktitle={Proc. IEEE Int.
Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco},
year={2012} }'
chicago: Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy
Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode
Shift Using a High Density Electrode Array.” In Proc. IEEE Int. Conf. Eng.
Med. Biolog. (EMBC), 2012.
ieee: A. Boschmann and M. Platzner, “Reducing classification accuracy degradation
of pattern recognition based myoelectric control caused by electrode shift using
a high density electrode array,” in Proc. IEEE Int. Conf. Eng. Med. Biolog.
(EMBC), 2012.
mla: Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy
Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode
Shift Using a High Density Electrode Array.” Proc. IEEE Int. Conf. Eng. Med.
Biolog. (EMBC), 2012.
short: 'A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC),
2012.'
date_created: 2019-07-10T11:03:21Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)
status: public
title: Reducing classification accuracy degradation of pattern recognition based myoelectric
control caused by electrode shift using a high density electrode array
type: conference
user_id: '3118'
year: '2012'
...
---
_id: '10650'
author:
- first_name: Denis
full_name: Dridger, Denis
last_name: Dridger
citation:
ama: Dridger D. Design and Implementation of a Nanophotonics Simulation Personality
for the Convey HC-1 Hybrid Core Computer. Paderborn University; 2012.
apa: Dridger, D. (2012). Design and Implementation of a Nanophotonics Simulation
Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University.
bibtex: '@book{Dridger_2012, title={Design and Implementation of a Nanophotonics
Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn
University}, author={Dridger, Denis}, year={2012} }'
chicago: Dridger, Denis. Design and Implementation of a Nanophotonics Simulation
Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University,
2012.
ieee: D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality
for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012.
mla: Dridger, Denis. Design and Implementation of a Nanophotonics Simulation
Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University,
2012.
short: D. Dridger, Design and Implementation of a Nanophotonics Simulation Personality
for the Convey HC-1 Hybrid Core Computer, Paderborn University, 2012.
date_created: 2019-07-10T11:10:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Design and Implementation of a Nanophotonics Simulation Personality for the
Convey HC-1 Hybrid Core Computer
type: mastersthesis
user_id: '3118'
year: '2012'
...
---
_id: '10652'
abstract:
- lang: eng
text: "The paradigm shift towards many-core parallelism is accompanied by two fundamental
questions: how should the many processors on a single die communicate to each
other and what are suitable programming models for these novel architectures?
In this thesis, the author tackles both questions by reviewing the reconfigurable
mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents
the design, implementation and evaluation of a many-core architecture that is
based on the execution principles and communication infrastructure of the reconfigurable
mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable
mesh processors with hundreds of autonomous cores are feasible. Several case studies
demonstrate the effectiveness of programming and illustrate why the reconfigurable
mesh is a promising model for many-cores."
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
citation:
ama: 'Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores.
Berlin: Logos Verlag Berlin GmbH; 2012.'
apa: 'Giefers, H. (2012). Design and Programming of Reconfigurable Mesh based
Many-Cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable
Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers,
Heiner}, year={2012} }'
chicago: 'Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based
Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.'
ieee: 'H. Giefers, Design and Programming of Reconfigurable Mesh based Many-Cores.
Berlin: Logos Verlag Berlin GmbH, 2012.'
mla: Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores.
Logos Verlag Berlin GmbH, 2012.
short: H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores,
Logos Verlag Berlin GmbH, Berlin, 2012.
date_created: 2019-07-10T11:13:12Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: '159'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3165-2
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Design and Programming of Reconfigurable Mesh based Many-Cores
type: dissertation
user_id: '3118'
year: '2012'
...
---
_id: '10658'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
citation:
ama: Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall
Go. Paderborn University; 2012.
apa: Graf, T. (2012). Adaptive Playouts in der Monte-Carlo Spielbaumsuche am
Anwendungsfall Go. Paderborn University.
bibtex: '@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche
am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias},
year={2012} }'
chicago: Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am
Anwendungsfall Go. Paderborn University, 2012.
ieee: T. Graf, Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall
Go. Paderborn University, 2012.
mla: Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall
Go. Paderborn University, 2012.
short: T. Graf, Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall
Go, Paderborn University, 2012.
date_created: 2019-07-10T11:13:34Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
title: Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go
type: mastersthesis
user_id: '3118'
year: '2012'
...
---
_id: '10667'
author:
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
citation:
ama: Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs.
Paderborn University; 2012.
apa: Hangmann, H. (2012). Generating Adjustable Temperature Gradients on modern
FPGAs. Paderborn University.
bibtex: '@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients
on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik},
year={2012} }'
chicago: Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern
FPGAs. Paderborn University, 2012.
ieee: H. Hangmann, Generating Adjustable Temperature Gradients on modern FPGAs.
Paderborn University, 2012.
mla: Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern
FPGAs. Paderborn University, 2012.
short: H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs,
Paderborn University, 2012.
date_created: 2019-07-10T11:15:12Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
title: Generating Adjustable Temperature Gradients on modern FPGAs
type: bachelorsthesis
user_id: '3118'
year: '2012'
...
---
_id: '10685'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Kyrre
full_name: Glette, Kyrre
last_name: Glette
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
citation:
ama: 'Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations
by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row
Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic
Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102'
apa: 'Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2012). Compensating
Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable
Functional Unit Row Classifier Architecture. International Journal of Adaptive,
Resilient and Autonomic Systems (IJARAS), 3(4), 17–31. https://doi.org/10.4018/jaras.2012100102'
bibtex: '@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource
Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional
Unit Row Classifier Architecture}, volume={3}, DOI={10.4018/jaras.2012100102},
number={4}, journal={International Journal of Adaptive, Resilient and Autonomic
Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette,
Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }'
chicago: 'Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. “Compensating
Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable
Functional Unit Row Classifier Architecture.” International Journal of Adaptive,
Resilient and Autonomic Systems (IJARAS) 3, no. 4 (2012): 17–31. https://doi.org/10.4018/jaras.2012100102.'
ieee: 'P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Compensating Resource
Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional
Unit Row Classifier Architecture,” International Journal of Adaptive, Resilient
and Autonomic Systems (IJARAS), vol. 3, no. 4, pp. 17–31, 2012.'
mla: 'Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable
Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.”
International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS),
vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:10.4018/jaras.2012100102.'
short: P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of
Adaptive, Resilient and Autonomic Systems (IJARAS) 3 (2012) 17–31.
date_created: 2019-07-10T11:28:10Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.4018/jaras.2012100102
intvolume: ' 3'
issue: '4'
language:
- iso: eng
page: 17-31
publication: International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)
publisher: IGI Global
status: public
title: 'Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time
Reconfigurable Functional Unit Row Classifier Architecture'
type: journal_article
user_id: '3118'
volume: 3
year: '2012'
...