---
_id: '10678'
author:
- first_name: Nikolaos
full_name: Ikonomakis, Nikolaos
last_name: Ikonomakis
citation:
ama: 'Ikonomakis N. PinSim: Schnelle Simulation Mit Pintools. Paderborn University;
2011.'
apa: 'Ikonomakis, N. (2011). PinSim: Schnelle Simulation mit Pintools. Paderborn
University.'
bibtex: '@book{Ikonomakis_2011, title={PinSim: Schnelle Simulation mit Pintools},
publisher={Paderborn University}, author={Ikonomakis, Nikolaos}, year={2011} }'
chicago: 'Ikonomakis, Nikolaos. PinSim: Schnelle Simulation Mit Pintools.
Paderborn University, 2011.'
ieee: 'N. Ikonomakis, PinSim: Schnelle Simulation mit Pintools. Paderborn
University, 2011.'
mla: 'Ikonomakis, Nikolaos. PinSim: Schnelle Simulation Mit Pintools. Paderborn
University, 2011.'
short: 'N. Ikonomakis, PinSim: Schnelle Simulation Mit Pintools, Paderborn University,
2011.'
date_created: 2019-07-10T11:23:19Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: 'PinSim: Schnelle Simulation mit Pintools'
type: bachelorsthesis
user_id: '3118'
year: '2011'
...
---
_id: '10680'
author:
- first_name: Hendrik
full_name: Kassner, Hendrik
last_name: Kassner
citation:
ama: Kassner H. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern.
Paderborn University; 2011.
apa: Kassner, H. (2011). MPI-CUDA Codegenerierung für Nanophoton Simulationen
auf Clustern. Paderborn University.
bibtex: '@book{Kassner_2011, title={MPI-CUDA Codegenerierung für Nanophoton Simulationen
auf Clustern}, publisher={Paderborn University}, author={Kassner, Hendrik}, year={2011}
}'
chicago: Kassner, Hendrik. MPI-CUDA Codegenerierung Für Nanophoton Simulationen
Auf Clustern. Paderborn University, 2011.
ieee: H. Kassner, MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern.
Paderborn University, 2011.
mla: Kassner, Hendrik. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf
Clustern. Paderborn University, 2011.
short: H. Kassner, MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern,
Paderborn University, 2011.
date_created: 2019-07-10T11:23:21Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern
type: bachelorsthesis
user_id: '3118'
year: '2011'
...
---
_id: '10687'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Evolution of Embedded Systems.
In: Müller-Schloer C, Schmeck H, Ungerer T, eds. Organic Computing---A Paradigm
Shift for Complex Systems. Vol 1. Autonomic Systems. Springer Basel; 2011:193-206.'
apa: Kaufmann, P., & Platzner, M. (2011). Multi-objective Intrinsic Evolution
of Embedded Systems. In C. Müller-Schloer, H. Schmeck, & T. Ungerer (Eds.),
Organic Computing---A Paradigm Shift for Complex Systems (Vol. 1, pp. 193–206).
Springer Basel.
bibtex: '@inbook{Kaufmann_Platzner_2011, series={Autonomic Systems}, title={Multi-objective
Intrinsic Evolution of Embedded Systems}, volume={1}, booktitle={Organic Computing---A
Paradigm Shift for Complex Systems}, publisher={Springer Basel}, author={Kaufmann,
Paul and Platzner, Marco}, editor={Müller-Schloer, Christian and Schmeck, Hartmut
and Ungerer, TheoEditors}, year={2011}, pages={193–206}, collection={Autonomic
Systems} }'
chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Evolution
of Embedded Systems.” In Organic Computing---A Paradigm Shift for Complex Systems,
edited by Christian Müller-Schloer, Hartmut Schmeck, and Theo Ungerer, 1:193–206.
Autonomic Systems. Springer Basel, 2011.
ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Evolution of Embedded
Systems,” in Organic Computing---A Paradigm Shift for Complex Systems,
vol. 1, C. Müller-Schloer, H. Schmeck, and T. Ungerer, Eds. Springer Basel, 2011,
pp. 193–206.
mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Evolution of
Embedded Systems.” Organic Computing---A Paradigm Shift for Complex Systems,
edited by Christian Müller-Schloer et al., vol. 1, Springer Basel, 2011, pp. 193–206.
short: 'P. Kaufmann, M. Platzner, in: C. Müller-Schloer, H. Schmeck, T. Ungerer
(Eds.), Organic Computing---A Paradigm Shift for Complex Systems, Springer Basel,
2011, pp. 193–206.'
date_created: 2019-07-10T11:28:12Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
editor:
- first_name: Christian
full_name: Müller-Schloer, Christian
last_name: Müller-Schloer
- first_name: Hartmut
full_name: Schmeck, Hartmut
last_name: Schmeck
- first_name: Theo
full_name: Ungerer, Theo
last_name: Ungerer
intvolume: ' 1'
language:
- iso: eng
page: 193-206
publication: Organic Computing---A Paradigm Shift for Complex Systems
publisher: Springer Basel
series_title: Autonomic Systems
status: public
title: Multi-objective Intrinsic Evolution of Embedded Systems
type: book_chapter
user_id: '3118'
volume: 1
year: '2011'
...
---
_id: '10736'
author:
- first_name: Arne
full_name: Schwabe, Arne
last_name: Schwabe
citation:
ama: Schwabe A. Analysis of Algorithmic Approaches for Temporal Partitioning.
Paderborn University; 2011.
apa: Schwabe, A. (2011). Analysis of Algorithmic Approaches for Temporal Partitioning.
Paderborn University.
bibtex: '@book{Schwabe_2011, title={Analysis of Algorithmic Approaches for Temporal
Partitioning}, publisher={Paderborn University}, author={Schwabe, Arne}, year={2011}
}'
chicago: Schwabe, Arne. Analysis of Algorithmic Approaches for Temporal Partitioning.
Paderborn University, 2011.
ieee: A. Schwabe, Analysis of Algorithmic Approaches for Temporal Partitioning.
Paderborn University, 2011.
mla: Schwabe, Arne. Analysis of Algorithmic Approaches for Temporal Partitioning.
Paderborn University, 2011.
short: A. Schwabe, Analysis of Algorithmic Approaches for Temporal Partitioning,
Paderborn University, 2011.
date_created: 2019-07-10T11:58:10Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Analysis of Algorithmic Approaches for Temporal Partitioning
type: mastersthesis
user_id: '3118'
year: '2011'
...
---
_id: '10737'
author:
- first_name: Lukas
full_name: Sekanina, Lukas
last_name: Sekanina
- first_name: James Alfred
full_name: Walker, James Alfred
last_name: Walker
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic
Circuits. In: Cartesian Genetic Programming. Natural Computing Series.
Springer Berlin Heidelberg; 2011:125-179.'
apa: Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., & Platzner, M. (2011).
Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp.
125–179). Springer Berlin Heidelberg.
bibtex: '@inbook{Sekanina_Walker_Kaufmann_Plessl_Platzner_2011, series={Natural
Computing Series}, title={Evolution of Electronic Circuits}, booktitle={Cartesian
Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Sekanina,
Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner,
Marco}, year={2011}, pages={125–179}, collection={Natural Computing Series} }'
chicago: Sekanina, Lukas, James Alfred Walker, Paul Kaufmann, Christian Plessl,
and Marco Platzner. “Evolution of Electronic Circuits.” In Cartesian Genetic
Programming, 125–79. Natural Computing Series. Springer Berlin Heidelberg,
2011.
ieee: L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution
of Electronic Circuits,” in Cartesian Genetic Programming, Springer Berlin
Heidelberg, 2011, pp. 125–179.
mla: Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” Cartesian Genetic
Programming, Springer Berlin Heidelberg, 2011, pp. 125–79.
short: 'L. Sekanina, J.A. Walker, P. Kaufmann, C. Plessl, M. Platzner, in: Cartesian
Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.'
date_created: 2019-07-10T11:59:35Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
- _id: '518'
language:
- iso: eng
page: 125-179
publication: Cartesian Genetic Programming
publisher: Springer Berlin Heidelberg
series_title: Natural Computing Series
status: public
title: Evolution of Electronic Circuits
type: book_chapter
user_id: '3118'
year: '2011'
...
---
_id: '10748'
author:
- first_name: James Alfred
full_name: Walker, James Alfred
last_name: Walker
- first_name: Julian F.
full_name: Miller, Julian F.
last_name: Miller
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Walker JA, Miller JF, Kaufmann P, Platzner M. Problem Decomposition in Cartesian
Genetic Programming. In: Cartesian Genetic Programming. Natural Computing
Series. Springer Berlin Heidelberg; 2011:35-99.'
apa: Walker, J. A., Miller, J. F., Kaufmann, P., & Platzner, M. (2011). Problem
Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming
(pp. 35–99). Springer Berlin Heidelberg.
bibtex: '@inbook{Walker_Miller_Kaufmann_Platzner_2011, series={Natural Computing
Series}, title={Problem Decomposition in Cartesian Genetic Programming}, booktitle={Cartesian
Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Walker,
James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}, year={2011},
pages={35–99}, collection={Natural Computing Series} }'
chicago: Walker, James Alfred, Julian F. Miller, Paul Kaufmann, and Marco Platzner.
“Problem Decomposition in Cartesian Genetic Programming.” In Cartesian Genetic
Programming, 35–99. Natural Computing Series. Springer Berlin Heidelberg,
2011.
ieee: J. A. Walker, J. F. Miller, P. Kaufmann, and M. Platzner, “Problem Decomposition
in Cartesian Genetic Programming,” in Cartesian Genetic Programming, Springer
Berlin Heidelberg, 2011, pp. 35–99.
mla: Walker, James Alfred, et al. “Problem Decomposition in Cartesian Genetic Programming.”
Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.
short: 'J.A. Walker, J.F. Miller, P. Kaufmann, M. Platzner, in: Cartesian Genetic
Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.'
date_created: 2019-07-10T12:02:57Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: 35-99
publication: Cartesian Genetic Programming
publisher: Springer Berlin Heidelberg
series_title: Natural Computing Series
status: public
title: Problem Decomposition in Cartesian Genetic Programming
type: book_chapter
user_id: '3118'
year: '2011'
...
---
_id: '10750'
author:
- first_name: Daniel
full_name: Welp, Daniel
last_name: Welp
citation:
ama: Welp D. User Space Scheduling for Heterogeneous Systems. Paderborn University;
2011.
apa: Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn
University.
bibtex: '@book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems},
publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }'
chicago: Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn
University, 2011.
ieee: D. Welp, User Space Scheduling for Heterogeneous Systems. Paderborn
University, 2011.
mla: Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn
University, 2011.
short: D. Welp, User Space Scheduling for Heterogeneous Systems, Paderborn University,
2011.
date_created: 2019-07-10T12:03:00Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: User Space Scheduling for Heterogeneous Systems
type: mastersthesis
user_id: '3118'
year: '2011'
...
---
_id: '13643'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
citation:
ama: 'Agne A, Platzner M, Lübbers E. Memory Virtualization for Multithreaded Reconfigurable
Hardware. In: Proceedings of the International Conference on Field Programmable
Logic and Applications (FPL). IEEE; 2011:185-188. doi:10.1109/fpl.2011.42'
apa: Agne, A., Platzner, M., & Lübbers, E. (2011). Memory Virtualization for
Multithreaded Reconfigurable Hardware. In Proceedings of the International
Conference on Field Programmable Logic and Applications (FPL) (pp. 185–188).
IEEE. https://doi.org/10.1109/fpl.2011.42
bibtex: '@inproceedings{Agne_Platzner_Lübbers_2011, title={Memory Virtualization
for Multithreaded Reconfigurable Hardware}, DOI={10.1109/fpl.2011.42},
booktitle={Proceedings of the International Conference on Field Programmable Logic
and Applications (FPL)}, publisher={IEEE}, author={Agne, Andreas and Platzner,
Marco and Lübbers, Enno}, year={2011}, pages={185–188} }'
chicago: Agne, Andreas, Marco Platzner, and Enno Lübbers. “Memory Virtualization
for Multithreaded Reconfigurable Hardware.” In Proceedings of the International
Conference on Field Programmable Logic and Applications (FPL), 185–88. IEEE,
2011. https://doi.org/10.1109/fpl.2011.42.
ieee: A. Agne, M. Platzner, and E. Lübbers, “Memory Virtualization for Multithreaded
Reconfigurable Hardware,” in Proceedings of the International Conference on
Field Programmable Logic and Applications (FPL), 2011, pp. 185–188.
mla: Agne, Andreas, et al. “Memory Virtualization for Multithreaded Reconfigurable
Hardware.” Proceedings of the International Conference on Field Programmable
Logic and Applications (FPL), IEEE, 2011, pp. 185–88, doi:10.1109/fpl.2011.42.
short: 'A. Agne, M. Platzner, E. Lübbers, in: Proceedings of the International Conference
on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–188.'
date_created: 2019-10-04T22:42:51Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpl.2011.42
language:
- iso: eng
page: 185-188
publication: Proceedings of the International Conference on Field Programmable Logic
and Applications (FPL)
publication_identifier:
isbn:
- '9781457714849'
publication_status: published
publisher: IEEE
status: public
title: Memory Virtualization for Multithreaded Reconfigurable Hardware
type: conference
user_id: '398'
year: '2011'
...
---
_id: '13644'
author:
- first_name: Jörg
full_name: Henkel, Jörg
last_name: Henkel
- first_name: Lars
full_name: Hedrich, Lars
last_name: Hedrich
- first_name: Andreas
full_name: Herkersdorf, Andreas
last_name: Herkersdorf
- first_name: Rüdiger
full_name: Kapitza, Rüdiger
last_name: Kapitza
- first_name: Daniel
full_name: Lohmann, Daniel
last_name: Lohmann
- first_name: Peter
full_name: Marwedel, Peter
last_name: Marwedel
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
- first_name: Wolfgang
full_name: Rosenstiel, Wolfgang
last_name: Rosenstiel
- first_name: Ulf
full_name: Schlichtmann, Ulf
last_name: Schlichtmann
- first_name: Olaf
full_name: Spinczyk, Olaf
last_name: Spinczyk
- first_name: Mehdi
full_name: Tahoori, Mehdi
last_name: Tahoori
- first_name: Lars
full_name: Bauer, Lars
last_name: Bauer
- first_name: Jürgen
full_name: Teich, Jürgen
last_name: Teich
- first_name: Norbert
full_name: Wehn, Norbert
last_name: Wehn
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Joachim
full_name: Becker, Joachim
last_name: Becker
- first_name: Oliver
full_name: Bringmann, Oliver
last_name: Bringmann
- first_name: Uwe
full_name: Brinkschulte, Uwe
last_name: Brinkschulte
- first_name: Samarjit
full_name: Chakraborty, Samarjit
last_name: Chakraborty
- first_name: Michael
full_name: Engel, Michael
last_name: Engel
- first_name: Rolf
full_name: Ernst, Rolf
last_name: Ernst
- first_name: Hermann
full_name: Härtig, Hermann
last_name: Härtig
citation:
ama: 'Henkel J, Hedrich L, Herkersdorf A, et al. Design and architectures for dependable
embedded systems. In: Proceedings of the Seventh IEEE/ACM/IFIP International
Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11.
; 2011. doi:10.1145/2039370.2039384'
apa: Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel,
P., … Härtig, H. (2011). Design and architectures for dependable embedded systems.
In Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software
Codesign and system synthesis - CODES+ISSS ’11. https://doi.org/10.1145/2039370.2039384
bibtex: '@inproceedings{Henkel_Hedrich_Herkersdorf_Kapitza_Lohmann_Marwedel_Platzner_Rosenstiel_Schlichtmann_Spinczyk_et
al._2011, title={Design and architectures for dependable embedded systems}, DOI={10.1145/2039370.2039384}, booktitle={Proceedings
of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign
and system synthesis - CODES+ISSS ’11}, author={Henkel, Jörg and Hedrich, Lars
and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel,
Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk,
Olaf and et al.}, year={2011} }'
chicago: Henkel, Jörg, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel
Lohmann, Peter Marwedel, Marco Platzner, et al. “Design and Architectures for
Dependable Embedded Systems.” In Proceedings of the Seventh IEEE/ACM/IFIP International
Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11,
2011. https://doi.org/10.1145/2039370.2039384.
ieee: J. Henkel et al., “Design and architectures for dependable embedded
systems,” in Proceedings of the seventh IEEE/ACM/IFIP International Conference
on Hardware/software Codesign and system synthesis - CODES+ISSS ’11, 2011.
mla: Henkel, Jörg, et al. “Design and Architectures for Dependable Embedded Systems.”
Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software
Codesign and System Synthesis - CODES+ISSS ’11, 2011, doi:10.1145/2039370.2039384.
short: 'J. Henkel, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel,
M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, L. Bauer,
J. Teich, N. Wehn, H.-J. Wunderlich, J. Becker, O. Bringmann, U. Brinkschulte,
S. Chakraborty, M. Engel, R. Ernst, H. Härtig, in: Proceedings of the Seventh
IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System
Synthesis - CODES+ISSS ’11, 2011.'
date_created: 2019-10-04T22:44:36Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1145/2039370.2039384
language:
- iso: eng
publication: Proceedings of the seventh IEEE/ACM/IFIP International Conference on
Hardware/software Codesign and system synthesis - CODES+ISSS '11
publication_identifier:
isbn:
- '9781450307154'
publication_status: published
status: public
title: Design and architectures for dependable embedded systems
type: conference
user_id: '398'
year: '2011'
...
---
_id: '2194'
author:
- first_name: Björn
full_name: Meyer, Björn
last_name: Meyer
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: 'Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to
parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp.
on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer
Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12'
apa: 'Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific
algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend.
Symp. on Application Accelerators in High Performance Computing (SAAHPC),
60–63. https://doi.org/10.1109/SAAHPC.2011.12'
bibtex: '@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific
algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend},
DOI={10.1109/SAAHPC.2011.12},
booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)},
publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian
and Förstner, Jens}, year={2011}, pages={60–63} }'
chicago: 'Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of
Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU
Backend.” In Symp. on Application Accelerators in High Performance Computing
(SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.'
ieee: 'B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms
to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in
Symp. on Application Accelerators in High Performance Computing (SAAHPC),
2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.'
mla: 'Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel
Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application
Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society,
2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.'
short: 'B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators
in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.'
date_created: 2018-04-03T14:55:57Z
date_updated: 2023-09-26T13:44:11Z
department:
- _id: '27'
- _id: '518'
- _id: '15'
- _id: '78'
doi: 10.1109/SAAHPC.2011.12
keyword:
- tet_topic_hpc
language:
- iso: eng
page: 60-63
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Symp. on Application Accelerators in High Performance Computing (SAAHPC)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'Transformation of scientific algorithms to parallel computing code: subdomain
support in a MPI-multi-GPU backend'
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2193'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for
heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273'
apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative
multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler.
Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273
bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative
multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler},
DOI={10.1109/ASAP.2011.6043273},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011},
pages={223–226} }'
chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann.
“Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely
Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures,
and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.
ieee: 'T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking
for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP),
2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.'
mla: Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators
in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011,
pp. 223–26, doi:10.1109/ASAP.2011.6043273.
short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on
Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer
Society, 2011, pp. 223–226.'
date_created: 2018-04-03T14:37:14Z
date_updated: 2023-09-26T13:43:48Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2011.6043273
language:
- iso: eng
page: 223-226
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Cooperative multitasking for heterogeneous accelerators in the Linux Completely
Fair Scheduler
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '656'
abstract:
- lang: eng
text: In the next decades, hybrid multi-cores will be the predominant architecture
for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies
are key for providing dependability in such systems. These strategies rely on
measuring the temperature distribution and redicting the thermal behavior of the
system when there are changes to the hardware and software running on the FPGA.
While there are a number of tools that use thermal models to predict temperature
distributions at design time, these tools lack the flexibility to autonomously
adjust to changing FPGA configurations. To address this problem we propose a temperature-aware
system that empowers FPGA-based reconfigurable multi-cores to autonomously predict
the on-chip temperature distribution for pro-active thread remapping. Our system
obtains temperature measurements through a self-calibrating grid of sensors and
uses area constrained heat-generating circuits in order to generate spatial and
temporal temperature gradients. The generated temperature variations are then
used to learn the free parameters of the system's thermal model. The system thus
acquires an understanding of its own thermal characteristics. We implemented an
FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T
FPGA that is aware of its thermal model. Finally, we show that the temperature
predictions vary less than 0.72 degree C on average compared to the measured temperature
distributions at run-time.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions
on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59'
apa: Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature
Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59
bibtex: '@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting
Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59},
booktitle={Proceedings of the 2011 International Conference on Reconfigurable
Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne,
Andreas and Plessl, Christian}, year={2011}, pages={55–60} }'
chicago: Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting
Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011
International Conference on Reconfigurable Computing and FPGAs (ReConFig),
55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.
ieee: 'M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions
on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.'
mla: Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on
FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable
Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.
short: 'M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International
Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.'
date_created: 2017-10-17T12:42:59Z
date_updated: 2023-09-26T13:46:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2011.59
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-14T13:49:39Z
date_updated: 2018-03-14T13:49:39Z
file_id: '1220'
file_name: 656-2011_happe_reconfig.pdf
file_size: 502244
relation: main_file
success: 1
file_date_updated: 2018-03-14T13:49:39Z
has_accepted_license: '1'
language:
- iso: eng
page: 55-60
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the 2011 International Conference on Reconfigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Measuring and Predicting Temperature Distributions on FPGAs at Run-Time
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2200'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int.
Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance
Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures}, DOI={10.1145/1950413.1950448},
booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
Michael}, year={2011}, pages={177–180} }'
chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA),
177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.'
ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc.
Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:
10.1145/1950413.1950448.'
mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate
Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
isbn:
- 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2201'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound
Streaming Applications: Architecture Modeling and a 3D Image Compositing Case
Study. Int Journal of Recon- figurable Computing (IJRC). Published online
2011. doi:10.1155/2011/760954'
apa: 'Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration
of Communication-bound Streaming Applications: Architecture Modeling and a 3D
Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).
https://doi.org/10.1155/2011/760954'
bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration
of Communication-bound Streaming Applications: Architecture Modeling and a 3D
Image Compositing Case Study}, DOI={10.1155/2011/760954},
journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi
Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian
and Platzner, Marco}, year={2011} }'
chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA
Acceleration of Communication-Bound Streaming Applications: Architecture Modeling
and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing
(IJRC), 2011. https://doi.org/10.1155/2011/760954.'
ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of
Communication-bound Streaming Applications: Architecture Modeling and a 3D Image
Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC),
2011, doi: 10.1155/2011/760954.'
mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming
Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int.
Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011,
doi:10.1155/2011/760954.'
short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable
Computing (IJRC) (2011).
date_created: 2018-04-03T15:09:49Z
date_updated: 2023-09-26T13:45:46Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2011/760954
keyword:
- funding-altera
language:
- iso: eng
publication: Int. Journal of Recon- figurable Computing (IJRC)
publisher: Hindawi Publishing Corp.
quality_controlled: '1'
status: public
title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture
Modeling and a 3D Image Compositing Case Study'
type: journal_article
user_id: '15278'
year: '2011'
...
---
_id: '2198'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and
Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable
Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153'
apa: Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension –
Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture.
Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153
bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension
– Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture},
DOI={10.1109/IPDPS.2011.153},
booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE
Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011},
pages={278–285} }'
chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
– Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer
Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.
ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility
and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc.
Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.'
mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
– Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society,
2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.
short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW),
IEEE Computer Society, 2011, pp. 278–285.'
date_created: 2018-04-03T15:05:52Z
date_updated: 2023-09-26T13:44:39Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/IPDPS.2011.153
language:
- iso: eng
page: 278-285
publication: Proc. Reconfigurable Architectures Workshop (RAW)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an
FPGA-based Reconfigurable ASIP Architecture
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '10605'
author:
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
- first_name: Uwe
full_name: Kastens, Uwe
last_name: Kastens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and
Prototype Tool Flow for Online Verification. International Journal of Reconfigurable
Computing. 2010;2010. doi:10.1155/2010/180242'
apa: 'Drzevitzky, S., Kastens, U., & Platzner, M. (2010). Proof-Carrying Hardware:
Concept and Prototype Tool Flow for Online Verification. International Journal
of Reconfigurable Computing, 2010. https://doi.org/10.1155/2010/180242'
bibtex: '@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware:
Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={10.1155/2010/180242}, journal={International
Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation},
author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010}
}'
chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying
Hardware: Concept and Prototype Tool Flow for Online Verification.” International
Journal of Reconfigurable Computing 2010 (2010). https://doi.org/10.1155/2010/180242.'
ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept
and Prototype Tool Flow for Online Verification,” International Journal of
Reconfigurable Computing, vol. 2010, 2010.'
mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype
Tool Flow for Online Verification.” International Journal of Reconfigurable
Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242.'
short: S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable
Computing 2010 (2010).
date_created: 2019-07-10T09:22:56Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1155/2010/180242
intvolume: ' 2010'
language:
- iso: eng
publication: International Journal of Reconfigurable Computing
publisher: Hindawi Publishing Corporation
status: public
title: 'Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification'
type: journal_article
user_id: '3118'
volume: 2010
year: '2010'
...
---
_id: '10614'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
citation:
ama: Agne A. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
Systemen. Paderborn University; 2010.
apa: Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren
Systemen. Paderborn University.
bibtex: '@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads
in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne,
Andreas}, year={2010} }'
chicago: Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in
Rekonfigurierbaren Systemen. Paderborn University, 2010.
ieee: A. Agne, Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren
Systemen. Paderborn University, 2010.
mla: Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
Systemen. Paderborn University, 2010.
short: A. Agne, Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
Systemen, Paderborn University, 2010.
date_created: 2019-07-10T09:25:12Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10629'
alternative_title:
- EMG-based Gait Analysis
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
citation:
ama: Boschmann A. EMG-Basierte Ganganalyse. Paderborn University; 2010.
apa: Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University.
bibtex: '@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn
University}, author={Boschmann, Alexander}, year={2010} }'
chicago: Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University,
2010.
ieee: A. Boschmann, EMG-basierte Ganganalyse. Paderborn University, 2010.
mla: Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University,
2010.
short: A. Boschmann, EMG-Basierte Ganganalyse, Paderborn University, 2010.
date_created: 2019-07-10T09:40:27Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: EMG-basierte Ganganalyse
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10642'
author:
- first_name: Daniel
full_name: Breitlauch, Daniel
last_name: Breitlauch
citation:
ama: Breitlauch D. Evolvable Cache Controller. Paderborn University; 2010.
apa: Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University.
bibtex: '@book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn
University}, author={Breitlauch, Daniel}, year={2010} }'
chicago: Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University,
2010.
ieee: D. Breitlauch, Evolvable Cache Controller. Paderborn University, 2010.
mla: Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University,
2010.
short: D. Breitlauch, Evolvable Cache Controller, Paderborn University, 2010.
date_created: 2019-07-10T11:03:43Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
title: Evolvable Cache Controller
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10649'
author:
- first_name: Denis
full_name: Dridger, Denis
last_name: Dridger
citation:
ama: Dridger D. Soft Microprocessors with Tightly Coupled Application-Specific
Coprocessors. Paderborn University; 2010.
apa: Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific
Coprocessors. Paderborn University.
bibtex: '@book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific
Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010}
}'
chicago: Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific
Coprocessors. Paderborn University, 2010.
ieee: D. Dridger, Soft Microprocessors with tightly coupled Application-Specific
Coprocessors. Paderborn University, 2010.
mla: Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific
Coprocessors. Paderborn University, 2010.
short: D. Dridger, Soft Microprocessors with Tightly Coupled Application-Specific
Coprocessors, Paderborn University, 2010.
date_created: 2019-07-10T11:10:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Soft Microprocessors with tightly coupled Application-Specific Coprocessors
type: bachelorsthesis
user_id: '3118'
year: '2010'
...