---
_id: '2200'
author:
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Michael
  full_name: Kauschke, Michael
  last_name: Kauschke
citation:
  ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
    for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int.
    Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a
    href="https://doi.org/10.1145/1950413.1950448">10.1145/1950413.1950448</a>'
  apa: Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance
    Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
    <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a
    href="https://doi.org/10.1145/1950413.1950448">https://doi.org/10.1145/1950413.1950448</a>
  bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
    USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
    Architectures}, DOI={<a href="https://doi.org/10.1145/1950413.1950448">10.1145/1950413.1950448</a>},
    booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
    author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
    Michael}, year={2011}, pages={177–180} }'
  chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
    “Performance Estimation Framework for Automated Exploration of CPU-Accelerator
    Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>,
    177–80. New York, NY, USA: ACM, 2011. <a href="https://doi.org/10.1145/1950413.1950448">https://doi.org/10.1145/1950413.1950448</a>.'
  ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
    Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc.
    Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi:
    <a href="https://doi.org/10.1145/1950413.1950448">10.1145/1950413.1950448</a>.'
  mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
    of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate
    Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href="https://doi.org/10.1145/1950413.1950448">10.1145/1950413.1950448</a>.
  short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
    Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
  isbn:
  - 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
  Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2201'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Tim
  full_name: Süß, Tim
  last_name: Süß
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound
    Streaming Applications: Architecture Modeling and a 3D Image Compositing Case
    Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online
    2011. doi:<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>'
  apa: 'Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration
    of Communication-bound Streaming Applications: Architecture Modeling and a 3D
    Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>.
    <a href="https://doi.org/10.1155/2011/760954">https://doi.org/10.1155/2011/760954</a>'
  bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration
    of Communication-bound Streaming Applications: Architecture Modeling and a 3D
    Image Compositing Case Study}, DOI={<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>},
    journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi
    Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian
    and Platzner, Marco}, year={2011} }'
  chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA
    Acceleration of Communication-Bound Streaming Applications: Architecture Modeling
    and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing
    (IJRC)</i>, 2011. <a href="https://doi.org/10.1155/2011/760954">https://doi.org/10.1155/2011/760954</a>.'
  ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of
    Communication-bound Streaming Applications: Architecture Modeling and a 3D Image
    Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>,
    2011, doi: <a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>.'
  mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming
    Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int.
    Journal of Recon- Figurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2011,
    doi:<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>.'
  short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable
    Computing (IJRC) (2011).
date_created: 2018-04-03T15:09:49Z
date_updated: 2023-09-26T13:45:46Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2011/760954
keyword:
- funding-altera
language:
- iso: eng
publication: Int. Journal of Recon- figurable Computing (IJRC)
publisher: Hindawi Publishing Corp.
quality_controlled: '1'
status: public
title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture
  Modeling and a 3D Image Compositing Case Study'
type: journal_article
user_id: '15278'
year: '2011'
...
---
_id: '2198'
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and
    Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: <i>Proc. Reconfigurable
    Architectures Workshop (RAW)</i>. IEEE Computer Society; 2011:278-285. doi:<a
    href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>'
  apa: Grad, M., &#38; Plessl, C. (2011). Just-in-time Instruction Set Extension –
    Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture.
    <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–285. <a href="https://doi.org/10.1109/IPDPS.2011.153">https://doi.org/10.1109/IPDPS.2011.153</a>
  bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture},
    DOI={<a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>},
    booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE
    Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011},
    pages={278–285} }'
  chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
    In <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–85. IEEE Computer
    Society, 2011. <a href="https://doi.org/10.1109/IPDPS.2011.153">https://doi.org/10.1109/IPDPS.2011.153</a>.
  ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility
    and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in <i>Proc.
    Reconfigurable Architectures Workshop (RAW)</i>, 2011, pp. 278–285, doi: <a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>.'
  mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
    <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, IEEE Computer Society,
    2011, pp. 278–85, doi:<a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>.
  short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW),
    IEEE Computer Society, 2011, pp. 278–285.'
date_created: 2018-04-03T15:05:52Z
date_updated: 2023-09-26T13:44:39Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/IPDPS.2011.153
language:
- iso: eng
page: 278-285
publication: Proc. Reconfigurable Architectures Workshop (RAW)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an
  FPGA-based Reconfigurable ASIP Architecture
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '10605'
author:
- first_name: Stephanie
  full_name: Drzevitzky, Stephanie
  last_name: Drzevitzky
- first_name: Uwe
  full_name: Kastens, Uwe
  last_name: Kastens
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and
    Prototype Tool Flow for Online Verification. <i>International Journal of Reconfigurable
    Computing</i>. 2010;2010. doi:<a href="https://doi.org/10.1155/2010/180242">10.1155/2010/180242</a>'
  apa: 'Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2010). Proof-Carrying Hardware:
    Concept and Prototype Tool Flow for Online Verification. <i>International Journal
    of Reconfigurable Computing</i>, <i>2010</i>. <a href="https://doi.org/10.1155/2010/180242">https://doi.org/10.1155/2010/180242</a>'
  bibtex: '@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware:
    Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={<a
    href="https://doi.org/10.1155/2010/180242">10.1155/2010/180242</a>}, journal={International
    Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation},
    author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010}
    }'
  chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying
    Hardware: Concept and Prototype Tool Flow for Online Verification.” <i>International
    Journal of Reconfigurable Computing</i> 2010 (2010). <a href="https://doi.org/10.1155/2010/180242">https://doi.org/10.1155/2010/180242</a>.'
  ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept
    and Prototype Tool Flow for Online Verification,” <i>International Journal of
    Reconfigurable Computing</i>, vol. 2010, 2010.'
  mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype
    Tool Flow for Online Verification.” <i>International Journal of Reconfigurable
    Computing</i>, vol. 2010, Hindawi Publishing Corporation, 2010, doi:<a href="https://doi.org/10.1155/2010/180242">10.1155/2010/180242</a>.'
  short: S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable
    Computing 2010 (2010).
date_created: 2019-07-10T09:22:56Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1155/2010/180242
intvolume: '      2010'
language:
- iso: eng
publication: International Journal of Reconfigurable Computing
publisher: Hindawi Publishing Corporation
status: public
title: 'Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification'
type: journal_article
user_id: '3118'
volume: 2010
year: '2010'
...
---
_id: '10614'
author:
- first_name: Andreas
  full_name: Agne, Andreas
  last_name: Agne
citation:
  ama: Agne A. <i>Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
    Systemen</i>. Paderborn University; 2010.
  apa: Agne, A. (2010). <i>Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren
    Systemen</i>. Paderborn University.
  bibtex: '@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads
    in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne,
    Andreas}, year={2010} }'
  chicago: Agne, Andreas. <i>Virtuelle Speicherverwaltung Für Hardware Threads in
    Rekonfigurierbaren Systemen</i>. Paderborn University, 2010.
  ieee: A. Agne, <i>Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren
    Systemen</i>. Paderborn University, 2010.
  mla: Agne, Andreas. <i>Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
    Systemen</i>. Paderborn University, 2010.
  short: A. Agne, Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren
    Systemen, Paderborn University, 2010.
date_created: 2019-07-10T09:25:12Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10629'
alternative_title:
- EMG-based Gait Analysis
author:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
citation:
  ama: Boschmann A. <i>EMG-Basierte Ganganalyse</i>. Paderborn University; 2010.
  apa: Boschmann, A. (2010). <i>EMG-basierte Ganganalyse</i>. Paderborn University.
  bibtex: '@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn
    University}, author={Boschmann, Alexander}, year={2010} }'
  chicago: Boschmann, Alexander. <i>EMG-Basierte Ganganalyse</i>. Paderborn University,
    2010.
  ieee: A. Boschmann, <i>EMG-basierte Ganganalyse</i>. Paderborn University, 2010.
  mla: Boschmann, Alexander. <i>EMG-Basierte Ganganalyse</i>. Paderborn University,
    2010.
  short: A. Boschmann, EMG-Basierte Ganganalyse, Paderborn University, 2010.
date_created: 2019-07-10T09:40:27Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: EMG-basierte Ganganalyse
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10642'
author:
- first_name: Daniel
  full_name: Breitlauch, Daniel
  last_name: Breitlauch
citation:
  ama: Breitlauch D. <i>Evolvable Cache Controller</i>. Paderborn University; 2010.
  apa: Breitlauch, D. (2010). <i>Evolvable Cache Controller</i>. Paderborn University.
  bibtex: '@book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn
    University}, author={Breitlauch, Daniel}, year={2010} }'
  chicago: Breitlauch, Daniel. <i>Evolvable Cache Controller</i>. Paderborn University,
    2010.
  ieee: D. Breitlauch, <i>Evolvable Cache Controller</i>. Paderborn University, 2010.
  mla: Breitlauch, Daniel. <i>Evolvable Cache Controller</i>. Paderborn University,
    2010.
  short: D. Breitlauch, Evolvable Cache Controller, Paderborn University, 2010.
date_created: 2019-07-10T11:03:43Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Evolvable Cache Controller
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10649'
author:
- first_name: Denis
  full_name: Dridger, Denis
  last_name: Dridger
citation:
  ama: Dridger D. <i>Soft Microprocessors with Tightly Coupled Application-Specific
    Coprocessors</i>. Paderborn University; 2010.
  apa: Dridger, D. (2010). <i>Soft Microprocessors with tightly coupled Application-Specific
    Coprocessors</i>. Paderborn University.
  bibtex: '@book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific
    Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010}
    }'
  chicago: Dridger, Denis. <i>Soft Microprocessors with Tightly Coupled Application-Specific
    Coprocessors</i>. Paderborn University, 2010.
  ieee: D. Dridger, <i>Soft Microprocessors with tightly coupled Application-Specific
    Coprocessors</i>. Paderborn University, 2010.
  mla: Dridger, Denis. <i>Soft Microprocessors with Tightly Coupled Application-Specific
    Coprocessors</i>. Paderborn University, 2010.
  short: D. Dridger, Soft Microprocessors with Tightly Coupled Application-Specific
    Coprocessors, Paderborn University, 2010.
date_created: 2019-07-10T11:10:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Soft Microprocessors with tightly coupled Application-Specific Coprocessors
type: bachelorsthesis
user_id: '3118'
year: '2010'
...
---
_id: '10657'
author:
- first_name: Tobias
  full_name: Graf, Tobias
  last_name: Graf
citation:
  ama: Graf T. <i>Parallelization of the UCT Algorithm on HPC-Clusters</i>. Paderborn
    University; 2010.
  apa: Graf, T. (2010). <i>Parallelization of the UCT Algorithm on HPC-Clusters</i>.
    Paderborn University.
  bibtex: '@book{Graf_2010, title={Parallelization of the UCT Algorithm on HPC-Clusters},
    publisher={Paderborn University}, author={Graf, Tobias}, year={2010} }'
  chicago: Graf, Tobias. <i>Parallelization of the UCT Algorithm on HPC-Clusters</i>.
    Paderborn University, 2010.
  ieee: T. Graf, <i>Parallelization of the UCT Algorithm on HPC-Clusters</i>. Paderborn
    University, 2010.
  mla: Graf, Tobias. <i>Parallelization of the UCT Algorithm on HPC-Clusters</i>.
    Paderborn University, 2010.
  short: T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters, Paderborn
    University, 2010.
date_created: 2019-07-10T11:13:33Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Parallelization of the UCT Algorithm on HPC-Clusters
type: bachelorsthesis
user_id: '3118'
year: '2010'
...
---
_id: '10683'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Kevin
  full_name: Englehart, Kevin
  last_name: Englehart
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Englehart K, Platzner M. Fluctuating EMG Signals: Investigating
    Long-term Effects of Pattern Matching Algorithms. In: <i>International Conference
    of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>. IEEE; 2010:6357-6360.'
  apa: 'Kaufmann, P., Englehart, K., &#38; Platzner, M. (2010). Fluctuating EMG Signals:
    Investigating Long-term Effects of Pattern Matching Algorithms. In <i>International
    Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>
    (pp. 6357–6360). IEEE.'
  bibtex: '@inproceedings{Kaufmann_Englehart_Platzner_2010, title={Fluctuating EMG
    Signals: Investigating Long-term Effects of Pattern Matching Algorithms}, booktitle={International
    Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}, publisher={IEEE},
    author={Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}, year={2010},
    pages={6357–6360} }'
  chicago: 'Kaufmann, Paul, Kevin Englehart, and Marco Platzner. “Fluctuating EMG
    Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” In <i>International
    Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>,
    6357–60. IEEE, 2010.'
  ieee: 'P. Kaufmann, K. Englehart, and M. Platzner, “Fluctuating EMG Signals: Investigating
    Long-term Effects of Pattern Matching Algorithms,” in <i>International Conference
    of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>, 2010, pp.
    6357–6360.'
  mla: 'Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects
    of Pattern Matching Algorithms.” <i>International Conference of the IEEE Engineering
    in Medicine and Biology Society (EMBC)</i>, IEEE, 2010, pp. 6357–60.'
  short: 'P. Kaufmann, K. Englehart, M. Platzner, in: International Conference of
    the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–6360.'
date_created: 2019-07-10T11:27:27Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 6357-6360
publication: International Conference of the IEEE Engineering in Medicine and Biology
  Society (EMBC)
publisher: IEEE
status: public
title: 'Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching
  Algorithms'
type: conference
user_id: '3118'
year: '2010'
...
---
_id: '10686'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Tobias
  full_name: Knieper, Tobias
  last_name: Knieper
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Knieper T, Platzner M. A Novel Hybrid Evolutionary Strategy and
    its Periodization with Multi-objective Genetic Optimizers. In: <i>IEEE World Congress
    on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>.
    IEEE; 2010:541-548.'
  apa: Kaufmann, P., Knieper, T., &#38; Platzner, M. (2010). A Novel Hybrid Evolutionary
    Strategy and its Periodization with Multi-objective Genetic Optimizers. In <i>IEEE
    World Congress on Computational Intelligence (WCCI), Congress on Evolutionary
    Computation (CEC)</i> (pp. 541–548). IEEE.
  bibtex: '@inproceedings{Kaufmann_Knieper_Platzner_2010, title={A Novel Hybrid Evolutionary
    Strategy and its Periodization with Multi-objective Genetic Optimizers}, booktitle={IEEE
    World Congress on Computational Intelligence (WCCI), Congress on Evolutionary
    Computation (CEC)}, publisher={IEEE}, author={Kaufmann, Paul and Knieper, Tobias
    and Platzner, Marco}, year={2010}, pages={541–548} }'
  chicago: Kaufmann, Paul, Tobias Knieper, and Marco Platzner. “A Novel Hybrid Evolutionary
    Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” In <i>IEEE
    World Congress on Computational Intelligence (WCCI), Congress on Evolutionary
    Computation (CEC)</i>, 541–48. IEEE, 2010.
  ieee: P. Kaufmann, T. Knieper, and M. Platzner, “A Novel Hybrid Evolutionary Strategy
    and its Periodization with Multi-objective Genetic Optimizers,” in <i>IEEE World
    Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation
    (CEC)</i>, 2010, pp. 541–548.
  mla: Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization
    with Multi-Objective Genetic Optimizers.” <i>IEEE World Congress on Computational
    Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>, IEEE, 2010,
    pp. 541–48.
  short: 'P. Kaufmann, T. Knieper, M. Platzner, in: IEEE World Congress on Computational
    Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp.
    541–548.'
date_created: 2019-07-10T11:28:11Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 541-548
publication: IEEE World Congress on Computational Intelligence (WCCI), Congress on
  Evolutionary Computation (CEC)
publisher: IEEE
status: public
title: A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective
  Genetic Optimizers
type: conference
user_id: '3118'
year: '2010'
...
---
_id: '10694'
author:
- first_name: Udo
  full_name: Kebschull, Udo
  last_name: Kebschull
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Jürgen
  full_name: Teich, Jürgen
  last_name: Teich
citation:
  ama: Kebschull U, Platzner M, Teich J. Selected papers from the 18th International
    Conference on Field Programmable Logic and Applications, FPL 2008 (editorial).
    <i>IET Computers Digital Techniques</i>. 2010;4(3):157-158. doi:<a href="https://doi.org/10.1049/iet-cdt.2010.9044">10.1049/iet-cdt.2010.9044</a>
  apa: Kebschull, U., Platzner, M., &#38; Teich, J. (2010). Selected papers from the
    18th International Conference on Field Programmable Logic and Applications, FPL
    2008 (editorial). <i>IET Computers Digital Techniques</i>, <i>4</i>(3), 157–158.
    <a href="https://doi.org/10.1049/iet-cdt.2010.9044">https://doi.org/10.1049/iet-cdt.2010.9044</a>
  bibtex: '@article{Kebschull_Platzner_Teich_2010, title={Selected papers from the
    18th International Conference on Field Programmable Logic and Applications, FPL
    2008 (editorial)}, volume={4}, DOI={<a href="https://doi.org/10.1049/iet-cdt.2010.9044">10.1049/iet-cdt.2010.9044</a>},
    number={3}, journal={IET Computers Digital Techniques}, author={Kebschull, Udo
    and Platzner, Marco and Teich, Jürgen}, year={2010}, pages={157–158} }'
  chicago: 'Kebschull, Udo, Marco Platzner, and Jürgen Teich. “Selected Papers from
    the 18th International Conference on Field Programmable Logic and Applications,
    FPL 2008 (Editorial).” <i>IET Computers Digital Techniques</i> 4, no. 3 (2010):
    157–58. <a href="https://doi.org/10.1049/iet-cdt.2010.9044">https://doi.org/10.1049/iet-cdt.2010.9044</a>.'
  ieee: U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International
    Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),”
    <i>IET Computers Digital Techniques</i>, vol. 4, no. 3, pp. 157–158, 2010.
  mla: Kebschull, Udo, et al. “Selected Papers from the 18th International Conference
    on Field Programmable Logic and Applications, FPL 2008 (Editorial).” <i>IET Computers
    Digital Techniques</i>, vol. 4, no. 3, 2010, pp. 157–58, doi:<a href="https://doi.org/10.1049/iet-cdt.2010.9044">10.1049/iet-cdt.2010.9044</a>.
  short: U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques 4 (2010)
    157–158.
date_created: 2019-07-10T11:30:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1049/iet-cdt.2010.9044
intvolume: '         4'
issue: '3'
language:
- iso: eng
page: 157-158
publication: IET Computers Digital Techniques
publication_identifier:
  issn:
  - 1751-8601
status: public
title: Selected papers from the 18th International Conference on Field Programmable
  Logic and Applications, FPL 2008 (editorial)
type: journal_article
user_id: '3118'
volume: 4
year: '2010'
...
---
_id: '10697'
author:
- first_name: Tobias
  full_name: Knieper, Tobias
  last_name: Knieper
citation:
  ama: Knieper T. <i>Hybridization of Global Multi-Objective and Local Search Techniques</i>.
    Paderborn University; 2010.
  apa: Knieper, T. (2010). <i>Hybridization of Global Multi-Objective and Local Search
    Techniques</i>. Paderborn University.
  bibtex: '@book{Knieper_2010, title={Hybridization of Global Multi-Objective and
    Local Search Techniques}, publisher={Paderborn University}, author={Knieper, Tobias},
    year={2010} }'
  chicago: Knieper, Tobias. <i>Hybridization of Global Multi-Objective and Local Search
    Techniques</i>. Paderborn University, 2010.
  ieee: T. Knieper, <i>Hybridization of Global Multi-Objective and Local Search Techniques</i>.
    Paderborn University, 2010.
  mla: Knieper, Tobias. <i>Hybridization of Global Multi-Objective and Local Search
    Techniques</i>. Paderborn University, 2010.
  short: T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques,
    Paderborn University, 2010.
date_created: 2019-07-10T11:30:23Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Hybridization of Global Multi-Objective and Local Search Techniques
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10699'
author:
- first_name: Tobias
  full_name: Knieper, Tobias
  last_name: Knieper
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Jim
  full_name: Torresen, Jim
  last_name: Torresen
citation:
  ama: 'Knieper T, Kaufmann P, Glette K, Platzner M, Torresen J. Coping with Resource
    Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture.
    In: <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>. Vol 6274. LNCS. Springer;
    2010:250-261.'
  apa: 'Knieper, T., Kaufmann, P., Glette, K., Platzner, M., &#38; Torresen, J. (2010).
    Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit
    Row Classifier Architecture. In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>
    (Vol. 6274, pp. 250–261). Springer.'
  bibtex: '@inproceedings{Knieper_Kaufmann_Glette_Platzner_Torresen_2010, series={LNCS},
    title={Coping with Resource Fluctuations: The Run-time Reconfigurable Functional
    Unit Row Classifier Architecture}, volume={6274}, booktitle={IEEE Intl. Conf.
    on Evolvable Systems (ICES)}, publisher={Springer}, author={Knieper, Tobias and
    Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2010},
    pages={250–261}, collection={LNCS} }'
  chicago: 'Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner, and Jim
    Torresen. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional
    Unit Row Classifier Architecture.” In <i>IEEE Intl. Conf. on Evolvable Systems
    (ICES)</i>, 6274:250–61. LNCS. Springer, 2010.'
  ieee: 'T. Knieper, P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Coping
    with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier
    Architecture,” in <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 2010, vol.
    6274, pp. 250–261.'
  mla: 'Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable
    Functional Unit Row Classifier Architecture.” <i>IEEE Intl. Conf. on Evolvable
    Systems (ICES)</i>, vol. 6274, Springer, 2010, pp. 250–61.'
  short: 'T. Knieper, P. Kaufmann, K. Glette, M. Platzner, J. Torresen, in: IEEE Intl.
    Conf. on Evolvable Systems (ICES), Springer, 2010, pp. 250–261.'
date_created: 2019-07-10T11:38:03Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: '      6274'
language:
- iso: eng
page: 250-261
publication: IEEE Intl. Conf. on Evolvable Systems (ICES)
publisher: Springer
series_title: LNCS
status: public
title: 'Coping with Resource Fluctuations: The Run-time Reconfigurable Functional
  Unit Row Classifier Architecture'
type: conference
user_id: '3118'
volume: 6274
year: '2010'
...
---
_id: '10704'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. ReconOS: An Operating System for Dynamically Reconfigurable
    Hardware. In: Platzner M, Teich J, Wehn N, eds. <i>Dynamically Reconfigurable
    Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH;
    2010:269-290. doi:<a href="https://doi.org/10.1007/978-90-481-3485-4_13">10.1007/978-90-481-3485-4_13</a>'
  apa: 'Lübbers, E., &#38; Platzner, M. (2010). ReconOS: An Operating System for Dynamically
    Reconfigurable Hardware. In M. Platzner, J. Teich, &#38; N. Wehn (Eds.), <i>Dynamically
    Reconfigurable Systems: Architectures, Design Methods and Applications</i> (pp.
    269–290). Springer-Verlag GmbH. <a href="https://doi.org/10.1007/978-90-481-3485-4_13">https://doi.org/10.1007/978-90-481-3485-4_13</a>'
  bibtex: '@inbook{Lübbers_Platzner_2010, title={ReconOS: An Operating System for
    Dynamically Reconfigurable Hardware}, DOI={<a href="https://doi.org/10.1007/978-90-481-3485-4_13">10.1007/978-90-481-3485-4_13</a>},
    booktitle={Dynamically Reconfigurable Systems: Architectures, Design Methods and
    Applications}, publisher={Springer-Verlag GmbH}, author={Lübbers, Enno and Platzner,
    Marco}, editor={Platzner, Marco and Teich, Jürgen and Wehn, NorbertEditors}, year={2010},
    pages={269–290} }'
  chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically
    Reconfigurable Hardware.” In <i>Dynamically Reconfigurable Systems: Architectures,
    Design Methods and Applications</i>, edited by Marco Platzner, Jürgen Teich, and
    Norbert Wehn, 269–90. Springer-Verlag GmbH, 2010. <a href="https://doi.org/10.1007/978-90-481-3485-4_13">https://doi.org/10.1007/978-90-481-3485-4_13</a>.'
  ieee: 'E. Lübbers and M. Platzner, “ReconOS: An Operating System for Dynamically
    Reconfigurable Hardware,” in <i>Dynamically Reconfigurable Systems: Architectures,
    Design Methods and Applications</i>, M. Platzner, J. Teich, and N. Wehn, Eds.
    Springer-Verlag GmbH, 2010, pp. 269–290.'
  mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically
    Reconfigurable Hardware.” <i>Dynamically Reconfigurable Systems: Architectures,
    Design Methods and Applications</i>, edited by Marco Platzner et al., Springer-Verlag
    GmbH, 2010, pp. 269–90, doi:<a href="https://doi.org/10.1007/978-90-481-3485-4_13">10.1007/978-90-481-3485-4_13</a>.'
  short: 'E. Lübbers, M. Platzner, in: M. Platzner, J. Teich, N. Wehn (Eds.), Dynamically
    Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag
    GmbH, 2010, pp. 269–290.'
date_created: 2019-07-10T11:41:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1007/978-90-481-3485-4_13
editor:
- first_name: Marco
  full_name: Platzner, Marco
  last_name: Platzner
- first_name: Jürgen
  full_name: Teich, Jürgen
  last_name: Teich
- first_name: Norbert
  full_name: Wehn, Norbert
  last_name: Wehn
language:
- iso: eng
page: 269-290
publication: 'Dynamically Reconfigurable Systems: Architectures, Design Methods and
  Applications'
publisher: Springer-Verlag GmbH
status: public
title: 'ReconOS: An Operating System for Dynamically Reconfigurable Hardware'
type: book_chapter
user_id: '3118'
year: '2010'
...
---
_id: '10710'
author:
- first_name: Robert
  full_name: Meiche, Robert
  last_name: Meiche
citation:
  ama: Meiche R. <i>FPGA/CPU Multicore-Plattform Für ReconOS/ECos</i>. Paderborn University;
    2010.
  apa: Meiche, R. (2010). <i>FPGA/CPU Multicore-Plattform für ReconOS/eCos</i>. Paderborn
    University.
  bibtex: '@book{Meiche_2010, title={FPGA/CPU Multicore-Plattform für ReconOS/eCos},
    publisher={Paderborn University}, author={Meiche, Robert}, year={2010} }'
  chicago: Meiche, Robert. <i>FPGA/CPU Multicore-Plattform Für ReconOS/ECos</i>. Paderborn
    University, 2010.
  ieee: R. Meiche, <i>FPGA/CPU Multicore-Plattform für ReconOS/eCos</i>. Paderborn
    University, 2010.
  mla: Meiche, Robert. <i>FPGA/CPU Multicore-Plattform Für ReconOS/ECos</i>. Paderborn
    University, 2010.
  short: R. Meiche, FPGA/CPU Multicore-Plattform Für ReconOS/ECos, Paderborn University,
    2010.
date_created: 2019-07-10T11:43:35Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: FPGA/CPU Multicore-Plattform für ReconOS/eCos
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10717'
author:
- first_name: Manuel
  full_name: Niekamp, Manuel
  last_name: Niekamp
citation:
  ama: Niekamp M. <i>Transparente Hardwarebeschleunigung Durch Shared Library Interposing</i>.
    Paderborn University; 2010.
  apa: Niekamp, M. (2010). <i>Transparente Hardwarebeschleunigung durch Shared Library
    Interposing</i>. Paderborn University.
  bibtex: '@book{Niekamp_2010, title={Transparente Hardwarebeschleunigung durch Shared
    Library Interposing}, publisher={Paderborn University}, author={Niekamp, Manuel},
    year={2010} }'
  chicago: Niekamp, Manuel. <i>Transparente Hardwarebeschleunigung Durch Shared Library
    Interposing</i>. Paderborn University, 2010.
  ieee: M. Niekamp, <i>Transparente Hardwarebeschleunigung durch Shared Library Interposing</i>.
    Paderborn University, 2010.
  mla: Niekamp, Manuel. <i>Transparente Hardwarebeschleunigung Durch Shared Library
    Interposing</i>. Paderborn University, 2010.
  short: M. Niekamp, Transparente Hardwarebeschleunigung Durch Shared Library Interposing,
    Paderborn University, 2010.
date_created: 2019-07-10T11:48:28Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
title: Transparente Hardwarebeschleunigung durch Shared Library Interposing
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10731'
author:
- first_name: Bodo
  full_name: Runde, Bodo
  last_name: Runde
citation:
  ama: Runde B. <i>A Token-Ring Network-On-Chip for Message Passing in ReconOS</i>.
    Paderborn University; 2010.
  apa: Runde, B. (2010). <i>A Token-Ring Network-On-Chip for Message Passing in ReconOS</i>.
    Paderborn University.
  bibtex: '@book{Runde_2010, title={A Token-Ring Network-On-Chip for Message Passing
    in ReconOS}, publisher={Paderborn University}, author={Runde, Bodo}, year={2010}
    }'
  chicago: Runde, Bodo. <i>A Token-Ring Network-On-Chip for Message Passing in ReconOS</i>.
    Paderborn University, 2010.
  ieee: B. Runde, <i>A Token-Ring Network-On-Chip for Message Passing in ReconOS</i>.
    Paderborn University, 2010.
  mla: Runde, Bodo. <i>A Token-Ring Network-On-Chip for Message Passing in ReconOS</i>.
    Paderborn University, 2010.
  short: B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS, Paderborn
    University, 2010.
date_created: 2019-07-10T11:54:50Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: A Token-Ring Network-On-Chip for Message Passing in ReconOS
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10752'
author:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
citation:
  ama: Wiersema T. <i>Scheduling Support for Heterogeneous Hardware Accelerators under
    Linux</i>. Paderborn University; 2010.
  apa: Wiersema, T. (2010). <i>Scheduling Support for Heterogeneous Hardware Accelerators
    under Linux</i>. Paderborn University.
  bibtex: '@book{Wiersema_2010, title={Scheduling Support for Heterogeneous Hardware
    Accelerators under Linux}, publisher={Paderborn University}, author={Wiersema,
    Tobias}, year={2010} }'
  chicago: Wiersema, Tobias. <i>Scheduling Support for Heterogeneous Hardware Accelerators
    under Linux</i>. Paderborn University, 2010.
  ieee: T. Wiersema, <i>Scheduling Support for Heterogeneous Hardware Accelerators
    under Linux</i>. Paderborn University, 2010.
  mla: Wiersema, Tobias. <i>Scheduling Support for Heterogeneous Hardware Accelerators
    under Linux</i>. Paderborn University, 2010.
  short: T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under
    Linux, Paderborn University, 2010.
date_created: 2019-07-10T12:03:02Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
title: Scheduling Support for Heterogeneous Hardware Accelerators under Linux
type: mastersthesis
user_id: '3118'
year: '2010'
...
---
_id: '10763'
citation:
  ama: 'Platzner M, Teich J, Wehn N, eds. <i>Dynamically Reconfigurable Systems: Architectures,
    Design Methods and Applications</i>. Springer-Verlag GmbH; 2010. doi:<a href="https://doi.org/10.1007/978-90-481-3485-4">10.1007/978-90-481-3485-4</a>'
  apa: 'Platzner, M., Teich, J., &#38; Wehn, N. (Eds.). (2010). <i>Dynamically Reconfigurable
    Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH.
    <a href="https://doi.org/10.1007/978-90-481-3485-4">https://doi.org/10.1007/978-90-481-3485-4</a>'
  bibtex: '@book{Platzner_Teich_Wehn_2010, title={Dynamically Reconfigurable Systems:
    Architectures, Design Methods and Applications}, DOI={<a href="https://doi.org/10.1007/978-90-481-3485-4">10.1007/978-90-481-3485-4</a>},
    publisher={Springer-Verlag GmbH}, year={2010} }'
  chicago: 'Platzner, Marco, Jürgen Teich, and Norbert Wehn, eds. <i>Dynamically Reconfigurable
    Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH,
    2010. <a href="https://doi.org/10.1007/978-90-481-3485-4">https://doi.org/10.1007/978-90-481-3485-4</a>.'
  ieee: 'M. Platzner, J. Teich, and N. Wehn, Eds., <i>Dynamically Reconfigurable Systems:
    Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH, 2010.'
  mla: 'Platzner, Marco, et al., editors. <i>Dynamically Reconfigurable Systems: Architectures,
    Design Methods and Applications</i>. Springer-Verlag GmbH, 2010, doi:<a href="https://doi.org/10.1007/978-90-481-3485-4">10.1007/978-90-481-3485-4</a>.'
  short: 'M. Platzner, J. Teich, N. Wehn, eds., Dynamically Reconfigurable Systems:
    Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010.'
date_created: 2019-07-10T12:07:04Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1007/978-90-481-3485-4
editor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Jürgen
  full_name: Teich, Jürgen
  last_name: Teich
- first_name: Norbert
  full_name: Wehn, Norbert
  last_name: Wehn
language:
- iso: eng
publication_identifier:
  isbn:
  - '9048134846'
publisher: Springer-Verlag GmbH
status: public
title: 'Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications'
type: book_editor
user_id: '3118'
year: '2010'
...