---
_id: '2222'
citation:
  ama: Plaks TP, Andrews D, DeMara R, et al., eds. <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010.
  apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &#38;
    Stitt, G. (Eds.). (2010). <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press.
  bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
    Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, year={2010} }'
  chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
    Christian Plessl, and Greg Stitt, eds. <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  ieee: T. P. Plaks <i>et al.</i>, Eds., <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  mla: Plaks, Toomas P., et al., editors. <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
    Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
    CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
  full_name: Plaks, Toomas P.
  last_name: Plaks
- first_name: David
  full_name: Andrews, David
  last_name: Andrews
- first_name: Ronald
  full_name: DeMara, Ronald
  last_name: DeMara
- first_name: Herman
  full_name: Lam, Herman
  last_name: Lam
- first_name: Jooheung
  full_name: Lee, Jooheung
  last_name: Lee
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Greg
  full_name: Stitt, Greg
  last_name: Stitt
language:
- iso: eng
publication_identifier:
  isbn:
  - 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
- first_name: Manuel
  full_name: Niekamp, Manuel
  last_name: Niekamp
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
    Acceleration in Systems with Heterogeneous Hardware Accelerators. In: <i>Proc.
    Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>.
    IEEE Computer Society; 2010:65-72. doi:<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>'
  apa: Beisel, T., Niekamp, M., &#38; Plessl, C. (2010). Using Shared Library Interposing
    for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
    <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
    (ASAP)</i>, 65–72. <a href="https://doi.org/10.1109/ASAP.2010.5540798">https://doi.org/10.1109/ASAP.2010.5540798</a>
  bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
    Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
    Accelerators}, DOI={<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>},
    booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
    Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
    and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
  chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
    Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
    Accelerators.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures,
    and Processors (ASAP)</i>, 65–72. IEEE Computer Society, 2010. <a href="https://doi.org/10.1109/ASAP.2010.5540798">https://doi.org/10.1109/ASAP.2010.5540798</a>.
  ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
    Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
    in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
    (ASAP)</i>, 2010, pp. 65–72, doi: <a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>.'
  mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
    in Systems with Heterogeneous Hardware Accelerators.” <i>Proc. Int. Conf. on Application-Specific
    Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2010,
    pp. 65–72, doi:<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>.
  short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
    Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
    65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
  Processors (ASAP)
publication_identifier:
  isbn:
  - 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
  Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
  full_name: Keller, Ariane
  last_name: Keller
- first_name: Bernhard
  full_name: Plattner, Bernhard
  last_name: Plattner
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
    for Future Networks. In: <i>Proc. IEEE Globecom Workshop on Network of the Future
    (FutureNet)</i>. IEEE; 2010:372-376. doi:<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>'
  apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., &#38; Plessl, C. (2010).
    Reconfigurable Nodes for Future Networks. <i>Proc. IEEE Globecom Workshop on Network
    of the Future (FutureNet)</i>, 372–376. <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>
  bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
    Nodes for Future Networks}, DOI={<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>},
    booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
    publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
    and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
  chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
    Plessl. “Reconfigurable Nodes for Future Networks.” In <i>Proc. IEEE Globecom
    Workshop on Network of the Future (FutureNet)</i>, 372–76. IEEE, 2010. <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>.
  ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
    Nodes for Future Networks,” in <i>Proc. IEEE Globecom Workshop on Network of the
    Future (FutureNet)</i>, 2010, pp. 372–376, doi: <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>.'
  mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” <i>Proc.
    IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, IEEE, 2010, pp.
    372–76, doi:<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>.
  short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
    Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
  isbn:
  - 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Michael
  full_name: Kauschke, Michael
  last_name: Kauschke
citation:
  ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
    Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
    <i>Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA)</i>. ; 2010.'
  apa: Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance
    Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
    &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping
    (WARP), International Symposium on Computer Architecture (ISCA)</i>.
  bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
    Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
    Workshop on Architectural Research Prototyping (WARP), International Symposium
    on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
    Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
    Sandra}, year={2010} }'
  chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
    “Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
    In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra
    Larrabee, 2010.
  ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
    for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on
    Architectural Research Prototyping (WARP), International Symposium on Computer
    Architecture (ISCA)</i>, 2010.
  mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
    Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP),
    International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami
    and Sandra Larrabee, 2010.
  short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
    (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
  full_name: Hammami, Omar
  last_name: Hammami
- first_name: Sandra
  full_name: Larrabee, Sandra
  last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
  Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '10639'
author:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Michael
  full_name: Winkler, Michael
  last_name: Winkler
citation:
  ama: 'Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand
    prostheses: Combining adaptive classification with high precision sockets. In:
    <i>Proc. Technically Assisted Rehabilitation (TAR)</i>. ; 2009.'
  apa: 'Boschmann, A., Kaufmann, P., Platzner, M., &#38; Winkler, M. (2009). Towards
    multi-movement hand prostheses: Combining adaptive classification with high precision
    sockets. In <i>Proc. Technically Assisted Rehabilitation (TAR)</i>.'
  bibtex: '@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards
    multi-movement hand prostheses: Combining adaptive classification with high precision
    sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann,
    Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009}
    }'
  chicago: 'Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler.
    “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with
    High Precision Sockets.” In <i>Proc. Technically Assisted Rehabilitation (TAR)</i>,
    2009.'
  ieee: 'A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement
    hand prostheses: Combining adaptive classification with high precision sockets,”
    in <i>Proc. Technically Assisted Rehabilitation (TAR)</i>, 2009.'
  mla: 'Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining
    Adaptive Classification with High Precision Sockets.” <i>Proc. Technically Assisted
    Rehabilitation (TAR)</i>, 2009.'
  short: 'A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically
    Assisted Rehabilitation (TAR), 2009.'
date_created: 2019-07-10T11:03:25Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. Technically Assisted Rehabilitation (TAR)
status: public
title: 'Towards multi-movement hand prostheses: Combining adaptive classification
  with high precision sockets'
type: conference
user_id: '3118'
year: '2009'
...
---
_id: '10702'
author:
- first_name: Alexander
  full_name: Kostin, Alexander
  last_name: Kostin
citation:
  ama: Kostin A. <i>Evolvable Robot Controller</i>. Paderborn University; 2009.
  apa: Kostin, A. (2009). <i>Evolvable Robot Controller</i>. Paderborn University.
  bibtex: '@book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn
    University}, author={Kostin, Alexander}, year={2009} }'
  chicago: Kostin, Alexander. <i>Evolvable Robot Controller</i>. Paderborn University,
    2009.
  ieee: A. Kostin, <i>Evolvable Robot Controller</i>. Paderborn University, 2009.
  mla: Kostin, Alexander. <i>Evolvable Robot Controller</i>. Paderborn University,
    2009.
  short: A. Kostin, Evolvable Robot Controller, Paderborn University, 2009.
date_created: 2019-07-10T11:38:28Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Evolvable Robot Controller
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10703'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable
    Computers. <i>ACM Transactions on Embedded Computing Systems</i>. 2009;9(1):8:1-8:33.
    doi:<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>'
  apa: 'Lübbers, E., &#38; Platzner, M. (2009). ReconOS: Multithreaded Programming
    for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>,
    <i>9</i>(1), 8:1-8:33. <a href="https://doi.org/10.1145/1596532.1596540">https://doi.org/10.1145/1596532.1596540</a>'
  bibtex: '@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming
    for Reconfigurable Computers}, volume={9}, DOI={<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>},
    number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers,
    Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }'
  chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming
    for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>
    9, no. 1 (2009): 8:1-8:33. <a href="https://doi.org/10.1145/1596532.1596540">https://doi.org/10.1145/1596532.1596540</a>.'
  ieee: 'E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable
    Computers,” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no.
    1, pp. 8:1-8:33, 2009.'
  mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for
    Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>,
    vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>.'
  short: E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9
    (2009) 8:1-8:33.
date_created: 2019-07-10T11:41:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1145/1596532.1596540
intvolume: '         9'
issue: '1'
keyword:
- Reconfigurable computing
- multithreading
- operating systems
language:
- iso: eng
page: 8:1-8:33
publication: ACM Transactions on Embedded Computing Systems
publication_identifier:
  issn:
  - 1539-9087
status: public
title: 'ReconOS: Multithreaded Programming for Reconfigurable Computers'
type: journal_article
user_id: '3118'
volume: 9
year: '2009'
...
---
_id: '10746'
author:
- first_name: Martin
  full_name: Tofall, Martin
  last_name: Tofall
citation:
  ama: Tofall M. <i>Compiler for a Custom Instruction Set CPU</i>. Paderborn University;
    2009.
  apa: Tofall, M. (2009). <i>Compiler for a Custom Instruction Set CPU</i>. Paderborn
    University.
  bibtex: '@book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn
    University}, author={Tofall, Martin}, year={2009} }'
  chicago: Tofall, Martin. <i>Compiler for a Custom Instruction Set CPU</i>. Paderborn
    University, 2009.
  ieee: M. Tofall, <i>Compiler for a Custom Instruction Set CPU</i>. Paderborn University,
    2009.
  mla: Tofall, Martin. <i>Compiler for a Custom Instruction Set CPU</i>. Paderborn
    University, 2009.
  short: M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University,
    2009.
date_created: 2019-07-10T12:01:52Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Compiler for a Custom Instruction Set CPU
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10749'
author:
- first_name: Alexander
  full_name: Warkentin, Alexander
  last_name: Warkentin
citation:
  ama: Warkentin A. <i>Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional
    Units</i>. Paderborn University; 2009.
  apa: Warkentin, A. (2009). <i>Coarse-grained CGP Model using Xilinx Virtex5 DSP48E
    Functional Units</i>. Paderborn University.
  bibtex: '@book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5
    DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin,
    Alexander}, year={2009} }'
  chicago: Warkentin, Alexander. <i>Coarse-Grained CGP Model Using Xilinx Virtex5
    DSP48E Functional Units</i>. Paderborn University, 2009.
  ieee: A. Warkentin, <i>Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional
    Units</i>. Paderborn University, 2009.
  mla: Warkentin, Alexander. <i>Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E
    Functional Units</i>. Paderborn University, 2009.
  short: A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional
    Units, Paderborn University, 2009.
date_created: 2019-07-10T12:02:58Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units
type: mastersthesis
user_id: '3118'
year: '2009'
...
---
_id: '10753'
author:
- first_name: Benedikt
  full_name: Wildenhain, Benedikt
  last_name: Wildenhain
citation:
  ama: Wildenhain B. <i>Implementierung von Kryptographie-Hardwarebeschleunigern Für
    Das HW/SW-Betriebssystem ReconOS</i>. Paderborn University; 2009.
  apa: Wildenhain, B. (2009). <i>Implementierung von Kryptographie-Hardwarebeschleunigern
    für das HW/SW-Betriebssystem ReconOS</i>. Paderborn University.
  bibtex: '@book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern
    für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain,
    Benedikt}, year={2009} }'
  chicago: Wildenhain, Benedikt. <i>Implementierung von Kryptographie-Hardwarebeschleunigern
    Für Das HW/SW-Betriebssystem ReconOS</i>. Paderborn University, 2009.
  ieee: B. Wildenhain, <i>Implementierung von Kryptographie-Hardwarebeschleunigern
    für das HW/SW-Betriebssystem ReconOS</i>. Paderborn University, 2009.
  mla: Wildenhain, Benedikt. <i>Implementierung von Kryptographie-Hardwarebeschleunigern
    Für Das HW/SW-Betriebssystem ReconOS</i>. Paderborn University, 2009.
  short: B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für
    Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.
date_created: 2019-07-10T12:05:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem
  ReconOS
type: bachelorsthesis
user_id: '3118'
year: '2009'
...
---
_id: '10777'
author:
- first_name: Hassan
  full_name: Ghasemzadeh Mohammadi, Hassan
  id: '61186'
  last_name: Ghasemzadeh Mohammadi
- first_name: Seyed Ghassem
  full_name: Miremadi, Seyed Ghassem
  last_name: Miremadi
- first_name: Alireza
  full_name: Ejlali, Alireza
  last_name: Ejlali
citation:
  ama: 'Ghasemzadeh Mohammadi H, Miremadi SG, Ejlali A. Signature Self Checking (SSC):
    A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In: <i>Dependable
    Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On</i>. IEEE;
    2009:252-255. doi:<a href="https://doi.org/10.1109/PRDC.2009.69">10.1109/PRDC.2009.69</a>'
  apa: 'Ghasemzadeh Mohammadi, H., Miremadi, S. G., &#38; Ejlali, A. (2009). Signature
    Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.
    In <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
    on</i> (pp. 252–255). IEEE. <a href="https://doi.org/10.1109/PRDC.2009.69">https://doi.org/10.1109/PRDC.2009.69</a>'
  bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Miremadi_Ejlali_2009, title={Signature
    Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors},
    DOI={<a href="https://doi.org/10.1109/PRDC.2009.69">10.1109/PRDC.2009.69</a>},
    booktitle={Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
    on}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed
    Ghassem and Ejlali, Alireza}, year={2009}, pages={252–255} }'
  chicago: 'Ghasemzadeh Mohammadi, Hassan, Seyed Ghassem Miremadi, and Alireza Ejlali.
    “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined
    Microprocessors.” In <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International
    Symposium On</i>, 252–55. IEEE, 2009. <a href="https://doi.org/10.1109/PRDC.2009.69">https://doi.org/10.1109/PRDC.2009.69</a>.'
  ieee: 'H. Ghasemzadeh Mohammadi, S. G. Miremadi, and A. Ejlali, “Signature Self
    Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors,”
    in <i>Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
    on</i>, 2009, pp. 252–255.'
  mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost
    Reliable Control Logic for Pipelined Microprocessors.” <i>Dependable Computing
    (PRDC), 2009 IEEE Pacific Rim International Symposium On</i>, IEEE, 2009, pp.
    252–55, doi:<a href="https://doi.org/10.1109/PRDC.2009.69">10.1109/PRDC.2009.69</a>.'
  short: 'H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing
    (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.'
date_created: 2019-07-10T12:11:34Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/PRDC.2009.69
extern: '1'
language:
- iso: eng
page: 252-255
publication: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium
  on
publisher: IEEE
status: public
title: 'Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined
  Microprocessors'
type: conference
user_id: '3118'
year: '2009'
...
---
_id: '13632'
author:
- first_name: Markus
  full_name: Happe, Markus
  last_name: Happe
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte
    Carlo Methods on CPU/FPGA Platforms. In: <i>Proceedings of the International Workshop
    on Applied Reconfigurable Computing (ARC)</i>. Springer; 2009.'
  apa: Happe, M., Lübbers, E., &#38; Platzner, M. (2009). A Multithreaded Framework
    for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In <i>Proceedings of
    the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer.
  bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework
    for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings
    of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer},
    author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }'
  chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework
    for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In <i>Proceedings of
    the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer,
    2009.
  ieee: M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential
    Monte Carlo Methods on CPU/FPGA Platforms,” in <i>Proceedings of the International
    Workshop on Applied Reconfigurable Computing (ARC)</i>, 2009.
  mla: Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo
    Methods on CPU/FPGA Platforms.” <i>Proceedings of the International Workshop on
    Applied Reconfigurable Computing (ARC)</i>, Springer, 2009.
  short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International
    Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.'
date_created: 2019-10-04T22:13:24Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
  (ARC)
publisher: Springer
status: public
title: A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13634'
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable
    Mesh. In: <i>Proceedings of the Workshop on Many-Cores, International Conference
    on Architecture of Computing Systems (ARCS)</i>. ; 2009.'
  apa: 'Giefers, H., &#38; Platzner, M. (2009). Towards Models for Many-Cores: The
    Case for the Reconfigurable Mesh. In <i>Proceedings of the Workshop on Many-Cores,
    International Conference on Architecture of Computing Systems (ARCS)</i>.'
  bibtex: '@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores:
    The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop
    on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)},
    author={Giefers, Heiner and Platzner, Marco}, year={2009} }'
  chicago: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The
    Case for the Reconfigurable Mesh.” In <i>Proceedings of the Workshop on Many-Cores,
    International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.'
  ieee: 'H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for
    the Reconfigurable Mesh,” in <i>Proceedings of the Workshop on Many-Cores, International
    Conference on Architecture of Computing Systems (ARCS)</i>, 2009.'
  mla: 'Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case
    for the Reconfigurable Mesh.” <i>Proceedings of the Workshop on Many-Cores, International
    Conference on Architecture of Computing Systems (ARCS)</i>, 2009.'
  short: 'H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores,
    International Conference on Architecture of Computing Systems (ARCS), 2009.'
date_created: 2019-10-04T22:16:01Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the Workshop on Many-Cores, International Conference on
  Architecture of Computing Systems (ARCS)
status: public
title: 'Towards Models for Many-Cores: The Case for the Reconfigurable Mesh'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13635'
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable
    Mesh Many-Cores. In: <i>Reconfigurable Architectures Workshop (RAW), Proceedings
    of the International Parallel and Distributed Processing Symposium</i>. IEEE;
    2009.'
  apa: 'Giefers, H., &#38; Platzner, M. (2009). ARMLang: A Language and Compiler for
    Programming Reconfigurable Mesh Many-Cores. In <i>Reconfigurable Architectures
    Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
    Symposium</i>. IEEE.'
  bibtex: '@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler
    for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures
    Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
    Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009}
    }'
  chicago: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler
    for Programming Reconfigurable Mesh Many-Cores.” In <i>Reconfigurable Architectures
    Workshop (RAW), Proceedings of the International Parallel and Distributed Processing
    Symposium</i>. IEEE, 2009.'
  ieee: 'H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming
    Reconfigurable Mesh Many-Cores,” in <i>Reconfigurable Architectures Workshop (RAW),
    Proceedings of the International Parallel and Distributed Processing Symposium</i>,
    2009.'
  mla: 'Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for
    Programming Reconfigurable Mesh Many-Cores.” <i>Reconfigurable Architectures Workshop
    (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>,
    IEEE, 2009.'
  short: 'H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW),
    Proceedings of the International Parallel and Distributed Processing Symposium,
    IEEE, 2009.'
date_created: 2019-10-04T22:17:57Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Reconfigurable Architectures Workshop (RAW), Proceedings of the International
  Parallel and Distributed Processing Symposium
publisher: IEEE
status: public
title: 'ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13636'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable
    Systems. In: <i>Proceedings of the 19th International Workshop on Field Programmable
    Logic and Applications (FPL) </i>. IEEE; 2009.'
  apa: Lübbers, E., &#38; Platzner, M. (2009). Cooperative Multithreading in Dynamically
    Reconfigurable Systems. In <i>Proceedings of the 19th International Workshop on
    Field Programmable Logic and Applications (FPL) </i>. IEEE.
  bibtex: '@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading
    in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International
    Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE},
    author={Lübbers, Enno and Platzner, Marco}, year={2009} }'
  chicago: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically
    Reconfigurable Systems.” In <i>Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.
  ieee: E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable
    Systems,” in <i>Proceedings of the 19th International Workshop on Field Programmable
    Logic and Applications (FPL) </i>, 2009.
  mla: Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically
    Reconfigurable Systems.” <i>Proceedings of the 19th International Workshop on
    Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009.
  short: 'E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) , IEEE, 2009.'
date_created: 2019-10-04T22:20:12Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: 'Proceedings of the 19th International Workshop on Field Programmable
  Logic and Applications (FPL) '
publisher: IEEE
status: public
title: Cooperative Multithreading in Dynamically Reconfigurable Systems
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13637'
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Giefers H, Platzner M. Program-driven Fine-grained Power Management for the
    Reconfigurable Mesh. In: <i>Proceedings of the 19th International Workshop on
    Field Programmable Logic and Applications (FPL) </i>. IEEE; 2009.'
  apa: Giefers, H., &#38; Platzner, M. (2009). Program-driven Fine-grained Power Management
    for the Reconfigurable Mesh. In <i>Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) </i>. IEEE.
  bibtex: '@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained
    Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th
    International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE},
    author={Giefers, Heiner and Platzner, Marco}, year={2009} }'
  chicago: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power
    Management for the Reconfigurable Mesh.” In <i>Proceedings of the 19th International
    Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.
  ieee: H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management
    for the Reconfigurable Mesh,” in <i>Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) </i>, 2009.
  mla: Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management
    for the Reconfigurable Mesh.” <i>Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009.
  short: 'H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop
    on Field Programmable Logic and Applications (FPL) , IEEE, 2009.'
date_created: 2019-10-04T22:22:02Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: 'Proceedings of the 19th International Workshop on Field Programmable
  Logic and Applications (FPL) '
publisher: IEEE
status: public
title: Program-driven Fine-grained Power Management for the Reconfigurable Mesh
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13638'
author:
- first_name: Markus
  full_name: Happe, Markus
  last_name: Happe
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework
    with runtime HW/SW repartitioning. In: <i>Proceedings of the 2009 International
    Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2009. doi:<a href="https://doi.org/10.1109/fpt.2009.5377645">10.1109/fpt.2009.5377645</a>'
  apa: Happe, M., Lübbers, E., &#38; Platzner, M. (2009). An adaptive Sequential Monte
    Carlo framework with runtime HW/SW repartitioning. In <i>Proceedings of the 2009
    International Conference on Field-Programmable Technology (FPT)</i>. IEEE. <a
    href="https://doi.org/10.1109/fpt.2009.5377645">https://doi.org/10.1109/fpt.2009.5377645</a>
  bibtex: '@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential
    Monte Carlo framework with runtime HW/SW repartitioning}, DOI={<a href="https://doi.org/10.1109/fpt.2009.5377645">10.1109/fpt.2009.5377645</a>},
    booktitle={Proceedings of the 2009 International Conference on Field-Programmable
    Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and
    Platzner, Marco}, year={2009} }'
  chicago: Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential
    Monte Carlo Framework with Runtime HW/SW Repartitioning.” In <i>Proceedings of
    the 2009 International Conference on Field-Programmable Technology (FPT)</i>.
    IEEE, 2009. <a href="https://doi.org/10.1109/fpt.2009.5377645">https://doi.org/10.1109/fpt.2009.5377645</a>.
  ieee: M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo
    framework with runtime HW/SW repartitioning,” in <i>Proceedings of the 2009 International
    Conference on Field-Programmable Technology (FPT)</i>, 2009.
  mla: Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime
    HW/SW Repartitioning.” <i>Proceedings of the 2009 International Conference on
    Field-Programmable Technology (FPT)</i>, IEEE, 2009, doi:<a href="https://doi.org/10.1109/fpt.2009.5377645">10.1109/fpt.2009.5377645</a>.
  short: 'M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International
    Conference on Field-Programmable Technology (FPT), IEEE, 2009.'
date_created: 2019-10-04T22:22:52Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpt.2009.5377645
language:
- iso: eng
publication: Proceedings of the 2009 International Conference on Field-Programmable
  Technology (FPT)
publication_identifier:
  isbn:
  - '9781424443758'
publication_status: published
publisher: IEEE
status: public
title: An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning
type: conference
user_id: '398'
year: '2009'
...
---
_id: '13639'
author:
- first_name: Stephanie
  full_name: Drzevitzky, Stephanie
  last_name: Drzevitzky
- first_name: Uwe
  full_name: Kastens, Uwe
  last_name: Kastens
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime
    Verification of Reconfigurable Modules. In: <i>Proceedings of the International
    Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2009.'
  apa: 'Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2009). Proof-carrying Hardware:
    Towards Runtime Verification of Reconfigurable Modules. In <i>Proceedings of the
    International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>.
    IEEE.'
  bibtex: '@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying
    Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings
    of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
    publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner,
    Marco}, year={2009} }'
  chicago: 'Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying
    Hardware: Towards Runtime Verification of Reconfigurable Modules.” In <i>Proceedings
    of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>.
    IEEE, 2009.'
  ieee: 'S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards
    Runtime Verification of Reconfigurable Modules,” in <i>Proceedings of the International
    Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009.'
  mla: 'Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification
    of Reconfigurable Modules.” <i>Proceedings of the International Conference on
    ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2009.'
  short: 'S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International
    Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.'
date_created: 2019-10-04T22:25:10Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Conference on ReConFigurable Computing
  and FPGAs (ReConFig)
publisher: IEEE
status: public
title: 'Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules'
type: conference
user_id: '398'
year: '2009'
...
---
_id: '2350'
abstract:
- lang: eng
  text: 'Mapping applications that consist of a collection of cores to FPGA accelerators
    and optimizing their performance is a challenging task in high performance reconfigurable
    computing. We present IMORC, an architectural template and highly versatile on-chip
    interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which
    allows for flexibly composing accelerators from cores running at full speed within
    their own clock domains, thus facilitating the re-use of cores and portability.
    Further, IMORC inserts performance counters for monitoring runtime data. In this
    paper, we first introduce the IMORC architectural template and the on-chip interconnect,
    and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor
    thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s
    monitoring infrastructure, we gain insights into the data-dependent behavior of
    the application which, in turn, allow for optimizing the accelerator. '
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring
    and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int.
    Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer
    Society; 2009:275-278. doi:<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>'
  apa: 'Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
    <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>,
    275–278. <a href="https://doi.org/10.1109/FCCM.2009.25">https://doi.org/10.1109/FCCM.2009.25</a>'
  bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing},
    DOI={<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>},
    booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
    publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian
    and Platzner, Marco}, year={2009}, pages={275–278} }'
  chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”
    In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>,
    275–78. IEEE Computer Society, 2009. <a href="https://doi.org/10.1109/FCCM.2009.25">https://doi.org/10.1109/FCCM.2009.25</a>.'
  ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring
    and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int.
    Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278,
    doi: <a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>.'
  mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization
    for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable
    Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78,
    doi:<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>.'
  short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable
    Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.'
date_created: 2018-04-16T15:05:52Z
date_updated: 2023-09-26T13:51:44Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2009.25
keyword:
- IMORC
- interconnect
- performance
language:
- iso: eng
page: 275-278
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publication_identifier:
  isbn:
  - 978-1-4244-4450-2
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance
  Reconfigurable Computing'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2262'
abstract:
- lang: eng
  text: 'In this work we present EvoCache, a novel approach for implementing application-specific
    caches. The key innovation of EvoCache is to make the function that maps memory
    addresses from the CPU address space to cache indices programmable. We support
    arbitrary Boolean mapping functions that are implemented within a small reconfigurable
    logic fabric. For finding suitable cache mapping functions we rely on techniques
    from the evolvable hardware domain and utilize an evolutionary optimization procedure.
    We evaluate the use of EvoCache in an embedded processor for two specific applications
    (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and
    energy consumption. We show that the evolvable hardware approach for optimizing
    the cache functions not only significantly improves the cache performance for
    the training data used during optimization, but that the evolved mapping functions
    generalize very well. Compared to a conventional cache architecture, EvoCache
    applied to test data achieves a reduction in execution time of up to 14.31% for
    JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70%
    for BZIP2). We also discuss the integration of EvoCache into the operating system
    and show that the area and delay overheads introduced by EvoCache are acceptable. '
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation
    of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems
    (AHS)</i>. IEEE Computer Society; 2009:11-18.'
  apa: 'Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific
    Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 11–18.'
  bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA,
    USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc.
    NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer
    Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009},
    pages={11–18} }'
  chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific
    Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.'
  ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific
    Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 2009, pp. 11–18.'
  mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache
    Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>,
    IEEE Computer Society, 2009, pp. 11–18.'
  short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive
    Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009,
    pp. 11–18.'
date_created: 2018-04-06T15:18:24Z
date_updated: 2023-09-26T13:53:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- EvoCache
- evolvable hardware
- computer architecture
language:
- iso: eng
page: 11-18
place: Los Alamitos, CA, USA
publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvoCaches: Application-specific Adaptation of Cache Mapping'
type: conference
user_id: '15278'
year: '2009'
...