---
_id: '2238'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Tim
  full_name: Süß, Tim
  last_name: Süß
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization
    for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on
    ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124.
    doi:<a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>'
  apa: Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication
    Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
    <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124.
    <a href="https://doi.org/10.1109/ReConFig.2009.32">https://doi.org/10.1109/ReConFig.2009.32</a>
  bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos,
    CA, USA}, title={Communication Performance Characterization for Reconfigurable
    Accelerator Design on the XD1000}, DOI={<a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>},
    booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
    publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and
    Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }'
  chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication
    Performance Characterization for Reconfigurable Accelerator Design on the XD1000.”
    In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24.
    Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href="https://doi.org/10.1109/ReConFig.2009.32">https://doi.org/10.1109/ReConFig.2009.32</a>.'
  ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance
    Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc.
    Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124,
    doi: <a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>.'
  mla: Schumacher, Tobias, et al. “Communication Performance Characterization for
    Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable
    Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a
    href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>.
  short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable
    Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA,
    2009, pp. 119–124.'
date_created: 2018-04-05T17:11:28Z
date_updated: 2023-09-26T13:52:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2009.32
keyword:
- IMORC
- graphics
language:
- iso: eng
page: 119-124
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
  isbn:
  - 978-0-7695-3917-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Communication Performance Characterization for Reconfigurable Accelerator Design
  on the XD1000
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2261'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor
    Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL)</i>. IEEE; 2009:338-344.'
  apa: Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th
    Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf.
    on Field Programmable Logic and Applications (FPL)</i>, 338–344.
  bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for
    k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc.
    Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE},
    author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009},
    pages={338–344} }'
  chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator
    for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc.
    Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE,
    2009.
  ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest
    Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on
    Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344.
  mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning
    Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.
  short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL), IEEE, 2009, pp. 338–344.'
date_created: 2018-04-06T15:15:47Z
date_updated: 2023-09-26T13:52:52Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- NOC
- KNN
- accelerator
language:
- iso: eng
page: 338-344
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publication_identifier:
  isbn:
  - 978-1-4244-3892-1
  issn:
  - 1946-1488
publisher: IEEE
quality_controlled: '1'
status: public
title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2263'
abstract:
- lang: eng
  text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture.
    The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary
    Processing Unit (APU) as well as the partial reconfiguration capabilities to provide
    dynamically reconfigurable custom instructions. We also present a hardware tool
    flow that automatically translates software functions into custom instructions
    and a software tool flow that creates binaries using these instructions. While
    previous research on processors with reconfigurable functional units has been
    performed predominantly with simulation, the Woolcano architecture allows for
    exploring dynamic instruction set extension with commercially available hardware.
    Finally, we present a case study demonstrating a custom floating-point instruction
    generated with our approach, which achieves a 40x speedup over software-emulated
    floating-point operations and a 21% speedup over the Xilinx hardware floating-point
    unit. '
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction
    Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of
    Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.'
  apa: 'Grad, M., &#38; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow
    for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. <i>Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–322.'
  bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture
    and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322}
    }'
  chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool
    Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    319–22. USA: CSREA Press, 2009.'
  ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic
    Instruction Set Extension on Xilinx Virtex-4 FX,” in <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>, 2009, pp. 319–322.'
  mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow
    for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” <i>Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press,
    2009, pp. 319–22.'
  short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.'
date_created: 2018-04-06T15:19:51Z
date_updated: 2023-09-26T13:53:30Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 319-322
place: USA
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-101-5
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension
  on Xilinx Virtex-4 FX'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2358'
author:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
- first_name: Stefan
  full_name: Lietsch, Stefan
  last_name: Lietsch
- first_name: Kris
  full_name: Thielemans, Kris
  last_name: Thielemans
citation:
  ama: 'Beisel T, Lietsch S, Thielemans K. A method for OSEM PET reconstruction on
    parallel architectures using STIR. In: <i>IEEE Nuclear Science Symposium Conference
    Record (NSS)</i>. IEEE; 2008:4161-4168. doi:<a href="https://doi.org/10.1109/NSSMIC.2008.4774198">10.1109/NSSMIC.2008.4774198</a>'
  apa: Beisel, T., Lietsch, S., &#38; Thielemans, K. (2008). A method for OSEM PET
    reconstruction on parallel architectures using STIR. In <i>IEEE Nuclear Science
    Symposium Conference Record (NSS)</i> (pp. 4161–4168). IEEE. <a href="https://doi.org/10.1109/NSSMIC.2008.4774198">https://doi.org/10.1109/NSSMIC.2008.4774198</a>
  bibtex: '@inproceedings{Beisel_Lietsch_Thielemans_2008, title={A method for OSEM
    PET reconstruction on parallel architectures using STIR}, DOI={<a href="https://doi.org/10.1109/NSSMIC.2008.4774198">10.1109/NSSMIC.2008.4774198</a>},
    booktitle={IEEE Nuclear Science Symposium Conference Record (NSS)}, publisher={IEEE},
    author={Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}, year={2008},
    pages={4161–4168} }'
  chicago: Beisel, Tobias, Stefan Lietsch, and Kris Thielemans. “A Method for OSEM
    PET Reconstruction on Parallel Architectures Using STIR.” In <i>IEEE Nuclear Science
    Symposium Conference Record (NSS)</i>, 4161–68. IEEE, 2008. <a href="https://doi.org/10.1109/NSSMIC.2008.4774198">https://doi.org/10.1109/NSSMIC.2008.4774198</a>.
  ieee: T. Beisel, S. Lietsch, and K. Thielemans, “A method for OSEM PET reconstruction
    on parallel architectures using STIR,” in <i>IEEE Nuclear Science Symposium Conference
    Record (NSS)</i>, 2008, pp. 4161–4168.
  mla: Beisel, Tobias, et al. “A Method for OSEM PET Reconstruction on Parallel Architectures
    Using STIR.” <i>IEEE Nuclear Science Symposium Conference Record (NSS)</i>, IEEE,
    2008, pp. 4161–68, doi:<a href="https://doi.org/10.1109/NSSMIC.2008.4774198">10.1109/NSSMIC.2008.4774198</a>.
  short: 'T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium
    Conference Record (NSS), IEEE, 2008, pp. 4161–4168.'
date_created: 2018-04-17T10:59:40Z
date_updated: 2022-01-06T06:55:57Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/NSSMIC.2008.4774198
page: 4161-4168
publication: IEEE Nuclear Science Symposium Conference Record (NSS)
publisher: IEEE
status: public
title: A method for OSEM PET reconstruction on parallel architectures using STIR
type: conference
user_id: '24135'
year: '2008'
...
---
_id: '2365'
author:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sven
  full_name: Döhre, Sven
  last_name: Döhre
- first_name: Markus
  full_name: Happe, Markus
  last_name: Happe
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Ulf
  full_name: Lorenz, Ulf
  last_name: Lorenz
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Andre
  full_name: Send, Andre
  last_name: Send
- first_name: Alexander
  full_name: Warkentin, Alexander
  last_name: Warkentin
citation:
  ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs.
    In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>. CSREA Press; 2008:245-251.'
  apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T.,
    … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>
    (pp. 245–251). CSREA Press.'
  bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008,
    title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter,
    Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander},
    year={2008}, pages={245–251} }'
  chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz,
    Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating
    GO with FPGAs.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems
    and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.'
  ieee: 'M. Platzner <i>et al.</i>, “The GOmputer: Accelerating GO with FPGAs,” in
    <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    2008, pp. 245–251.'
  mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    CSREA Press, 2008, pp. 245–51.'
  short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A.
    Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems
    and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:34:35Z
date_updated: 2022-01-06T06:55:58Z
department:
- _id: '27'
- _id: '78'
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-064-7
publisher: CSREA Press
status: public
title: 'The GOmputer: Accelerating GO with FPGAs'
type: conference
user_id: '24135'
year: '2008'
...
---
_id: '10628'
alternative_title:
- Effects of Pattern Matching Algorithms on Long-term Electromyography Signals
author:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
citation:
  ama: Boschmann A. <i>Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation
    von EMG-Signalen</i>. Paderborn University; 2008.
  apa: Boschmann, A. (2008). <i>Aufbau und experimentelle Bewertung eines Systems
    zur Langzeitklassifikation von EMG-Signalen</i>. Paderborn University.
  bibtex: '@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines
    Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University},
    author={Boschmann, Alexander}, year={2008} }'
  chicago: Boschmann, Alexander. <i>Aufbau Und Experimentelle Bewertung Eines Systems
    Zur Langzeitklassifikation von EMG-Signalen</i>. Paderborn University, 2008.
  ieee: A. Boschmann, <i>Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation
    von EMG-Signalen</i>. Paderborn University, 2008.
  mla: Boschmann, Alexander. <i>Aufbau Und Experimentelle Bewertung Eines Systems
    Zur Langzeitklassifikation von EMG-Signalen</i>. Paderborn University, 2008.
  short: A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassifikation
    von EMG-Signalen, Paderborn University, 2008.
date_created: 2019-07-10T09:40:26Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation
  von EMG-Signalen
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10641'
alternative_title:
- Self-optimizing Cache Controller
author:
- first_name: Daniel
  full_name: Breitlauch, Daniel
  last_name: Breitlauch
citation:
  ama: Breitlauch D. <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn University;
    2008.
  apa: Breitlauch, D. (2008). <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn
    University.
  bibtex: '@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn
    University}, author={Breitlauch, Daniel}, year={2008} }'
  chicago: Breitlauch, Daniel. <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn
    University, 2008.
  ieee: D. Breitlauch, <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn University,
    2008.
  mla: Breitlauch, Daniel. <i>Selbstoptimierender Cache-Kontroller</i>. Paderborn
    University, 2008.
  short: D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University,
    2008.
date_created: 2019-07-10T11:03:42Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Selbstoptimierender Cache-Kontroller
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10644'
alternative_title:
- Distributed Simulation of mobile Robots using EyeSim
author:
- first_name: Toni
  full_name: Ceylan, Toni
  last_name: Ceylan
- first_name: Coni
  full_name: Yalcin, Coni
  last_name: Yalcin
citation:
  ama: Ceylan T, Yalcin C. <i>Verteilte Simulation von Mobilen Robotern Mit EyeSim</i>.
    Paderborn University; 2008.
  apa: Ceylan, T., &#38; Yalcin, C. (2008). <i>Verteilte Simulation von mobilen Robotern
    mit EyeSim</i>. Paderborn University.
  bibtex: '@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern
    mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin,
    Coni}, year={2008} }'
  chicago: Ceylan, Toni, and Coni Yalcin. <i>Verteilte Simulation von Mobilen Robotern
    Mit EyeSim</i>. Paderborn University, 2008.
  ieee: T. Ceylan and C. Yalcin, <i>Verteilte Simulation von mobilen Robotern mit
    EyeSim</i>. Paderborn University, 2008.
  mla: Ceylan, Toni, and Coni Yalcin. <i>Verteilte Simulation von Mobilen Robotern
    Mit EyeSim</i>. Paderborn University, 2008.
  short: T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim,
    Paderborn University, 2008.
date_created: 2019-07-10T11:03:45Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Verteilte Simulation von mobilen Robotern mit EyeSim
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10653'
author:
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Thiemo
  full_name: Gruber, Thiemo
  last_name: Gruber
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Jim
  full_name: Torresen, Jim
  last_name: Torresen
- first_name: Bernhard
  full_name: Sick, Bernhard
  last_name: Sick
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing
    Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic
    Hand Control. In: <i>IEEE Adaptive Hardware and Systems (AHS)</i>. IEEE; 2008:32-39.'
  apa: Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., &#38; Platzner,
    M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
    Prosthetic Hand Control. In <i>IEEE Adaptive Hardware and Systems (AHS)</i> (pp.
    32–39). IEEE.
  bibtex: '@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing
    Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic
    Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE},
    author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim
    and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }'
  chicago: Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick,
    and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers
    for Electromyographic Prosthetic Hand Control.” In <i>IEEE Adaptive Hardware and
    Systems (AHS)</i>, 32–39. IEEE, 2008.
  ieee: K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner,
    “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
    Prosthetic Hand Control,” in <i>IEEE Adaptive Hardware and Systems (AHS)</i>,
    2008, pp. 32–39.
  mla: Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers
    for Electromyographic Prosthetic Hand Control.” <i>IEEE Adaptive Hardware and
    Systems (AHS)</i>, IEEE, 2008, pp. 32–39.
  short: 'K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in:
    IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.'
date_created: 2019-07-10T11:13:13Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 32-39
publication: IEEE Adaptive Hardware and Systems (AHS)
publisher: IEEE
status: public
title: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic
  Prosthetic Hand Control
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '10656'
author:
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Jim
  full_name: Torresen, Jim
  last_name: Torresen
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware
    Architectures for Classification Tasks. In: <i>IEEE Intl. Conf. on Evolvable Systems
    (ICES)</i>. Vol 5216. LNCS. Springer; 2008:22-33.'
  apa: Glette, K., Torresen, J., Kaufmann, P., &#38; Platzner, M. (2008). A Comparison
    of Evolvable Hardware Architectures for Classification Tasks. In <i>IEEE Intl.
    Conf. on Evolvable Systems (ICES)</i> (Vol. 5216, pp. 22–33). Springer.
  bibtex: '@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A
    Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216},
    booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer},
    author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco},
    year={2008}, pages={22–33}, collection={LNCS} }'
  chicago: Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison
    of Evolvable Hardware Architectures for Classification Tasks.” In <i>IEEE Intl.
    Conf. on Evolvable Systems (ICES)</i>, 5216:22–33. LNCS. Springer, 2008.
  ieee: K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable
    Hardware Architectures for Classification Tasks,” in <i>IEEE Intl. Conf. on Evolvable
    Systems (ICES)</i>, 2008, vol. 5216, pp. 22–33.
  mla: Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for
    Classification Tasks.” <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, vol.
    5216, Springer, 2008, pp. 22–33.
  short: 'K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on
    Evolvable Systems (ICES), Springer, 2008, pp. 22–33.'
date_created: 2019-07-10T11:13:31Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: '      5216'
language:
- iso: eng
page: 22-33
publication: IEEE Intl. Conf. on Evolvable Systems (ICES)
publisher: Springer
series_title: LNCS
status: public
title: A Comparison of Evolvable Hardware Architectures for Classification Tasks
type: conference
user_id: '3118'
volume: 5216
year: '2008'
...
---
_id: '10669'
author:
- first_name: Markus
  full_name: Happe, Markus
  last_name: Happe
citation:
  ama: Happe M. <i>Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern</i>.
    Paderborn University; 2008.
  apa: Happe, M. (2008). <i>Parallelisierung und Hardware- / Software - Codesign von
    Partikelfiltern</i>. Paderborn University.
  bibtex: '@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign
    von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus},
    year={2008} }'
  chicago: Happe, Markus. <i>Parallelisierung Und Hardware- / Software - Codesign
    von Partikelfiltern</i>. Paderborn University, 2008.
  ieee: M. Happe, <i>Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern</i>.
    Paderborn University, 2008.
  mla: Happe, Markus. <i>Parallelisierung Und Hardware- / Software - Codesign von
    Partikelfiltern</i>. Paderborn University, 2008.
  short: M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern,
    Paderborn University, 2008.
date_created: 2019-07-10T11:15:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern
type: mastersthesis
user_id: '3118'
year: '2008'
...
---
_id: '10690'
author:
- first_name: Jim
  full_name: Torresen, Jim
  last_name: Torresen
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
citation:
  ama: Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial
    at Architecture of Computing Systems (ARCS). 2008.
  apa: Torresen, J., Glette, K., Platzner, M., &#38; Kaufmann, P. (2008). Evolvable
    Hardware - Tutorial at Architecture of Computing Systems (ARCS).
  bibtex: '@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware
    - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim
    and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }'
  chicago: Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable
    Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008.
  ieee: J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware
    - Tutorial at Architecture of Computing Systems (ARCS).” 2008.
  mla: Torresen, Jim, et al. <i>Evolvable Hardware - Tutorial at Architecture of Computing
    Systems (ARCS)</i>. 2008.
  short: J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).
date_created: 2019-07-10T11:29:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
status: public
title: Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)
type: preprint
user_id: '398'
year: '2008'
...
---
_id: '10691'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation
    of Modules in Cartesian Genetic Programming. In: <i>Genetic and Evolutionary Computation
    (GECCO)</i>. ACM Press; 2008:1219-1226.'
  apa: Kaufmann, P., &#38; Platzner, M. (2008). Advanced Techniques for the Creation
    and Propagation of Modules in Cartesian Genetic Programming. In <i>Genetic and
    Evolutionary Computation (GECCO)</i> (pp. 1219–1226). ACM Press.
  bibtex: '@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the
    Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic
    and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann,
    Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }'
  chicago: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation
    and Propagation of Modules in Cartesian Genetic Programming.” In <i>Genetic and
    Evolutionary Computation (GECCO)</i>, 1219–26. ACM Press, 2008.
  ieee: P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation
    of Modules in Cartesian Genetic Programming,” in <i>Genetic and Evolutionary Computation
    (GECCO)</i>, 2008, pp. 1219–1226.
  mla: Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and
    Propagation of Modules in Cartesian Genetic Programming.” <i>Genetic and Evolutionary
    Computation (GECCO)</i>, ACM Press, 2008, pp. 1219–26.
  short: 'P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO),
    ACM Press, 2008, pp. 1219–1226.'
date_created: 2019-07-10T11:29:57Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: 1219 - 1226
publication: Genetic and Evolutionary Computation (GECCO)
publisher: ACM Press
status: public
title: Advanced Techniques for the Creation and Propagation of Modules in Cartesian
  Genetic Programming
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '10696'
alternative_title:
- Multi-objective Optimizer IBEA for Digital Logic Design
author:
- first_name: Tobias
  full_name: Knieper, Tobias
  last_name: Knieper
citation:
  ama: Knieper T. <i>Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
    IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn University; 2008.
  apa: Knieper, T. (2008). <i>Implementierung und Bewertung des multikriteriellen
    Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf</i>. Paderborn
    University.
  bibtex: '@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen
    Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn
    University}, author={Knieper, Tobias}, year={2008} }'
  chicago: Knieper, Tobias. <i>Implementierung Und Bewertung Des Multikriteriellen
    Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn
    University, 2008.
  ieee: T. Knieper, <i>Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens
    IBEA für den automatisierten Schaltungsentwurf</i>. Paderborn University, 2008.
  mla: Knieper, Tobias. <i>Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
    IBEA Für Den Automatisierten Schaltungsentwurf</i>. Paderborn University, 2008.
  short: T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens
    IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.
date_created: 2019-07-10T11:30:22Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens
  IBEA für den automatisierten Schaltungsentwurf
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10718'
author:
- first_name: Jörg
  full_name: Niklas, Jörg
  last_name: Niklas
citation:
  ama: Niklas J. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme</i>.
    Paderborn University; 2008.
  apa: Niklas, J. (2008). <i>Eine Monitoring- und Debugging-Infrastruktur für hybride
    HW/SW-Systeme</i>. Paderborn University.
  bibtex: '@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur
    für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas,
    Jörg}, year={2008} }'
  chicago: Niklas, Jörg. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride
    HW/SW-Systeme</i>. Paderborn University, 2008.
  ieee: J. Niklas, <i>Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme</i>.
    Paderborn University, 2008.
  mla: Niklas, Jörg. <i>Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme</i>.
    Paderborn University, 2008.
  short: J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme,
    Paderborn University, 2008.
date_created: 2019-07-10T11:48:29Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10721'
author:
- first_name: Marco
  full_name: Östermann, Marco
  last_name: Östermann
citation:
  ama: Östermann M. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn University;
    2008.
  apa: Östermann, M. (2008). <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn
    University.
  bibtex: '@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU},
    publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }'
  chicago: Östermann, Marco. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn
    University, 2008.
  ieee: M. Östermann, <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn
    University, 2008.
  mla: Östermann, Marco. <i>Raytracing on a Custom Instruction Set CPU</i>. Paderborn
    University, 2008.
  short: M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University,
    2008.
date_created: 2019-07-10T11:52:51Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Raytracing on a Custom Instruction Set CPU
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10751'
author:
- first_name: Nico
  full_name: Westerheide, Nico
  last_name: Westerheide
citation:
  ama: Westerheide N. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>.
    Paderborn University; 2008.
  apa: Westerheide, N. (2008). <i>Design and Evaluation of MicroBlaze Multi-core Architectures</i>.
    Paderborn University.
  bibtex: '@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core
    Architectures}, publisher={Paderborn University}, author={Westerheide, Nico},
    year={2008} }'
  chicago: Westerheide, Nico. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>.
    Paderborn University, 2008.
  ieee: N. Westerheide, <i>Design and Evaluation of MicroBlaze Multi-core Architectures</i>.
    Paderborn University, 2008.
  mla: Westerheide, Nico. <i>Design and Evaluation of MicroBlaze Multi-Core Architectures</i>.
    Paderborn University, 2008.
  short: N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures,
    Paderborn University, 2008.
date_created: 2019-07-10T12:03:01Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Design and Evaluation of MicroBlaze Multi-core Architectures
type: bachelorsthesis
user_id: '3118'
year: '2008'
...
---
_id: '10778'
author:
- first_name: Hassan
  full_name: Ghasemzadeh Mohammadi, Hassan
  id: '61186'
  last_name: Ghasemzadeh Mohammadi
- first_name: Hamed
  full_name: Tabkhi, Hamed
  last_name: Tabkhi
- first_name: Seyed Ghassem
  full_name: Miremadi, Seyed Ghassem
  last_name: Miremadi
- first_name: Alireza
  full_name: Ejlali, Alireza
  last_name: Ejlali
citation:
  ama: 'Ghasemzadeh Mohammadi H, Tabkhi H, Miremadi SG, Ejlali A. A cost-effective
    error detection and roll-back recovery technique for embedded microprocessor control
    logic. In: <i>2008 International Conference on Microelectronics</i>. IEEE; 2008:444-447.
    doi:<a href="https://doi.org/10.1109/ICM.2008.5393497">10.1109/ICM.2008.5393497</a>'
  apa: Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., &#38; Ejlali, A. (2008).
    A cost-effective error detection and roll-back recovery technique for embedded
    microprocessor control logic. In <i>2008 International Conference on Microelectronics</i>
    (pp. 444–447). IEEE. <a href="https://doi.org/10.1109/ICM.2008.5393497">https://doi.org/10.1109/ICM.2008.5393497</a>
  bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Tabkhi_Miremadi_Ejlali_2008, title={A
    cost-effective error detection and roll-back recovery technique for embedded microprocessor
    control logic}, DOI={<a href="https://doi.org/10.1109/ICM.2008.5393497">10.1109/ICM.2008.5393497</a>},
    booktitle={2008 International Conference on Microelectronics}, publisher={IEEE},
    author={Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem
    and Ejlali, Alireza}, year={2008}, pages={444–447} }'
  chicago: Ghasemzadeh Mohammadi, Hassan, Hamed Tabkhi, Seyed Ghassem Miremadi, and
    Alireza Ejlali. “A Cost-Effective Error Detection and Roll-Back Recovery Technique
    for Embedded Microprocessor Control Logic.” In <i>2008 International Conference
    on Microelectronics</i>, 444–47. IEEE, 2008. <a href="https://doi.org/10.1109/ICM.2008.5393497">https://doi.org/10.1109/ICM.2008.5393497</a>.
  ieee: H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective
    error detection and roll-back recovery technique for embedded microprocessor control
    logic,” in <i>2008 International Conference on Microelectronics</i>, 2008, pp.
    444–447.
  mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Cost-Effective Error Detection and
    Roll-Back Recovery Technique for Embedded Microprocessor Control Logic.” <i>2008
    International Conference on Microelectronics</i>, IEEE, 2008, pp. 444–47, doi:<a
    href="https://doi.org/10.1109/ICM.2008.5393497">10.1109/ICM.2008.5393497</a>.
  short: 'H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008
    International Conference on Microelectronics, IEEE, 2008, pp. 444–447.'
date_created: 2019-07-10T12:11:35Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ICM.2008.5393497
extern: '1'
language:
- iso: eng
page: 444-447
publication: 2008 International Conference on Microelectronics
publisher: IEEE
status: public
title: A cost-effective error detection and roll-back recovery technique for embedded
  microprocessor control logic
type: conference
user_id: '3118'
year: '2008'
...
---
_id: '13629'
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore
    Arrays. In: <i>Proceedings of the International Symposium on Systems, Architectures,
    Modeling and Simulation (SAMOS)</i>. IEEE; 2008.'
  apa: Giefers, H., &#38; Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms
    on Softcore Arrays. In <i>Proceedings of the International Symposium on Systems,
    Architectures, Modeling and Simulation (SAMOS)</i>. IEEE.
  bibtex: '@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh
    Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium
    on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE},
    author={Giefers, Heiner and Platzner, Marco}, year={2008} }'
  chicago: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms
    on Softcore Arrays.” In <i>Proceedings of the International Symposium on Systems,
    Architectures, Modeling and Simulation (SAMOS)</i>. IEEE, 2008.
  ieee: H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore
    Arrays,” in <i>Proceedings of the International Symposium on Systems, Architectures,
    Modeling and Simulation (SAMOS)</i>, 2008.
  mla: Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms
    on Softcore Arrays.” <i>Proceedings of the International Symposium on Systems,
    Architectures, Modeling and Simulation (SAMOS)</i>, IEEE, 2008.
  short: 'H. Giefers, M. Platzner, in: Proceedings of the International Symposium
    on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.'
date_created: 2019-10-04T22:05:22Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the International Symposium on Systems, Architectures,
  Modeling and Simulation (SAMOS)
publisher: IEEE
status: public
title: Realizing Reconfigurable Mesh Algorithms on Softcore Arrays
type: conference
user_id: '398'
year: '2008'
...
---
_id: '13630'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. Communication and Synchronization in Multithreaded
    Reconfigurable Computing Systems. In: <i>Proceedings of the 8th International
    Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>.
    CSREA Press; 2008.'
  apa: Lübbers, E., &#38; Platzner, M. (2008). Communication and Synchronization in
    Multithreaded Reconfigurable Computing Systems. In <i>Proceedings of the 8th International
    Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>.
    CSREA Press.
  bibtex: '@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization
    in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of
    the 8th International Conference on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner,
    Marco}, year={2008} }'
  chicago: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in
    Multithreaded Reconfigurable Computing Systems.” In <i>Proceedings of the 8th
    International Conference on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>. CSREA Press, 2008.
  ieee: E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded
    Reconfigurable Computing Systems,” in <i>Proceedings of the 8th International
    Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    2008.
  mla: Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded
    Reconfigurable Computing Systems.” <i>Proceedings of the 8th International Conference
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press,
    2008.
  short: 'E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference
    on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.'
date_created: 2019-10-04T22:07:14Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 8th International Conference on Engineering of Reconfigurable
  Systems and Algorithms (ERSA)
publisher: CSREA Press
status: public
title: Communication and Synchronization in Multithreaded Reconfigurable Computing
  Systems
type: conference
user_id: '398'
year: '2008'
...