---
_id: '13631'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. A portable abstraction layer for hardware threads.
    In: <i>Proceedings of the 18th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. IEEE; 2008. doi:<a href="https://doi.org/10.1109/fpl.2008.4629901">10.1109/fpl.2008.4629901</a>'
  apa: Lübbers, E., &#38; Platzner, M. (2008). A portable abstraction layer for hardware
    threads. In <i>Proceedings of the 18th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. IEEE. <a href="https://doi.org/10.1109/fpl.2008.4629901">https://doi.org/10.1109/fpl.2008.4629901</a>
  bibtex: '@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer
    for hardware threads}, DOI={<a href="https://doi.org/10.1109/fpl.2008.4629901">10.1109/fpl.2008.4629901</a>},
    booktitle={Proceedings of the 18th International Conference on Field Programmable
    Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner,
    Marco}, year={2008} }'
  chicago: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware
    Threads.” In <i>Proceedings of the 18th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. IEEE, 2008. <a href="https://doi.org/10.1109/fpl.2008.4629901">https://doi.org/10.1109/fpl.2008.4629901</a>.
  ieee: E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,”
    in <i>Proceedings of the 18th International Conference on Field Programmable Logic
    and Applications (FPL)</i>, 2008.
  mla: Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware
    Threads.” <i>Proceedings of the 18th International Conference on Field Programmable
    Logic and Applications (FPL)</i>, IEEE, 2008, doi:<a href="https://doi.org/10.1109/fpl.2008.4629901">10.1109/fpl.2008.4629901</a>.
  short: 'E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference
    on Field Programmable Logic and Applications (FPL), IEEE, 2008.'
date_created: 2019-10-04T22:07:43Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpl.2008.4629901
language:
- iso: eng
publication: Proceedings of the 18th International Conference on Field Programmable
  Logic and Applications (FPL)
publication_identifier:
  isbn:
  - '9781424419609'
publication_status: published
publisher: IEEE
status: public
title: A portable abstraction layer for hardware threads
type: conference
user_id: '398'
year: '2008'
...
---
_id: '2364'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Robert
  full_name: Meiche, Robert
  last_name: Meiche
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware
    Accelerator for k-th Nearest Neighbor Thinning. In: <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.'
  apa: Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner,
    M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    245–251.
  bibtex: '@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008,
    title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers,
    Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251}
    }'
  chicago: Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian
    Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor
    Thinning.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.
  ieee: T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner,
    “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in <i>Proc. Int.
    Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008,
    pp. 245–251.
  mla: Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor
    Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>, CSREA Press, 2008, pp. 245–51.
  short: 'T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner,
    in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
    CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:33:32Z
date_updated: 2023-09-26T13:54:24Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-064-7
publisher: CSREA Press
quality_controlled: '1'
status: public
title: A Hardware Accelerator for k-th Nearest Neighbor Thinning
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '2372'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance
    monitoring and optimization of reconfigurable computers. In: <i>Many-Core and
    Reconfigurable Supercomputing Conference (MRSC)</i>. ; 2008.'
  apa: 'Schumacher, T., Plessl, C., &#38; Platzner, M. (2008). IMORC: An infrastructure
    for performance monitoring and optimization of reconfigurable computers. <i>Many-Core
    and Reconfigurable Supercomputing Conference (MRSC)</i>.'
  bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure
    for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core
    and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias
    and Plessl, Christian and Platzner, Marco}, year={2008} }'
  chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure
    for Performance Monitoring and Optimization of Reconfigurable Computers.” In <i>Many-Core
    and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.'
  ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for
    performance monitoring and optimization of reconfigurable computers,” 2008.'
  mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring
    and Optimization of Reconfigurable Computers.” <i>Many-Core and Reconfigurable
    Supercomputing Conference (MRSC)</i>, 2008.'
  short: 'T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable
    Supercomputing Conference (MRSC), 2008.'
date_created: 2018-04-17T12:05:28Z
date_updated: 2023-09-26T13:55:51Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- IP core
- interconnect
language:
- iso: eng
publication: Many-core and Reconfigurable Supercomputing Conference (MRSC)
quality_controlled: '1'
status: public
title: 'IMORC: An infrastructure for performance monitoring and optimization of reconfigurable
  computers'
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '10698'
author:
- first_name: Tobias
  full_name: Knieper, Tobias
  last_name: Knieper
- first_name: Bertrand
  full_name: Defo, Bertrand
  last_name: Defo
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital
    Hardware. In: <i>Biologically Inspired Collaborative Computing (BICC)</i>. Vol
    268. IFIP International Federation for Information Processing. Springer; 2008:213-222.
    doi:<a href="https://doi.org/10.1007/978-0-387-09655-1_19">10.1007/978-0-387-09655-1_19</a>'
  apa: Knieper, T., Defo, B., Kaufmann, P., &#38; Platzner, M. (2008). On Robust Evolution
    of Digital Hardware. <i>Biologically Inspired Collaborative Computing (BICC)</i>,
    <i>268</i>, 213–222. <a href="https://doi.org/10.1007/978-0-387-09655-1_19">https://doi.org/10.1007/978-0-387-09655-1_19</a>
  bibtex: '@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International
    Federation for Information Processing}, title={On Robust Evolution of Digital
    Hardware}, volume={268}, DOI={<a href="https://doi.org/10.1007/978-0-387-09655-1_19">10.1007/978-0-387-09655-1_19</a>},
    booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer},
    author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco},
    year={2008}, pages={213–222}, collection={IFIP International Federation for Information
    Processing} }'
  chicago: Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On
    Robust Evolution of Digital Hardware.” In <i>Biologically Inspired Collaborative
    Computing (BICC)</i>, 268:213–22. IFIP International Federation for Information
    Processing. Springer, 2008. <a href="https://doi.org/10.1007/978-0-387-09655-1_19">https://doi.org/10.1007/978-0-387-09655-1_19</a>.
  ieee: 'T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of
    Digital Hardware,” in <i>Biologically Inspired Collaborative Computing (BICC)</i>,
    2008, vol. 268, pp. 213–222, doi: <a href="https://doi.org/10.1007/978-0-387-09655-1_19">10.1007/978-0-387-09655-1_19</a>.'
  mla: Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” <i>Biologically
    Inspired Collaborative Computing (BICC)</i>, vol. 268, Springer, 2008, pp. 213–22,
    doi:<a href="https://doi.org/10.1007/978-0-387-09655-1_19">10.1007/978-0-387-09655-1_19</a>.
  short: 'T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired
    Collaborative Computing (BICC), Springer, 2008, pp. 213–222.'
date_created: 2019-07-10T11:38:02Z
date_updated: 2026-02-19T08:35:12Z
department:
- _id: '78'
doi: 10.1007/978-0-387-09655-1_19
intvolume: '       268'
language:
- iso: eng
page: 213-222
publication: Biologically Inspired Collaborative Computing (BICC)
publisher: Springer
series_title: IFIP International Federation for Information Processing
status: public
title: On Robust Evolution of Digital Hardware
type: conference
user_id: '14972'
volume: 268
year: '2008'
...
---
_id: '6508'
abstract:
- lang: eng
  text: 'In this paper, we present a framework that supports experimenting with evolutionary
    hardware design. We describe the framework''s modules for composing evolutionary
    optimizers and for setting up, controlling, and analyzing experiments. Two case
    studies demonstrate the usefulness of the framework: evolution of hash functions
    and evolution based on pre-engineered circuits.'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution.
    In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>.
    IEEE; 2007:447-454. doi:<a href="https://doi.org/10.1109/ahs.2007.73">10.1109/ahs.2007.73</a>'
  apa: 'Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware
    Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
    2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href="https://doi.org/10.1109/ahs.2007.73">https://doi.org/10.1109/ahs.2007.73</a>'
  bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework
    for Hardware Evolution}, DOI={<a href="https://doi.org/10.1109/ahs.2007.73">10.1109/ahs.2007.73</a>},
    booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)},
    publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454}
    }'
  chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
    Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems
    (AHS 2007)</i>, 447–54. IEEE, 2007. <a href="https://doi.org/10.1109/ahs.2007.73">https://doi.org/10.1109/ahs.2007.73</a>.'
  ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,”
    in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>,
    Edinburgh, UK, 2007, pp. 447–454.'
  mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
    Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
    2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href="https://doi.org/10.1109/ahs.2007.73">10.1109/ahs.2007.73</a>.'
  short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS 2007), IEEE, 2007, pp. 447–454.'
conference:
  end_date: 2007-08-08
  location: Edinburgh, UK
  name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
  start_date: 2007-08-05
date_created: 2019-01-08T09:52:43Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
doi: 10.1109/ahs.2007.73
keyword:
- integrated circuit design
- hardware evolution
- evolutionary hardware design
- evolutionary optimizers
- hash functions
- preengineered circuits
- Hardware
- Circuits
- Design optimization
- Visualization
- Genetic programming
- Genetic mutations
- Clustering algorithms
- Biological cells
- Field programmable gate arrays
- Routing
language:
- iso: eng
page: 447-454
publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
publication_identifier:
  isbn:
  - 076952866X
  - '9780769528663'
publication_status: published
publisher: IEEE
status: public
title: 'MOVES: A Modular Framework for Hardware Evolution'
type: conference
user_id: '3118'
year: '2007'
...
---
_id: '10623'
author:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
citation:
  ama: Beisel T. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion
    in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>. Paderborn
    University; 2007.
  apa: Beisel, T. (2007). <i>Entwurf und Evaluation eines parallelen Verfahrens zur
    Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen</i>.
    Paderborn University.
  bibtex: '@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens
    zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen},
    publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }'
  chicago: Beisel, Tobias. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur
    Bildrekonstruktion in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>.
    Paderborn University, 2007.
  ieee: T. Beisel, <i>Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion
    in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen</i>. Paderborn
    University, 2007.
  mla: Beisel, Tobias. <i>Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion
    in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen</i>. Paderborn
    University, 2007.
  short: T. Beisel, Entwurf Und Evaluation Eines Parallelen Verfahrens Zur Bildrekonstruktion
    in Der Positronen-Emissions-Tomographie Auf Multi-Core-Architekturen, Paderborn
    University, 2007.
date_created: 2019-07-10T09:36:57Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in
  der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen
type: mastersthesis
user_id: '3118'
year: '2007'
...
---
_id: '10625'
author:
- first_name: Neil
  full_name: Bergmann, Neil
  last_name: Bergmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Jürgen
  full_name: Teich, Jürgen
  last_name: Teich
citation:
  ama: Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial).
    <i>{EURASIP} Journal on Embedded Systems</i>. 2007;2007:1-2. doi:<a href="https://doi.org/10.1155/2007/28405">10.1155/2007/28405</a>
  apa: Bergmann, N., Platzner, M., &#38; Teich, J. (2007). Dynamically Reconfigurable
    Architectures (editorial). <i>{EURASIP} Journal on Embedded Systems</i>, <i>2007</i>,
    1–2. <a href="https://doi.org/10.1155/2007/28405">https://doi.org/10.1155/2007/28405</a>
  bibtex: '@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable
    Architectures (editorial)}, volume={2007}, DOI={<a href="https://doi.org/10.1155/2007/28405">10.1155/2007/28405</a>},
    journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business
    Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007},
    pages={1–2} }'
  chicago: 'Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable
    Architectures (Editorial).” <i>{EURASIP} Journal on Embedded Systems</i> 2007
    (2007): 1–2. <a href="https://doi.org/10.1155/2007/28405">https://doi.org/10.1155/2007/28405</a>.'
  ieee: N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures
    (editorial),” <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, pp. 1–2,
    2007.
  mla: Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).”
    <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, Springer Science+Business
    Media, 2007, pp. 1–2, doi:<a href="https://doi.org/10.1155/2007/28405">10.1155/2007/28405</a>.
  short: N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems
    2007 (2007) 1–2.
date_created: 2019-07-10T09:40:11Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1155/2007/28405
intvolume: '      2007'
language:
- iso: eng
page: 1-2
publication: '{EURASIP} Journal on Embedded Systems'
publisher: Springer Science+Business Media
status: public
title: Dynamically Reconfigurable Architectures (editorial)
type: journal_article
user_id: '398'
volume: 2007
year: '2007'
...
---
_id: '10643'
author:
- first_name: Toni
  full_name: Ceylan, Toni
  last_name: Ceylan
- first_name: Coni
  full_name: Yalcin, Coni
  last_name: Yalcin
citation:
  ama: Ceylan T, Yalcin C. <i>Distributed Simulation of Mobile Robots Using EyeSim</i>.
    Paderborn University; 2007.
  apa: Ceylan, T., &#38; Yalcin, C. (2007). <i>Distributed Simulation of mobile Robots
    using EyeSim</i>. Paderborn University.
  bibtex: '@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots
    using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin,
    Coni}, year={2007} }'
  chicago: Ceylan, Toni, and Coni Yalcin. <i>Distributed Simulation of Mobile Robots
    Using EyeSim</i>. Paderborn University, 2007.
  ieee: T. Ceylan and C. Yalcin, <i>Distributed Simulation of mobile Robots using
    EyeSim</i>. Paderborn University, 2007.
  mla: Ceylan, Toni, and Coni Yalcin. <i>Distributed Simulation of Mobile Robots Using
    EyeSim</i>. Paderborn University, 2007.
  short: T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim,
    Paderborn University, 2007.
date_created: 2019-07-10T11:03:44Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: Distributed Simulation of mobile Robots using EyeSim
type: bachelorsthesis
user_id: '3118'
year: '2007'
...
---
_id: '10646'
author:
- first_name: Klaus
  full_name: Danne, Klaus
  last_name: Danne
- first_name: Roland
  full_name: Mühlenbernd, Roland
  last_name: Mühlenbernd
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks
    on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>.
    2007;1(4):295-302. doi:<a href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>
  apa: Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2007). Server-based execution
    of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital
    Techniques</i>, <i>1</i>(4), 295–302. <a href="https://doi.org/10.1049/iet-cdt:20060186">https://doi.org/10.1049/iet-cdt:20060186</a>
  bibtex: '@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution
    of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={<a
    href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>},
    number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and
    Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }'
  chicago: 'Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution
    of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital
    Techniques</i> 1, no. 4 (2007): 295–302. <a href="https://doi.org/10.1049/iet-cdt:20060186">https://doi.org/10.1049/iet-cdt:20060186</a>.'
  ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic
    tasks on dynamically reconfigurable hardware,” <i>IET Computers Digital Techniques</i>,
    vol. 1, no. 4, pp. 295–302, 2007.
  mla: Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically
    Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i>, vol. 1, no.
    4, 2007, pp. 295–302, doi:<a href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>.
  short: K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1
    (2007) 295–302.
date_created: 2019-07-10T11:10:54Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1049/iet-cdt:20060186
intvolume: '         1'
issue: '4'
keyword:
- reconfigurable architectures
- resource allocation
- device reconfiguration time
- dynamic hardware reconfiguration
- dynamically reconfigurable hardware
- light-weight runtime system
- merge server distribute load
- periodic real-time tasks
- runtime system overheads
- schedulability analysis
- scheduling technique
- server-based execution
- synthesis tool flow
language:
- iso: eng
page: 295-302
publication: IET Computers Digital Techniques
publication_identifier:
  issn:
  - 1751-8601
status: public
title: Server-based execution of periodic tasks on dynamically reconfigurable hardware
type: journal_article
user_id: '3118'
volume: 1
year: '2007'
...
---
_id: '10647'
author:
- first_name: Bertrand
  full_name: Defo, Bertrand
  last_name: Defo
citation:
  ama: Defo B. <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated
    Circuit Design and Optimization</i>. Paderborn University; 2007.
  apa: Defo, B. (2007). <i>A Comparison of Multi-Objective Evolutionary Algorithms
    for Automated Circuit Design and Optimization</i>. Paderborn University.
  bibtex: '@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms
    for Automated Circuit Design and Optimization}, publisher={Paderborn University},
    author={Defo, Bertrand}, year={2007} }'
  chicago: Defo, Bertrand. <i>A Comparison of Multi-Objective Evolutionary Algorithms
    for Automated Circuit Design and Optimization</i>. Paderborn University, 2007.
  ieee: B. Defo, <i>A Comparison of Multi-Objective Evolutionary Algorithms for Automated
    Circuit Design and Optimization</i>. Paderborn University, 2007.
  mla: Defo, Bertrand. <i>A Comparison of Multi-Objective Evolutionary Algorithms
    for Automated Circuit Design and Optimization</i>. Paderborn University, 2007.
  short: B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated
    Circuit Design and Optimization, Paderborn University, 2007.
date_created: 2019-07-10T11:10:55Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit
  Design and Optimization
type: mastersthesis
user_id: '3118'
year: '2007'
...
---
_id: '10648'
author:
- first_name: Sven
  full_name: Döhre, Sven
  last_name: Döhre
citation:
  ama: Döhre S. <i>Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle
    Für Multi-FPGA Systeme</i>. Paderborn University; 2007.
  apa: Döhre, S. (2007). <i>Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle
    für Multi-FPGA Systeme</i>. Paderborn University.
  bibtex: '@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten
    Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University},
    author={Döhre, Sven}, year={2007} }'
  chicago: Döhre, Sven. <i>Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle
    Für Multi-FPGA Systeme</i>. Paderborn University, 2007.
  ieee: S. Döhre, <i>Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle
    für Multi-FPGA Systeme</i>. Paderborn University, 2007.
  mla: Döhre, Sven. <i>Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle
    Für Multi-FPGA Systeme</i>. Paderborn University, 2007.
  short: S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle
    Für Multi-FPGA Systeme, Paderborn University, 2007.
date_created: 2019-07-10T11:10:56Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle
  für Multi-FPGA Systeme
type: mastersthesis
user_id: '3118'
year: '2007'
...
---
_id: '10689'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Platzner M. Toward Self-adaptive Embedded Systems: Multi-objective
    Hardware Evolution. In: <i>Architecture of Computing Systems (ARCS)</i>. Vol 4415.
    LNCS. Springer; 2007:199-208.'
  apa: 'Kaufmann, P., &#38; Platzner, M. (2007). Toward Self-adaptive Embedded Systems:
    Multi-objective Hardware Evolution. In <i>Architecture of Computing Systems (ARCS)</i>
    (Vol. 4415, pp. 199–208). Springer.'
  bibtex: '@inproceedings{Kaufmann_Platzner_2007, series={LNCS}, title={Toward Self-adaptive
    Embedded Systems: Multi-objective Hardware Evolution}, volume={4415}, booktitle={Architecture
    of Computing Systems (ARCS)}, publisher={Springer}, author={Kaufmann, Paul and
    Platzner, Marco}, year={2007}, pages={199–208}, collection={LNCS} }'
  chicago: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems:
    Multi-Objective Hardware Evolution.” In <i>Architecture of Computing Systems (ARCS)</i>,
    4415:199–208. LNCS. Springer, 2007.'
  ieee: 'P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective
    Hardware Evolution,” in <i>Architecture of Computing Systems (ARCS)</i>, 2007,
    vol. 4415, pp. 199–208.'
  mla: 'Kaufmann, Paul, and Marco Platzner. “Toward Self-Adaptive Embedded Systems:
    Multi-Objective Hardware Evolution.” <i>Architecture of Computing Systems (ARCS)</i>,
    vol. 4415, Springer, 2007, pp. 199–208.'
  short: 'P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS),
    Springer, 2007, pp. 199–208.'
date_created: 2019-07-10T11:29:03Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
intvolume: '      4415'
language:
- iso: eng
page: 199-208
publication: Architecture of Computing Systems (ARCS)
publisher: Springer
series_title: LNCS
status: public
title: 'Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution'
type: conference
user_id: '3118'
volume: 4415
year: '2007'
...
---
_id: '10709'
alternative_title:
- k-th Nearest Neighbor VHDL- Implementation for Multi-objective Algorithm Diversity-preserving
  Mechanism Acceleration
author:
- first_name: Robert
  full_name: Meiche, Robert
  last_name: Meiche
citation:
  ama: Meiche R. <i>VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle
    Optimierungsalgorithmen</i>. Paderborn University; 2007.
  apa: Meiche, R. (2007). <i>VHDL-Implementierung eines Clustering-Verfahrens für
    multikriterielle Optimierungsalgorithmen</i>. Paderborn University.
  bibtex: '@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens
    für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University},
    author={Meiche, Robert}, year={2007} }'
  chicago: Meiche, Robert. <i>VHDL-Implementierung Eines Clustering-Verfahrens Für
    Multikriterielle Optimierungsalgorithmen</i>. Paderborn University, 2007.
  ieee: R. Meiche, <i>VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle
    Optimierungsalgorithmen</i>. Paderborn University, 2007.
  mla: Meiche, Robert. <i>VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle
    Optimierungsalgorithmen</i>. Paderborn University, 2007.
  short: R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle
    Optimierungsalgorithmen, Paderborn University, 2007.
date_created: 2019-07-10T11:43:33Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
title: VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen
type: bachelorsthesis
user_id: '3118'
year: '2007'
...
---
_id: '10728'
author:
- first_name: Waldemar
  full_name: Reisch, Waldemar
  last_name: Reisch
citation:
  ama: Reisch W. <i>Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare
    Betriebssystem ReconOS</i>. Paderborn University; 2007.
  apa: Reisch, W. (2007). <i>Bildverarbeitungs-Architekturen und -Bibliotheken für
    das rekonfigurierbare Betriebssystem ReconOS</i>. Paderborn University.
  bibtex: '@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken
    für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University},
    author={Reisch, Waldemar}, year={2007} }'
  chicago: Reisch, Waldemar. <i>Bildverarbeitungs-Architekturen Und -Bibliotheken
    Für Das Rekonfigurierbare Betriebssystem ReconOS</i>. Paderborn University, 2007.
  ieee: W. Reisch, <i>Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare
    Betriebssystem ReconOS</i>. Paderborn University, 2007.
  mla: Reisch, Waldemar. <i>Bildverarbeitungs-Architekturen Und -Bibliotheken Für
    Das Rekonfigurierbare Betriebssystem ReconOS</i>. Paderborn University, 2007.
  short: W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare
    Betriebssystem ReconOS, Paderborn University, 2007.
date_created: 2019-07-10T11:54:46Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare
  Betriebssystem ReconOS
type: mastersthesis
user_id: '3118'
year: '2007'
...
---
_id: '10729'
author:
- first_name: Eike
  full_name: Rethmeier, Eike
  last_name: Rethmeier
citation:
  ama: Rethmeier E. <i>Konzeption Und Implementierung Einer Microsoft Windows CE 5.0
    Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem</i>. Paderborn University;
    2007.
  apa: Rethmeier, E. (2007). <i>Konzeption und Implementierung einer Microsoft Windows
    CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem</i>. Paderborn
    University.
  bibtex: '@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft
    Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn
    University}, author={Rethmeier, Eike}, year={2007} }'
  chicago: Rethmeier, Eike. <i>Konzeption Und Implementierung Einer Microsoft Windows
    CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem</i>. Paderborn
    University, 2007.
  ieee: E. Rethmeier, <i>Konzeption und Implementierung einer Microsoft Windows CE
    5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem</i>. Paderborn
    University, 2007.
  mla: Rethmeier, Eike. <i>Konzeption Und Implementierung Einer Microsoft Windows
    CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem</i>. Paderborn
    University, 2007.
  short: E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0
    Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University,
    2007.
date_created: 2019-07-10T11:54:47Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für
  ein ARM-basiertes eingebettetes Rechnersystem
type: mastersthesis
user_id: '3118'
year: '2007'
...
---
_id: '10735'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Lübbers E, Kaufmann P, Platzner M. Accelerating the Cube Cut
    Problem with an FPGA-Augmented Compute Cluster. In: <i>Proceedings of the ParaFPGA
    Symposium, International Conference on Parallel Computing: Architectures, Algorithms
    and Applications (PARCO)</i>. Vol 15. Advances in Parallel Computing. IOS Press;
    2007:749-756.'
  apa: 'Schumacher, T., Lübbers, E., Kaufmann, P., &#38; Platzner, M. (2007). Accelerating
    the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In <i>Proceedings
    of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures,
    Algorithms and Applications (PARCO)</i> (Vol. 15, pp. 749–756). IOS Press.'
  bibtex: '@inproceedings{Schumacher_Lübbers_Kaufmann_Platzner_2007, series={Advances
    in Parallel Computing}, title={Accelerating the Cube Cut Problem with an FPGA-Augmented
    Compute Cluster}, volume={15}, booktitle={Proceedings of the ParaFPGA Symposium,
    International Conference on Parallel Computing: Architectures, Algorithms and
    Applications (PARCO)}, publisher={IOS Press}, author={Schumacher, Tobias and Lübbers,
    Enno and Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={749–756}, collection={Advances
    in Parallel Computing} }'
  chicago: 'Schumacher, Tobias, Enno Lübbers, Paul Kaufmann, and Marco Platzner. “Accelerating
    the Cube Cut Problem with an FPGA-Augmented Compute Cluster.” In <i>Proceedings
    of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures,
    Algorithms and Applications (PARCO)</i>, 15:749–56. Advances in Parallel Computing.
    IOS Press, 2007.'
  ieee: 'T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the
    Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in <i>Proceedings of
    the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures,
    Algorithms and Applications (PARCO)</i>, 2007, vol. 15, pp. 749–756.'
  mla: 'Schumacher, Tobias, et al. “Accelerating the Cube Cut Problem with an FPGA-Augmented
    Compute Cluster.” <i>Proceedings of the ParaFPGA Symposium, International Conference
    on Parallel Computing: Architectures, Algorithms and Applications (PARCO)</i>,
    vol. 15, IOS Press, 2007, pp. 749–56.'
  short: 'T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of
    the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures,
    Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.'
date_created: 2019-07-10T11:58:09Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
intvolume: '        15'
language:
- iso: eng
page: 749-756
publication: 'Proceedings of the ParaFPGA Symposium, International Conference on Parallel
  Computing: Architectures, Algorithms and Applications (PARCO)'
publisher: IOS Press
series_title: Advances in Parallel Computing
status: public
title: Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster
type: conference
user_id: '398'
volume: 15
year: '2007'
...
---
_id: '13627'
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Giefers H, Platzner M. A Many-Core Implementation Based on the Reconfigurable
    Mesh Model. In: <i>Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. IEEE; 2007. doi:<a href="https://doi.org/10.1109/fpl.2007.4380623">10.1109/fpl.2007.4380623</a>'
  apa: Giefers, H., &#38; Platzner, M. (2007). A Many-Core Implementation Based on
    the Reconfigurable Mesh Model. In <i>Proceedings of the 17th International Conference
    on Field Programmable Logic and Applications (FPL)</i>. IEEE. <a href="https://doi.org/10.1109/fpl.2007.4380623">https://doi.org/10.1109/fpl.2007.4380623</a>
  bibtex: '@inproceedings{Giefers_Platzner_2007, title={A Many-Core Implementation
    Based on the Reconfigurable Mesh Model}, DOI={<a href="https://doi.org/10.1109/fpl.2007.4380623">10.1109/fpl.2007.4380623</a>},
    booktitle={Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner,
    Marco}, year={2007} }'
  chicago: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based
    on the Reconfigurable Mesh Model.” In <i>Proceedings of the 17th International
    Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2007.
    <a href="https://doi.org/10.1109/fpl.2007.4380623">https://doi.org/10.1109/fpl.2007.4380623</a>.
  ieee: H. Giefers and M. Platzner, “A Many-Core Implementation Based on the Reconfigurable
    Mesh Model,” in <i>Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)</i>, 2007.
  mla: Giefers, Heiner, and Marco Platzner. “A Many-Core Implementation Based on the
    Reconfigurable Mesh Model.” <i>Proceedings of the 17th International Conference
    on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2007, doi:<a href="https://doi.org/10.1109/fpl.2007.4380623">10.1109/fpl.2007.4380623</a>.
  short: 'H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference
    on Field Programmable Logic and Applications (FPL), IEEE, 2007.'
date_created: 2019-10-04T21:57:25Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpl.2007.4380623
language:
- iso: eng
publication: Proceedings of the 17th International Conference on Field Programmable
  Logic and Applications (FPL)
publication_identifier:
  isbn:
  - '9781424410590'
  - '9781424410606'
publication_status: published
publisher: IEEE
status: public
title: A Many-Core Implementation Based on the Reconfigurable Mesh Model
type: conference
user_id: '398'
year: '2007'
...
---
_id: '13628'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads.
    In: <i>Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. IEEE; 2007. doi:<a href="https://doi.org/10.1109/fpl.2007.4380686">10.1109/fpl.2007.4380686</a>'
  apa: 'Lübbers, E., &#38; Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and
    Software Threads. In <i>Proceedings of the 17th International Conference on Field
    Programmable Logic and Applications (FPL)</i>. IEEE. <a href="https://doi.org/10.1109/fpl.2007.4380686">https://doi.org/10.1109/fpl.2007.4380686</a>'
  bibtex: '@inproceedings{Lübbers_Platzner_2007, title={ReconOS: An RTOS Supporting
    Hard-and Software Threads}, DOI={<a href="https://doi.org/10.1109/fpl.2007.4380686">10.1109/fpl.2007.4380686</a>},
    booktitle={Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner,
    Marco}, year={2007} }'
  chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and
    Software Threads.” In <i>Proceedings of the 17th International Conference on Field
    Programmable Logic and Applications (FPL)</i>. IEEE, 2007. <a href="https://doi.org/10.1109/fpl.2007.4380686">https://doi.org/10.1109/fpl.2007.4380686</a>.'
  ieee: 'E. Lübbers and M. Platzner, “ReconOS: An RTOS Supporting Hard-and Software
    Threads,” in <i>Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)</i>, 2007.'
  mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: An RTOS Supporting Hard-and Software
    Threads.” <i>Proceedings of the 17th International Conference on Field Programmable
    Logic and Applications (FPL)</i>, IEEE, 2007, doi:<a href="https://doi.org/10.1109/fpl.2007.4380686">10.1109/fpl.2007.4380686</a>.'
  short: 'E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference
    on Field Programmable Logic and Applications (FPL), IEEE, 2007.'
date_created: 2019-10-04T21:58:35Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/fpl.2007.4380686
language:
- iso: eng
publication: Proceedings of the 17th International Conference on Field Programmable
  Logic and Applications (FPL)
publication_identifier:
  isbn:
  - '9781424410590'
  - '9781424410606'
publication_status: published
publisher: IEEE
status: public
title: 'ReconOS: An RTOS Supporting Hard-and Software Threads'
type: conference
user_id: '398'
year: '2007'
...
---
_id: '2401'
abstract:
- lang: eng
  text: ' This paper presents a novel method for optimal temporal partitioning of
    sequential circuits for time-multiplexed reconfigurable architectures. The method
    bases on slowdown and retiming and maximizes the circuit''s performance during
    execution while restricting the size of the partitions to respect the resource
    constraints of the reconfigurable architecture. We provide a mixed integer linear
    program (MILP) formulation of the problem, which can be solved exactly. In contrast
    to related work, our approach optimizes performance directly, takes structural
    modifications of the circuit into account, and is extensible. We present the application
    of the new method to temporal partitioning for a coarse-grained reconfigurable
    architecture. '
author:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
citation:
  ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown
    and Retiming. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>.
    IEEE Computer Society; 2006:345-348. doi:<a href="https://doi.org/10.1109/FPT.2006.270344">10.1109/FPT.2006.270344</a>'
  apa: Plessl, C., Platzner, M., &#38; Thiele, L. (2006). Optimal Temporal Partitioning
    based on Slowdown and Retiming. In <i>Proc. Int. Conf. on Field Programmable Technology
    (ICFPT)</i> (pp. 345–348). IEEE Computer Society. <a href="https://doi.org/10.1109/FPT.2006.270344">https://doi.org/10.1109/FPT.2006.270344</a>
  bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning
    based on Slowdown and Retiming}, DOI={<a href="https://doi.org/10.1109/FPT.2006.270344">10.1109/FPT.2006.270344</a>},
    booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
    Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar},
    year={2006}, pages={345–348} }'
  chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal
    Partitioning Based on Slowdown and Retiming.” In <i>Proc. Int. Conf. on Field
    Programmable Technology (ICFPT)</i>, 345–48. IEEE Computer Society, 2006. <a href="https://doi.org/10.1109/FPT.2006.270344">https://doi.org/10.1109/FPT.2006.270344</a>.
  ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based
    on Slowdown and Retiming,” in <i>Proc. Int. Conf. on Field Programmable Technology
    (ICFPT)</i>, 2006, pp. 345–348.
  mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown
    and Retiming.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>,
    IEEE Computer Society, 2006, pp. 345–48, doi:<a href="https://doi.org/10.1109/FPT.2006.270344">10.1109/FPT.2006.270344</a>.
  short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable
    Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.'
date_created: 2018-04-17T13:43:21Z
date_updated: 2022-01-06T06:56:05Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2006.270344
keyword:
- temporal partitioning
- retiming
- ILP
page: 345-348
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: Optimal Temporal Partitioning based on Slowdown and Retiming
type: conference
user_id: '24135'
year: '2006'
...
---
_id: '10688'
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In:
    <i>Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)</i>.
    ; 2006.'
  apa: Kaufmann, P., &#38; Platzner, M. (2006). Multi-objective Intrinsic Hardware
    Evolution. In <i>Intl. Conf. Military Applications of Programmable Logic Devices
    (MAPLD)</i>.
  bibtex: '@inproceedings{Kaufmann_Platzner_2006, title={Multi-objective Intrinsic
    Hardware Evolution}, booktitle={Intl. Conf. Military Applications of Programmable
    Logic Devices (MAPLD)}, author={Kaufmann, Paul and Platzner, Marco}, year={2006}
    }'
  chicago: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware
    Evolution.” In <i>Intl. Conf. Military Applications of Programmable Logic Devices
    (MAPLD)</i>, 2006.
  ieee: P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,”
    in <i>Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)</i>,
    2006.
  mla: Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Hardware Evolution.”
    <i>Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)</i>,
    2006.
  short: 'P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable
    Logic Devices (MAPLD), 2006.'
date_created: 2019-07-10T11:28:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)
status: public
title: Multi-objective Intrinsic Hardware Evolution
type: conference
user_id: '3118'
year: '2006'
...