---
_id: '45916'
author:
- first_name: Nihal
full_name: Yadalam Murali Kumar, Nihal
last_name: Yadalam Murali Kumar
citation:
ama: Yadalam Murali Kumar N. Data Analytics for Predictive Maintenance of Time
Series Data. Paderborn University; 2023.
apa: Yadalam Murali Kumar, N. (2023). Data Analytics for Predictive Maintenance
of Time Series Data. Paderborn University.
bibtex: '@book{Yadalam Murali Kumar_2023, title={Data Analytics for Predictive Maintenance
of Time Series Data}, publisher={Paderborn University}, author={Yadalam Murali
Kumar, Nihal}, year={2023} }'
chicago: Yadalam Murali Kumar, Nihal. Data Analytics for Predictive Maintenance
of Time Series Data. Paderborn University, 2023.
ieee: N. Yadalam Murali Kumar, Data Analytics for Predictive Maintenance of Time
Series Data. Paderborn University, 2023.
mla: Yadalam Murali Kumar, Nihal. Data Analytics for Predictive Maintenance of
Time Series Data. Paderborn University, 2023.
short: N. Yadalam Murali Kumar, Data Analytics for Predictive Maintenance of Time
Series Data, Paderborn University, 2023.
date_created: 2023-07-09T12:59:28Z
date_updated: 2023-07-09T13:06:37Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publisher: Paderborn University
status: public
title: Data Analytics for Predictive Maintenance of Time Series Data
type: mastersthesis
user_id: '398'
year: '2023'
...
---
_id: '64114'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
last_name: Ahmed
- first_name: Muhammad
full_name: Awais, Muhammad
last_name: Awais
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Ahmed QA, Awais M, Platzner M. MAAS: Hiding Trojans in Approximate Circuits.
In: 2023 24th International Symposium on Quality Electronic Design (ISQED).
IEEE; 2023. doi:10.1109/isqed57927.2023.10129286'
apa: 'Ahmed, Q. A., Awais, M., & Platzner, M. (2023). MAAS: Hiding Trojans in
Approximate Circuits. 2023 24th International Symposium on Quality Electronic
Design (ISQED). https://doi.org/10.1109/isqed57927.2023.10129286'
bibtex: '@inproceedings{Ahmed_Awais_Platzner_2023, title={MAAS: Hiding Trojans in
Approximate Circuits}, DOI={10.1109/isqed57927.2023.10129286},
booktitle={2023 24th International Symposium on Quality Electronic Design (ISQED)},
publisher={IEEE}, author={Ahmed, Qazi Arbab and Awais, Muhammad and Platzner,
Marco}, year={2023} }'
chicago: 'Ahmed, Qazi Arbab, Muhammad Awais, and Marco Platzner. “MAAS: Hiding Trojans
in Approximate Circuits.” In 2023 24th International Symposium on Quality Electronic
Design (ISQED). IEEE, 2023. https://doi.org/10.1109/isqed57927.2023.10129286.'
ieee: 'Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate
Circuits,” 2023, doi: 10.1109/isqed57927.2023.10129286.'
mla: 'Ahmed, Qazi Arbab, et al. “MAAS: Hiding Trojans in Approximate Circuits.”
2023 24th International Symposium on Quality Electronic Design (ISQED),
IEEE, 2023, doi:10.1109/isqed57927.2023.10129286.'
short: 'Q.A. Ahmed, M. Awais, M. Platzner, in: 2023 24th International Symposium
on Quality Electronic Design (ISQED), IEEE, 2023.'
date_created: 2026-02-11T10:19:40Z
date_updated: 2026-02-11T10:20:32Z
department:
- _id: '78'
doi: 10.1109/isqed57927.2023.10129286
publication: 2023 24th International Symposium on Quality Electronic Design (ISQED)
publication_status: published
publisher: IEEE
status: public
title: 'MAAS: Hiding Trojans in Approximate Circuits'
type: conference
user_id: '64665'
year: '2023'
...
---
_id: '54244'
author:
- first_name: Salem
full_name: AlAidroos, Salem
last_name: AlAidroos
citation:
ama: AlAidroos S. Design and Implementation of a RadioML Demonstrator Based on
an RFSoC Platform. Paderborn University; 2023.
apa: AlAidroos, S. (2023). Design and Implementation of a RadioML Demonstrator
based on an RFSoC Platform. Paderborn University.
bibtex: '@book{AlAidroos_2023, title={Design and Implementation of a RadioML Demonstrator
based on an RFSoC Platform}, publisher={Paderborn University}, author={AlAidroos,
Salem}, year={2023} }'
chicago: AlAidroos, Salem. Design and Implementation of a RadioML Demonstrator
Based on an RFSoC Platform. Paderborn University, 2023.
ieee: S. AlAidroos, Design and Implementation of a RadioML Demonstrator based
on an RFSoC Platform. Paderborn University, 2023.
mla: AlAidroos, Salem. Design and Implementation of a RadioML Demonstrator Based
on an RFSoC Platform. Paderborn University, 2023.
short: S. AlAidroos, Design and Implementation of a RadioML Demonstrator Based on
an RFSoC Platform, Paderborn University, 2023.
date_created: 2024-05-13T13:59:16Z
date_updated: 2026-04-27T14:20:33Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform
type: mastersthesis
user_id: '55631'
year: '2023'
...
---
_id: '54243'
author:
- first_name: Marvin Osaretin
full_name: Oviasogie, Marvin Osaretin
last_name: Oviasogie
citation:
ama: Oviasogie MO. Demonstrator for Dataflow-Based DNN Acceleration for Vision
Applications on Platform FPGAs. Paderborn University; 2023.
apa: Oviasogie, M. O. (2023). Demonstrator for Dataflow-based DNN Acceleration
for Vision Applications on Platform FPGAs. Paderborn University.
bibtex: '@book{Oviasogie_2023, title={Demonstrator for Dataflow-based DNN Acceleration
for Vision Applications on Platform FPGAs}, publisher={Paderborn University},
author={Oviasogie, Marvin Osaretin}, year={2023} }'
chicago: Oviasogie, Marvin Osaretin. Demonstrator for Dataflow-Based DNN Acceleration
for Vision Applications on Platform FPGAs. Paderborn University, 2023.
ieee: M. O. Oviasogie, Demonstrator for Dataflow-based DNN Acceleration for Vision
Applications on Platform FPGAs. Paderborn University, 2023.
mla: Oviasogie, Marvin Osaretin. Demonstrator for Dataflow-Based DNN Acceleration
for Vision Applications on Platform FPGAs. Paderborn University, 2023.
short: M.O. Oviasogie, Demonstrator for Dataflow-Based DNN Acceleration for Vision
Applications on Platform FPGAs, Paderborn University, 2023.
date_created: 2024-05-13T13:58:31Z
date_updated: 2026-04-27T14:20:58Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on
Platform FPGAs
type: bachelorsthesis
user_id: '55631'
year: '2023'
...
---
_id: '54241'
author:
- first_name: Lucas David
full_name: Reuter, Lucas David
last_name: Reuter
citation:
ama: Reuter LD. Development of a Power Analysis Framework for Embedded FPGA Accelerators.
Paderborn University; 2023.
apa: Reuter, L. D. (2023). Development of a Power Analysis Framework for Embedded
FPGA Accelerators. Paderborn University.
bibtex: '@book{Reuter_2023, title={Development of a Power Analysis Framework for
Embedded FPGA Accelerators}, publisher={Paderborn University}, author={Reuter,
Lucas David}, year={2023} }'
chicago: Reuter, Lucas David. Development of a Power Analysis Framework for Embedded
FPGA Accelerators. Paderborn University, 2023.
ieee: L. D. Reuter, Development of a Power Analysis Framework for Embedded FPGA
Accelerators. Paderborn University, 2023.
mla: Reuter, Lucas David. Development of a Power Analysis Framework for Embedded
FPGA Accelerators. Paderborn University, 2023.
short: L.D. Reuter, Development of a Power Analysis Framework for Embedded FPGA
Accelerators, Paderborn University, 2023.
date_created: 2024-05-13T13:56:45Z
date_updated: 2026-04-27T14:21:10Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Development of a Power Analysis Framework for Embedded FPGA Accelerators
type: bachelorsthesis
user_id: '55631'
year: '2023'
...
---
_id: '29945'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Lucas David
full_name: Reuter, Lucas David
last_name: Reuter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Reuter LD, Platzner M. Search Space Characterization
for Approximate Logic Synthesis . In: 2022 59th ACM/IEEE Design Automation
Conference (DAC).'
apa: Witschen, L. M., Wiersema, T., Reuter, L. D., & Platzner, M. (n.d.). Search
Space Characterization for Approximate Logic Synthesis . 2022 59th ACM/IEEE
Design Automation Conference (DAC). 2022 59th ACM/IEEE Design Automation Conference
(DAC), San Francisco, USA.
bibtex: '@inproceedings{Witschen_Wiersema_Reuter_Platzner, title={Search Space Characterization
for Approximate Logic Synthesis }, booktitle={2022 59th ACM/IEEE Design Automation
Conference (DAC)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Reuter,
Lucas David and Platzner, Marco} }'
chicago: Witschen, Linus Matthias, Tobias Wiersema, Lucas David Reuter, and Marco
Platzner. “Search Space Characterization for Approximate Logic Synthesis .” In
2022 59th ACM/IEEE Design Automation Conference (DAC), n.d.
ieee: L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space
Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th
ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.
mla: Witschen, Linus Matthias, et al. “Search Space Characterization for Approximate
Logic Synthesis .” 2022 59th ACM/IEEE Design Automation Conference (DAC).
short: 'L.M. Witschen, T. Wiersema, L.D. Reuter, M. Platzner, in: 2022 59th ACM/IEEE
Design Automation Conference (DAC), n.d.'
conference:
end_date: 2022-07-14
location: San Francisco, USA
name: 2022 59th ACM/IEEE Design Automation Conference (DAC)
start_date: 2022-07-10
date_created: 2022-02-22T07:51:38Z
date_updated: 2022-02-22T07:51:42Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
publication: 2022 59th ACM/IEEE Design Automation Conference (DAC)
publication_status: accepted
status: public
title: 'Search Space Characterization for Approximate Logic Synthesis '
type: conference
user_id: '49051'
year: '2022'
...
---
_id: '29865'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Artmann M, Platzner M. MUSCAT: MUS-based Circuit
Approximation Technique. In: Design, Automation and Test in Europe (DATE).'
apa: 'Witschen, L. M., Wiersema, T., Artmann, M., & Platzner, M. (n.d.). MUSCAT:
MUS-based Circuit Approximation Technique. Design, Automation and Test in Europe
(DATE). Design, Automation and Test in Europe (DATE), Online.'
bibtex: '@inproceedings{Witschen_Wiersema_Artmann_Platzner, title={MUSCAT: MUS-based
Circuit Approximation Technique}, booktitle={Design, Automation and Test in Europe
(DATE)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias
and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Matthias Artmann, and Marco
Platzner. “MUSCAT: MUS-Based Circuit Approximation Technique.” In Design, Automation
and Test in Europe (DATE), n.d.'
ieee: 'L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based
Circuit Approximation Technique,” presented at the Design, Automation and Test
in Europe (DATE), Online.'
mla: 'Witschen, Linus Matthias, et al. “MUSCAT: MUS-Based Circuit Approximation
Technique.” Design, Automation and Test in Europe (DATE).'
short: 'L.M. Witschen, T. Wiersema, M. Artmann, M. Platzner, in: Design, Automation
and Test in Europe (DATE), n.d.'
conference:
location: Online
name: Design, Automation and Test in Europe (DATE)
date_created: 2022-02-16T16:22:23Z
date_updated: 2022-02-22T07:52:01Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Design, Automation and Test in Europe (DATE)
publication_status: accepted
status: public
title: 'MUSCAT: MUS-based Circuit Approximation Technique'
type: conference
user_id: '49051'
year: '2022'
...
---
_id: '30971'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Platzner M. Integrating Safety Guarantees into the Learning Classifier
System XCS. In: Applications of Evolutionary Computation, EvoApplications 2022,
Proceedings. Vol 13224. Lecture Notes in Computer Science. Springer International
Publishing; 2022:386-401. doi:10.1007/978-3-031-02462-7_25'
apa: Hansmeier, T., & Platzner, M. (2022). Integrating Safety Guarantees into
the Learning Classifier System XCS. Applications of Evolutionary Computation,
EvoApplications 2022, Proceedings, 13224, 386–401. https://doi.org/10.1007/978-3-031-02462-7_25
bibtex: '@inproceedings{Hansmeier_Platzner_2022, series={Lecture Notes in Computer
Science}, title={Integrating Safety Guarantees into the Learning Classifier System
XCS}, volume={13224}, DOI={10.1007/978-3-031-02462-7_25},
booktitle={Applications of Evolutionary Computation, EvoApplications 2022, Proceedings},
publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner,
Marco}, year={2022}, pages={386–401}, collection={Lecture Notes in Computer Science}
}'
chicago: Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into
the Learning Classifier System XCS.” In Applications of Evolutionary Computation,
EvoApplications 2022, Proceedings, 13224:386–401. Lecture Notes in Computer
Science. Springer International Publishing, 2022. https://doi.org/10.1007/978-3-031-02462-7_25.
ieee: 'T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning
Classifier System XCS,” in Applications of Evolutionary Computation, EvoApplications
2022, Proceedings, Madrid, 2022, vol. 13224, pp. 386–401, doi: 10.1007/978-3-031-02462-7_25.'
mla: Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the
Learning Classifier System XCS.” Applications of Evolutionary Computation,
EvoApplications 2022, Proceedings, vol. 13224, Springer International Publishing,
2022, pp. 386–401, doi:10.1007/978-3-031-02462-7_25.
short: 'T. Hansmeier, M. Platzner, in: Applications of Evolutionary Computation,
EvoApplications 2022, Proceedings, Springer International Publishing, 2022, pp.
386–401.'
conference:
end_date: 2022-04-22
location: Madrid
name: 25th International Conference on Applications of Evolutionary Computation,
EvoApplications 2022
start_date: 2022-04-20
date_created: 2022-04-28T09:42:33Z
date_updated: 2022-04-28T10:24:18Z
department:
- _id: '78'
doi: 10.1007/978-3-031-02462-7_25
intvolume: ' 13224'
language:
- iso: eng
page: 386-401
project:
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
- _id: '1'
name: 'SFB 901: SFB 901'
publication: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings
publication_identifier:
isbn:
- '9783031024610'
- '9783031024627'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer International Publishing
series_title: Lecture Notes in Computer Science
status: public
title: Integrating Safety Guarantees into the Learning Classifier System XCS
type: conference
user_id: '49992'
volume: 13224
year: '2022'
...
---
_id: '32855'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Clausing L, Platzner M. ReconOS64: A Hardware Operating System for Modern
Platform FPGAs with 64-Bit Support. In: 2022 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2022:120-127. doi:10.1109/ipdpsw55747.2022.00029'
apa: 'Clausing, L., & Platzner, M. (2022). ReconOS64: A Hardware Operating System
for Modern Platform FPGAs with 64-Bit Support. 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 120–127. https://doi.org/10.1109/ipdpsw55747.2022.00029'
bibtex: '@inproceedings{Clausing_Platzner_2022, title={ReconOS64: A Hardware Operating
System for Modern Platform FPGAs with 64-Bit Support}, DOI={10.1109/ipdpsw55747.2022.00029},
booktitle={2022 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Clausing, Lennart and Platzner,
Marco}, year={2022}, pages={120–127} }'
chicago: 'Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating
System for Modern Platform FPGAs with 64-Bit Support.” In 2022 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), 120–27.
IEEE, 2022. https://doi.org/10.1109/ipdpsw55747.2022.00029.'
ieee: 'L. Clausing and M. Platzner, “ReconOS64: A Hardware Operating System for
Modern Platform FPGAs with 64-Bit Support,” in 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), Lyon, France, 2022,
pp. 120–127, doi: 10.1109/ipdpsw55747.2022.00029.'
mla: 'Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System
for Modern Platform FPGAs with 64-Bit Support.” 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–27,
doi:10.1109/ipdpsw55747.2022.00029.'
short: 'L. Clausing, M. Platzner, in: 2022 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–127.'
conference:
end_date: 2022-06-03
location: ' Lyon, France'
name: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW)
start_date: 2022-05-30
date_created: 2022-08-16T09:58:34Z
date_updated: 2022-11-18T09:36:00Z
department:
- _id: '78'
doi: 10.1109/ipdpsw55747.2022.00029
language:
- iso: eng
page: 120-127
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: 2022 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
eisbn:
- 978-1-6654-9747-3
publication_status: published
publisher: IEEE
status: public
title: 'ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit
Support'
type: conference
user_id: '477'
year: '2022'
...
---
_id: '33253'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Mathis
full_name: Brede, Mathis
last_name: Brede
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Brede M, Platzner M. XCS on Embedded Systems: An Analysis of
Execution Profiles and Accelerated Classifier Deletion. In: GECCO ’22: Proceedings
of the Genetic and Evolutionary Computation Conference Companion. Association
for Computing Machinery (ACM); 2022:2071-2079. doi:10.1145/3520304.3533977'
apa: 'Hansmeier, T., Brede, M., & Platzner, M. (2022). XCS on Embedded Systems:
An Analysis of Execution Profiles and Accelerated Classifier Deletion. GECCO
’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion,
2071–2079. https://doi.org/10.1145/3520304.3533977'
bibtex: '@inproceedings{Hansmeier_Brede_Platzner_2022, place={New York, NY, United
States}, title={XCS on Embedded Systems: An Analysis of Execution Profiles and
Accelerated Classifier Deletion}, DOI={10.1145/3520304.3533977},
booktitle={GECCO ’22: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Brede, Mathis and Platzner, Marco}, year={2022}, pages={2071–2079}
}'
chicago: 'Hansmeier, Tim, Mathis Brede, and Marco Platzner. “XCS on Embedded Systems:
An Analysis of Execution Profiles and Accelerated Classifier Deletion.” In GECCO
’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion,
2071–79. New York, NY, United States: Association for Computing Machinery (ACM),
2022. https://doi.org/10.1145/3520304.3533977.'
ieee: 'T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis
of Execution Profiles and Accelerated Classifier Deletion,” in GECCO ’22: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Boston,
MA, USA, 2022, pp. 2071–2079, doi: 10.1145/3520304.3533977.'
mla: 'Hansmeier, Tim, et al. “XCS on Embedded Systems: An Analysis of Execution
Profiles and Accelerated Classifier Deletion.” GECCO ’22: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for
Computing Machinery (ACM), 2022, pp. 2071–79, doi:10.1145/3520304.3533977.'
short: 'T. Hansmeier, M. Brede, M. Platzner, in: GECCO ’22: Proceedings of the Genetic
and Evolutionary Computation Conference Companion, Association for Computing Machinery
(ACM), New York, NY, United States, 2022, pp. 2071–2079.'
conference:
end_date: 2022-07-13
location: Boston, MA, USA
name: International Workshop on Learning Classifier Systems (IWLCS 2022)
start_date: 2022-07-09
date_created: 2022-09-02T11:47:17Z
date_updated: 2022-11-18T10:13:22Z
department:
- _id: '78'
doi: 10.1145/3520304.3533977
language:
- iso: eng
page: 2071-2079
place: New York, NY, United States
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
publication: 'GECCO ''22: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: 'XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated
Classifier Deletion'
type: conference
user_id: '477'
year: '2022'
...
---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '29541'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated
ROS 2 Applications. Published online 2022.'
apa: 'Lienen, C., & Platzner, M. (2022). ReconROS Executor: Event-Driven
Programming of FPGA-accelerated ROS 2 Applications.'
bibtex: '@article{Lienen_Platzner_2022, title={ReconROS Executor: Event-Driven Programming
of FPGA-accelerated ROS 2 Applications}, author={Lienen, Christian and Platzner,
Marco}, year={2022} }'
chicago: 'Lienen, Christian, and Marco Platzner. “ReconROS Executor: Event-Driven
Programming of FPGA-Accelerated ROS 2 Applications,” 2022.'
ieee: 'C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of
FPGA-accelerated ROS 2 Applications.” 2022.'
mla: 'Lienen, Christian, and Marco Platzner. ReconROS Executor: Event-Driven
Programming of FPGA-Accelerated ROS 2 Applications. 2022.'
short: C. Lienen, M. Platzner, (2022).
date_created: 2022-01-26T08:52:20Z
date_updated: 2022-01-28T08:30:16Z
department:
- _id: '78'
language:
- iso: eng
main_file_link:
- url: https://arxiv.org/abs/2201.07454
status: public
title: 'ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications'
type: preprint
user_id: '60323'
year: '2022'
...
---
_id: '34007'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications
using ReconROS.
apa: Lienen, C., & Platzner, M. (n.d.). Task Mapping for Hardware-Accelerated
Robotics Applications using ReconROS. 2022 Sixth IEEE International Conference
on Robotic Computing (IRC) , Neaples, Italy.
bibtex: '@inproceedings{Lienen_Platzner, title={Task Mapping for Hardware-Accelerated
Robotics Applications using ReconROS}, author={Lienen, Christian and Platzner,
Marco} }'
chicago: Lienen, Christian, and Marco Platzner. “Task Mapping for Hardware-Accelerated
Robotics Applications Using ReconROS,” n.d.
ieee: C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics
Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference
on Robotic Computing (IRC) , Neaples, Italy.
mla: Lienen, Christian, and Marco Platzner. Task Mapping for Hardware-Accelerated
Robotics Applications Using ReconROS.
short: 'C. Lienen, M. Platzner, in: n.d.'
conference:
location: Neaples, Italy
name: '2022 Sixth IEEE International Conference on Robotic Computing (IRC) '
date_created: 2022-11-04T09:26:42Z
date_updated: 2022-11-04T09:26:47Z
department:
- _id: '78'
language:
- iso: eng
publication_status: accepted
status: public
title: Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS
type: conference
user_id: '60323'
year: '2022'
...
---
_id: '34005'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics
Applications. In: 2022 25th Euromicro Conference on Digital System Design (DSD).
doi:10.1109/DSD57027.2022.00088'
apa: Lienen, C., & Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications. 2022 25th Euromicro Conference on Digital System
Design (DSD). 25th Euromicro Conference on Digital System Design (DSD), Maspalomas,
Gran Canaria, Spain. https://doi.org/10.1109/DSD57027.2022.00088
bibtex: '@inproceedings{Lienen_Platzner, title={Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications}, DOI={10.1109/DSD57027.2022.00088},
booktitle={2022 25th Euromicro Conference on Digital System Design (DSD)}, author={Lienen,
Christian and Platzner, Marco} }'
chicago: Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated
ROS 2 Robotics Applications.” In 2022 25th Euromicro Conference on Digital
System Design (DSD), n.d. https://doi.org/10.1109/DSD57027.2022.00088.
ieee: 'C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital
System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: 10.1109/DSD57027.2022.00088.'
mla: Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated
ROS 2 Robotics Applications.” 2022 25th Euromicro Conference on Digital System
Design (DSD), doi:10.1109/DSD57027.2022.00088.
short: 'C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System
Design (DSD), n.d.'
conference:
location: Maspalomas, Gran Canaria, Spain
name: 25th Euromicro Conference on Digital System Design (DSD)
date_created: 2022-11-04T09:24:47Z
date_updated: 2023-01-06T06:38:27Z
department:
- _id: '78'
doi: 10.1109/DSD57027.2022.00088
language:
- iso: eng
publication: 2022 25th Euromicro Conference on Digital System Design (DSD)
publication_status: accepted
status: public
title: Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
type: conference
user_id: '60323'
year: '2022'
...
---
_id: '34041'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. Frameworks and Methodologies for Search-Based Approximate Logic
Synthesis.; 2022. doi:10.17619/UNIPB/1-1649
apa: Witschen, L. M. (2022). Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. https://doi.org/10.17619/UNIPB/1-1649
bibtex: '@book{Witschen_2022, title={Frameworks and Methodologies for Search-based
Approximate Logic Synthesis}, DOI={10.17619/UNIPB/1-1649},
author={Witschen, Linus Matthias}, year={2022} }'
chicago: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis, 2022. https://doi.org/10.17619/UNIPB/1-1649.
ieee: L. M. Witschen, Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. 2022.
mla: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis. 2022, doi:10.17619/UNIPB/1-1649.
short: L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate
Logic Synthesis, 2022.
date_created: 2022-11-09T06:26:22Z
date_updated: 2023-01-19T06:41:22Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1649
language:
- iso: eng
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Frameworks and Methodologies for Search-based Approximate Logic Synthesis
type: dissertation
user_id: '15504'
year: '2022'
...
---
_id: '32342'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level
Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022);
2022.'
apa: Ahmed, Q. A., & Platzner, M. (2022). On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium
on VLSI Aliathon Resort, Pafos, Cyprus.
bibtex: '@inproceedings{Ahmed_Platzner_2022, place={Pafos, Cyprus}, title={On the
Detection and Circumvention of Bitstream-Level Trojans in FPGAs}, publisher={IEEE
Computer Society Annual Symposium on VLSI (ISVLSI,2022)}, author={Ahmed, Qazi
Arbab and Platzner, Marco}, year={2022} }'
chicago: 'Ahmed, Qazi Arbab, and Marco Platzner. “On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs.” Pafos, Cyprus: IEEE Computer Society Annual
Symposium on VLSI (ISVLSI,2022), 2022.'
ieee: Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level
Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on
VLSI Aliathon Resort, Pafos, Cyprus, 2022.
mla: Ahmed, Qazi Arbab, and Marco Platzner. On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium
on VLSI (ISVLSI,2022), 2022.
short: 'Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI
(ISVLSI,2022), Pafos, Cyprus, 2022.'
conference:
end_date: July 6, 2022
location: Pafos, Cyprus
name: IEEE Computer Society Annual Symposium on VLSI Aliathon Resort,
start_date: ' July 4, 2022'
date_created: 2022-07-12T19:56:48Z
date_updated: 2023-04-19T15:04:30Z
department:
- _id: '78'
language:
- iso: eng
place: Pafos, Cyprus
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
publisher: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)
status: public
title: On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs
type: conference
user_id: '72764'
year: '2022'
...
---
_id: '33990'
abstract:
- lang: eng
text: Deep neural networks (DNNs) are penetrating into a broad spectrum of applications
and replacing manual algorithmic implementations, including the radio frequency
communications domain with classical signal processing algorithms. However, the
high throughput (gigasamples per second) and low latency requirements of this
application domain pose a significant hurdle for adopting computationally demanding
DNNs. In this article, we explore highly specialized DNN inference accelerator
approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification.
Using an automated end-to-end flow for the generation of the FPGA solution, we
can easily explore a spectrum of solutions that optimize for different design
targets, including accuracy, power efficiency, resources, throughput, and latency.
By leveraging reduced precision arithmetic and customized streaming dataflow,
we demonstrate a solution that meets the application requirements and outperforms
alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded
graphics processing units (GPUs), we measure >10x higher throughput and >100x
lower latency under comparable accuracy and power envelopes.
author:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Yaman
full_name: Umuroglu, Yaman
last_name: Umuroglu
- first_name: Alessandro
full_name: Pappalardo, Alessandro
last_name: Pappalardo
- first_name: Michaela
full_name: Blott, Michaela
last_name: Blott
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN:
Enabling Future RF Applications With FPGA Streaming Architectures. IEEE Micro.
2022;42(6):125-133. doi:10.1109/MM.2022.3202091'
apa: 'Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., & Platzner, M.
(2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming
Architectures. IEEE Micro, 42(6), 125–133. https://doi.org/10.1109/MM.2022.3202091'
bibtex: '@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML
Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures},
volume={42}, DOI={10.1109/MM.2022.3202091},
number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and
Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco},
year={2022}, pages={125–133} }'
chicago: 'Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott,
and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With
FPGA Streaming Architectures.” IEEE Micro 42, no. 6 (2022): 125–33. https://doi.org/10.1109/MM.2022.3202091.'
ieee: 'F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML
Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,”
IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi: 10.1109/MM.2022.3202091.'
mla: 'Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications
With FPGA Streaming Architectures.” IEEE Micro, vol. 42, no. 6, IEEE, 2022,
pp. 125–33, doi:10.1109/MM.2022.3202091.'
short: F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro
42 (2022) 125–133.
date_created: 2022-11-03T14:42:16Z
date_updated: 2023-04-04T15:09:17Z
department:
- _id: '78'
doi: 10.1109/MM.2022.3202091
intvolume: ' 42'
issue: '6'
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9933377
page: 125-133
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: IEEE Micro
publication_status: published
publisher: IEEE
status: public
title: 'RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures'
type: journal_article
user_id: '55631'
volume: 42
year: '2022'
...
---
_id: '45715'
author:
- first_name: Vanessa Ingrid
full_name: Tcheussi Ngayap, Vanessa Ingrid
last_name: Tcheussi Ngayap
citation:
ama: Tcheussi Ngayap VI. FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators.; 2022.
apa: Tcheussi Ngayap, V. I. (2022). FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators.
bibtex: '@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022}
}'
chicago: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core
Processor with Hardware Accelerators, 2022.
ieee: V. I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with
Hardware Accelerators. 2022.
mla: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators. 2022.
short: V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators, 2022.
date_created: 2023-06-22T12:04:57Z
date_updated: 2023-06-22T12:07:53Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators
type: mastersthesis
user_id: '74287'
year: '2022'
...
---
_id: '45914'
author:
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
citation:
ama: Manjunatha S. Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance. Paderborn University ; 2022.
apa: Manjunatha, S. (2022). Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance. Paderborn University .
bibtex: '@book{Manjunatha_2022, title={Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance}, publisher={Paderborn University
}, author={Manjunatha, Suraj}, year={2022} }'
chicago: Manjunatha, Suraj. Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance. Paderborn University , 2022.
ieee: S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance. Paderborn University , 2022.
mla: Manjunatha, Suraj. Dealing With Pre-Processing And Feature Extraction Of
Time-Series Data In Predictive Maintenance. Paderborn University , 2022.
short: S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance, Paderborn University , 2022.
date_created: 2023-07-09T12:54:08Z
date_updated: 2023-07-09T13:05:11Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publisher: 'Paderborn University '
status: public
supervisor:
- first_name: 'Marco '
full_name: 'Platzner, Marco '
last_name: Platzner
title: Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive
Maintenance
type: mastersthesis
user_id: '398'
year: '2022'
...
---
_id: '45915'
author:
- first_name: Parvinder
full_name: Kaur , Parvinder
last_name: 'Kaur '
citation:
ama: Kaur P. Analysis of Time-Series Classification in Conditional Monitoring
Systems.; 2022.
apa: Kaur , P. (2022). Analysis of Time-Series Classification in Conditional
Monitoring Systems.
bibtex: '@book{Kaur _2022, place={Paderborn University }, title={Analysis of Time-Series
Classification in Conditional Monitoring Systems}, author={Kaur , Parvinder},
year={2022} }'
chicago: Kaur , Parvinder. Analysis of Time-Series Classification in Conditional
Monitoring Systems. Paderborn University , 2022.
ieee: P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring
Systems. Paderborn University , 2022.
mla: Kaur , Parvinder. Analysis of Time-Series Classification in Conditional
Monitoring Systems. 2022.
short: P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring
Systems, Paderborn University , 2022.
date_created: 2023-07-09T12:58:06Z
date_updated: 2023-07-09T13:05:55Z
department:
- _id: '78'
language:
- iso: eng
place: 'Paderborn University '
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: Analysis of Time-Series Classification in Conditional Monitoring Systems
type: mastersthesis
user_id: '398'
year: '2022'
...