---
_id: '2432'
abstract:
- lang: eng
text: In this paper, we present the analysis of applications from the domain of
handheld and wearable computing. This analysis is the first step to derive and
evaluate design parameters for dynamically reconfigurable processors. We discuss
the selection of representative benchmarks for handhelds and wearables and group
the applications into multimedia, communications, and cryptography programs. We
simulate the applications on a cycle-accurate processor simulator and gather statistical
data such as instruction mix, cache hit rates and memory requirements for an embedded
processor model. A breakdown of the executed cycles into different functions identifies
the most compute-intensive code sections - the kernels. Then, we analyze the applications
and discuss parameters that strongly influence the design of dynamically reconfigurable
processors. Finally, we outline the construction of a parameterizable simulation
model for a reconfigurable unit that is attached to a processor core.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
- first_name: Gerhard
full_name: Tröster, Gerhard
last_name: Tröster
citation:
ama: 'Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors
for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology:
FPGAs and Reconfigurable Processors for Computing and Communications III.
Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376'
apa: 'Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001).
Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376'
bibtex: '@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc.
SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application
Analysis}, volume={4525}, DOI={10.1117/12.434376},
booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for
Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and
Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146},
collection={Proc. SPIE} }'
chicago: 'Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard
Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”
In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.'
ieee: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable
Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, vol. 4525, pp. 135–146.'
mla: 'Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables:
Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable
Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46,
doi:10.1117/12.434376.'
short: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, pp. 135–146.'
date_created: 2018-04-17T15:51:39Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
doi: 10.1117/12.434376
intvolume: ' 4525'
keyword:
- benchmark
page: 135-146
publication: 'Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III'
series_title: Proc. SPIE
status: public
title: 'Reconfigurable Processors for Handhelds and Wearables: Application Analysis'
type: conference
user_id: '24135'
volume: 4525
year: '2001'
...
---
_id: '10713'
author:
- first_name: Oskar
full_name: Mencer, Oskar
last_name: Mencer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Martin
full_name: Morf, Martin
last_name: Morf
- first_name: Michael
full_name: J. Flynn, Michael
last_name: J. Flynn
citation:
ama: Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers
for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration
({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835
apa: Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented
domain specific compilers for programming FPGAs. {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835
bibtex: '@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain
specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835},
number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI})
Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn,
Michael}, year={2001}, pages={205–210} }'
chicago: 'Mencer, Oskar, Marco Platzner, Martin Morf, and Michael J. Flynn. “Object-Oriented
Domain Specific Compilers for Programming FPGAs.” {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems 9, no. 1 (2001): 205–10. https://doi.org/10.1109/92.920835.'
ieee: O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain
specific compilers for programming FPGAs,” {IEEE} Transactions on Very Large
Scale Integration ({VLSI}) Systems, vol. 9, no. 1, pp. 205–210, 2001.
mla: Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming
FPGAs.” {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems,
vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.
short: O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very
Large Scale Integration ({VLSI}) Systems 9 (2001) 205–210.
date_created: 2019-07-10T11:47:42Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/92.920835
extern: '1'
intvolume: ' 9'
issue: '1'
language:
- iso: eng
page: 205-210
publication: '{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems'
status: public
title: Object-oriented domain specific compilers for programming FPGAs
type: journal_article
user_id: '398'
volume: 9
year: '2001'
...
---
_id: '13463'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.
apa: Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).
bibtex: '@book{Enzler_Platzner_2001, title={Dynamically Reconfigurable Processors},
publisher={TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}, author={Enzler,
Rolf and Platzner, Marco}, year={2001} }'
chicago: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
ieee: R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
mla: Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors.
TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
short: R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK,
Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
date_created: 2019-09-30T09:27:00Z
date_updated: 2022-01-06T06:51:36Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)
status: public
title: Dynamically Reconfigurable Processors
type: misc
user_id: '398'
year: '2001'
...
---
_id: '6507'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Platzner M. Reconfigurable accelerators for combinatorial problems. Computer.
2000;33(4):58-60. doi:10.1109/2.839322
apa: Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems.
Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322
bibtex: '@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial
problems}, volume={33}, DOI={10.1109/2.839322},
number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics
Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }'
chicago: 'Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”
Computer 33, no. 4 (2000): 58–60. https://doi.org/10.1109/2.839322.'
ieee: M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer,
vol. 33, no. 4, pp. 58–60, 2000.
mla: Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”
Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers
(IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.
short: M. Platzner, Computer 33 (2000) 58–60.
date_created: 2019-01-08T09:45:03Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
doi: 10.1109/2.839322
extern: '1'
intvolume: ' 33'
issue: '4'
language:
- iso: eng
page: 58-60
publication: Computer
publication_identifier:
issn:
- 0018-9162
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Reconfigurable accelerators for combinatorial problems
type: journal_article
user_id: '398'
volume: 33
year: '2000'
...
---
_id: '10606'
author:
- first_name: Michael
full_name: Eisenring, Michael
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable
Embedded Systems. IEE Proceedings -- Computers & Digital Techniques.
2000;147:159-165. doi:10.1049/ip-cdt:20000496
apa: Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital
Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496
bibtex: '@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496},
journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET},
author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165}
}'
chicago: 'Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital
Techniques 147 (2000): 159–65. https://doi.org/10.1049/ip-cdt:20000496.'
ieee: M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in
Reconfigurable Embedded Systems,” IEE Proceedings -- Computers & Digital
Techniques, vol. 147, pp. 159–165, 2000.
mla: Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication
in Reconfigurable Embedded Systems.” IEE Proceedings -- Computers & Digital
Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.
short: M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques
147 (2000) 159–165.
date_created: 2019-07-10T09:22:58Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1049/ip-cdt:20000496
extern: '1'
intvolume: ' 147'
language:
- iso: eng
page: 159-165
publication: IEE Proceedings -- Computers & Digital Techniques
publisher: IET
status: public
title: Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems
type: journal_article
user_id: '398'
volume: 147
year: '2000'
...
---
_id: '10725'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
- first_name: Reinhold
full_name: Weiss, Reinhold
last_name: Weiss
citation:
ama: 'Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized
computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68.
doi:10.1109/5254.850829'
apa: 'Platzner, M., Rinner, B., & Weiss, R. (2000). Toward embedded qualitative
simulation: a specialized computer architecture for QSim. IEEE Intelligent
Systems, 15(2), 62–68. https://doi.org/10.1109/5254.850829'
bibtex: '@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative
simulation: a specialized computer architecture for QSim}, volume={15}, DOI={10.1109/5254.850829}, number={2},
journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\&}
Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard
and Weiss, Reinhold}, year={2000}, pages={62–68} }'
chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Toward Embedded
Qualitative Simulation: A Specialized Computer Architecture for QSim.” IEEE
Intelligent Systems 15, no. 2 (2000): 62–68. https://doi.org/10.1109/5254.850829.'
ieee: 'M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation:
a specialized computer architecture for QSim,” IEEE Intelligent Systems,
vol. 15, no. 2, pp. 62–68, 2000.'
mla: 'Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized
Computer Architecture for QSim.” IEEE Intelligent Systems, vol. 15, no.
2, Institute of Electrical {\&} Electronics Engineers ({IEEE}), 2000, pp.
62–68, doi:10.1109/5254.850829.'
short: M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68.
date_created: 2019-07-10T11:54:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/5254.850829
extern: '1'
intvolume: ' 15'
issue: '2'
language:
- iso: eng
page: 62-68
publication: IEEE Intelligent Systems
publisher: Institute of Electrical {\&} Electronics Engineers ({IEEE})
status: public
title: 'Toward embedded qualitative simulation: a specialized computer architecture
for QSim'
type: journal_article
user_id: '398'
volume: 15
year: '2000'
...
---
_id: '13609'
author:
- first_name: Michael H.
full_name: Eisenring, Michael H.
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable
Systems. In: Proceedings of the 2nd International Workshop on Engineering of
Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.'
apa: Eisenring, M. H., & Platzner, M. (2000). An Implementation Framework for
Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop
on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp.
151–157). CSREA Press.
bibtex: '@inproceedings{Eisenring_Platzner_2000, title={An Implementation Framework
for Run-time Reconfigurable Systems}, booktitle={Proceedings of the 2nd International
Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE)},
publisher={CSREA Press}, author={Eisenring, Michael H. and Platzner, Marco}, year={2000},
pages={151–157} }'
chicago: Eisenring, Michael H., and Marco Platzner. “An Implementation Framework
for Run-Time Reconfigurable Systems.” In Proceedings of the 2nd International
Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE),
151–57. CSREA Press, 2000.
ieee: M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time
Reconfigurable Systems,” in Proceedings of the 2nd International Workshop on
Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 2000, pp.
151–157.
mla: Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for
Run-Time Reconfigurable Systems.” Proceedings of the 2nd International Workshop
on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA
Press, 2000, pp. 151–57.
short: 'M.H. Eisenring, M. Platzner, in: Proceedings of the 2nd International Workshop
on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press,
2000, pp. 151–157.'
date_created: 2019-10-04T21:05:39Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
page: 151-157
publication: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable
Hardware/Software Objects (ENREGLE)
publisher: CSREA Press
status: public
title: An Implementation Framework for Run-time Reconfigurable Systems
type: conference
user_id: '398'
year: '2000'
...
---
_id: '13610'
author:
- first_name: Michael
full_name: Eisenring, Michael
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded
Systems. In: Proceedings of the 10th International Workshop on Field Programmable
Logic and Applications (FPL). Springer; 2000:565-574.'
apa: Eisenring, M., & Platzner, M. (2000). Optimization of Run-time Reconfigurable
Embedded Systems. In Proceedings of the 10th International Workshop on Field
Programmable Logic and Applications (FPL) (pp. 565–574). Springer.
bibtex: '@inproceedings{Eisenring_Platzner_2000, title={Optimization of Run-time
Reconfigurable Embedded Systems}, booktitle={Proceedings of the 10th International
Workshop on Field Programmable Logic and Applications (FPL)}, publisher={Springer},
author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={565–574}
}'
chicago: Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable
Embedded Systems.” In Proceedings of the 10th International Workshop on Field
Programmable Logic and Applications (FPL), 565–74. Springer, 2000.
ieee: M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded
Systems,” in Proceedings of the 10th International Workshop on Field Programmable
Logic and Applications (FPL), 2000, pp. 565–574.
mla: Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable
Embedded Systems.” Proceedings of the 10th International Workshop on Field
Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–74.
short: 'M. Eisenring, M. Platzner, in: Proceedings of the 10th International Workshop
on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–574.'
date_created: 2019-10-04T21:09:09Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
page: 565-574
publication: Proceedings of the 10th International Workshop on Field Programmable
Logic and Applications (FPL)
publisher: Springer
status: public
title: Optimization of Run-time Reconfigurable Embedded Systems
type: conference
user_id: '398'
year: '2000'
...
---
_id: '13607'
author:
- first_name: Oskar
full_name: Mencer, Oskar
last_name: Mencer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability
in an object-oriented design environment. In: Proceedings of the 32nd Annual
Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press;
1999. doi:10.1109/hicss.1999.772883'
apa: Mencer, O., & Platzner, M. (1999). Dynamic circuit generation for Boolean
satisfiability in an object-oriented design environment. In Proceedings of
the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32).
IEEE CS Press. https://doi.org/10.1109/hicss.1999.772883
bibtex: '@inproceedings{Mencer_Platzner_1999, title={Dynamic circuit generation
for Boolean satisfiability in an object-oriented design environment}, DOI={10.1109/hicss.1999.772883},
booktitle={Proceedings of the 32nd Annual Hawaii International Conference on Systems
Sciences (HICSS-32)}, publisher={IEEE CS Press}, author={Mencer, Oskar and Platzner,
Marco}, year={1999} }'
chicago: Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean
Satisfiability in an Object-Oriented Design Environment.” In Proceedings of
the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32).
IEEE CS Press, 1999. https://doi.org/10.1109/hicss.1999.772883.
ieee: O. Mencer and M. Platzner, “Dynamic circuit generation for Boolean satisfiability
in an object-oriented design environment,” in Proceedings of the 32nd Annual
Hawaii International Conference on Systems Sciences (HICSS-32), 1999.
mla: Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean
Satisfiability in an Object-Oriented Design Environment.” Proceedings of the
32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32),
IEEE CS Press, 1999, doi:10.1109/hicss.1999.772883.
short: 'O. Mencer, M. Platzner, in: Proceedings of the 32nd Annual Hawaii International
Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999.'
date_created: 2019-10-04T20:59:20Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1109/hicss.1999.772883
extern: '1'
language:
- iso: eng
publication: Proceedings of the 32nd Annual Hawaii International Conference on Systems
Sciences (HICSS-32)
publication_identifier:
isbn:
- '0769500013'
publication_status: published
publisher: IEEE CS Press
status: public
title: Dynamic circuit generation for Boolean satisfiability in an object-oriented
design environment
type: conference
user_id: '398'
year: '1999'
...
---
_id: '13608'
author:
- first_name: Michael
full_name: Eisenring, Michael
last_name: Eisenring
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable
Embedded Systems. In: Proceedings of the 9th International Workshop on Field
Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214.
doi:10.1007/978-3-540-48302-1_21'
apa: Eisenring, M., Platzner, M., & Thiele, L. (1999). Communication Synthesis
for Reconfigurable Embedded Systems. In Proceedings of the 9th International
Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp.
205–214). Springer. https://doi.org/10.1007/978-3-540-48302-1_21
bibtex: '@inproceedings{Eisenring_Platzner_Thiele_1999, series={LCS}, title={Communication
Synthesis for Reconfigurable Embedded Systems}, volume={1673}, DOI={10.1007/978-3-540-48302-1_21},
booktitle={Proceedings of the 9th International Workshop on Field Programmable
Logic and Applications (FPL)}, publisher={Springer}, author={Eisenring, Michael
and Platzner, Marco and Thiele, Lothar}, year={1999}, pages={205–214}, collection={LCS}
}'
chicago: Eisenring, Michael, Marco Platzner, and Lothar Thiele. “Communication Synthesis
for Reconfigurable Embedded Systems.” In Proceedings of the 9th International
Workshop on Field Programmable Logic and Applications (FPL), 1673:205–14.
LCS. Springer, 1999. https://doi.org/10.1007/978-3-540-48302-1_21.
ieee: M. Eisenring, M. Platzner, and L. Thiele, “Communication Synthesis for Reconfigurable
Embedded Systems,” in Proceedings of the 9th International Workshop on Field
Programmable Logic and Applications (FPL), 1999, vol. 1673, pp. 205–214.
mla: Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded
Systems.” Proceedings of the 9th International Workshop on Field Programmable
Logic and Applications (FPL), vol. 1673, Springer, 1999, pp. 205–14, doi:10.1007/978-3-540-48302-1_21.
short: 'M. Eisenring, M. Platzner, L. Thiele, in: Proceedings of the 9th International
Workshop on Field Programmable Logic and Applications (FPL), Springer, 1999, pp.
205–214.'
date_created: 2019-10-04T21:01:05Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1007/978-3-540-48302-1_21
extern: '1'
intvolume: ' 1673'
language:
- iso: eng
page: 205-214
publication: Proceedings of the 9th International Workshop on Field Programmable Logic
and Applications (FPL)
publication_identifier:
isbn:
- '9783540664574'
- '9783540483021'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer
series_title: LCS
status: public
title: Communication Synthesis for Reconfigurable Embedded Systems
type: conference
user_id: '398'
volume: 1673
year: '1999'
...
---
_id: '10607'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Platzner M. Reconfigurable Computer Architectures. e&i Elektrotechnik
und Informationstechnik. 1998;115:143-148.
apa: Platzner, M. (1998). Reconfigurable Computer Architectures. E&i Elektrotechnik
Und Informationstechnik, 115, 143–148.
bibtex: '@article{Platzner_1998, title={Reconfigurable Computer Architectures},
volume={115}, journal={e&i Elektrotechnik und Informationstechnik}, publisher={Springer},
author={Platzner, Marco}, year={1998}, pages={143–148} }'
chicago: 'Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik
Und Informationstechnik 115 (1998): 143–48.'
ieee: M. Platzner, “Reconfigurable Computer Architectures,” e&i Elektrotechnik
und Informationstechnik, vol. 115, pp. 143–148, 1998.
mla: Platzner, Marco. “Reconfigurable Computer Architectures.” E&i Elektrotechnik
Und Informationstechnik, vol. 115, Springer, 1998, pp. 143–48.
short: M. Platzner, E&i Elektrotechnik Und Informationstechnik 115 (1998) 143–148.
date_created: 2019-07-10T09:22:59Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
extern: '1'
intvolume: ' 115'
language:
- iso: eng
page: 143-148
publication: e&i Elektrotechnik und Informationstechnik
publisher: Springer
status: public
title: Reconfigurable Computer Architectures
type: journal_article
user_id: '398'
volume: 115
year: '1998'
...
---
_id: '10608'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction
Algorithm. International Journal of Computers & Their Applications.
1998;5:106-116.
apa: Platzner, M., & Rinner, B. (1998). Design and Implementation of a Parallel
Constraint Satisfaction Algorithm. International Journal of Computers &
Their Applications, 5, 106–116.
bibtex: '@article{Platzner_Rinner_1998, title={Design and Implementation of a Parallel
Constraint Satisfaction Algorithm}, volume={5}, journal={International Journal
of Computers & Their Applications}, publisher={ISCA}, author={Platzner, Marco
and Rinner, Bernhard}, year={1998}, pages={106–116} }'
chicago: 'Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a
Parallel Constraint Satisfaction Algorithm.” International Journal of Computers
& Their Applications 5 (1998): 106–16.'
ieee: M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint
Satisfaction Algorithm,” International Journal of Computers & Their Applications,
vol. 5, pp. 106–116, 1998.
mla: Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel
Constraint Satisfaction Algorithm.” International Journal of Computers &
Their Applications, vol. 5, ISCA, 1998, pp. 106–16.
short: M. Platzner, B. Rinner, International Journal of Computers & Their Applications
5 (1998) 106–116.
date_created: 2019-07-10T09:23:00Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
extern: '1'
intvolume: ' 5'
language:
- iso: eng
page: 106-116
publication: International Journal of Computers & Their Applications
publisher: ISCA
status: public
title: Design and Implementation of a Parallel Constraint Satisfaction Algorithm
type: journal_article
user_id: '398'
volume: 5
year: '1998'
...
---
_id: '13464'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
- first_name: Reinhold
full_name: Weiss, Reinhold
last_name: Weiss
citation:
ama: Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Fast
Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital
Signal Processing Solutions from Europe’s leading Universities; 1998:106-107.
apa: Platzner, M., Rinner, B., & Weiss, R. (1998). A Distributed Computer
Architecture for Fast Qualitative Simulation (pp. 106–107). Texas Instruments,
The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading
Universities.
bibtex: '@book{Platzner_Rinner_Weiss_1998, title={A Distributed Computer Architecture
for Fast Qualitative Simulation }, publisher={Texas Instruments, The Elite Yearbook
1997 - Digital Signal Processing Solutions from Europe’s leading Universities},
author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1998},
pages={106–107} }'
chicago: Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. A Distributed
Computer Architecture for Fast Qualitative Simulation . Texas Instruments,
The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading
Universities, 1998.
ieee: M. Platzner, B. Rinner, and R. Weiss, A Distributed Computer Architecture
for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997
- Digital Signal Processing Solutions from Europe’s leading Universities, 1998,
pp. 106–107.
mla: Platzner, Marco, et al. A Distributed Computer Architecture for Fast Qualitative
Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing
Solutions from Europe’s leading Universities, 1998, pp. 106–07.
short: M. Platzner, B. Rinner, R. Weiss, A Distributed Computer Architecture for
Fast Qualitative Simulation , Texas Instruments, The Elite Yearbook 1997 - Digital
Signal Processing Solutions from Europe’s leading Universities, 1998.
date_created: 2019-09-30T09:33:27Z
date_updated: 2022-01-06T06:51:36Z
department:
- _id: '78'
language:
- iso: eng
page: 106-107
publisher: Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing
Solutions from Europe's leading Universities
status: public
title: 'A Distributed Computer Architecture for Fast Qualitative Simulation '
type: misc
user_id: '398'
year: '1998'
...
---
_id: '13606'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable
hardware. In: Proceedings of the 8th International Workshop on Field Programmable
Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78.
doi:10.1007/bfb0055234'
apa: 'Platzner, M., & De Micheli, G. (1998). Acceleration of satisfiability
algorithms by reconfigurable hardware. In Proceedings of the 8th International
Workshop on Field Programmable Logic and Applications (FPL) (pp. 69–78).
Berlin, Heidelberg: Springer . https://doi.org/10.1007/bfb0055234'
bibtex: '@inproceedings{Platzner_De Micheli_1998, place={Berlin, Heidelberg}, series={LNCS},
title={Acceleration of satisfiability algorithms by reconfigurable hardware},
DOI={10.1007/bfb0055234}, booktitle={Proceedings
of the 8th International Workshop on Field Programmable Logic and Applications
(FPL) }, publisher={Springer }, author={Platzner, Marco and De Micheli, Giovanni},
year={1998}, pages={69–78}, collection={LNCS} }'
chicago: 'Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability
Algorithms by Reconfigurable Hardware.” In Proceedings of the 8th International
Workshop on Field Programmable Logic and Applications (FPL) , 69–78. LNCS.
Berlin, Heidelberg: Springer , 1998. https://doi.org/10.1007/bfb0055234.'
ieee: M. Platzner and G. De Micheli, “Acceleration of satisfiability algorithms
by reconfigurable hardware,” in Proceedings of the 8th International Workshop
on Field Programmable Logic and Applications (FPL) , 1998, pp. 69–78.
mla: Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms
by Reconfigurable Hardware.” Proceedings of the 8th International Workshop
on Field Programmable Logic and Applications (FPL) , Springer , 1998, pp.
69–78, doi:10.1007/bfb0055234.
short: 'M. Platzner, G. De Micheli, in: Proceedings of the 8th International Workshop
on Field Programmable Logic and Applications (FPL) , Springer , Berlin, Heidelberg,
1998, pp. 69–78.'
date_created: 2019-10-04T20:46:34Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
doi: 10.1007/bfb0055234
extern: '1'
language:
- iso: eng
page: 69-78
place: Berlin, Heidelberg
publication: 'Proceedings of the 8th International Workshop on Field Programmable
Logic and Applications (FPL) '
publication_identifier:
isbn:
- '9783540649489'
- '9783540680666'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: 'Springer '
series_title: LNCS
status: public
title: Acceleration of satisfiability algorithms by reconfigurable hardware
type: conference
user_id: '398'
year: '1998'
...
---
_id: '10609'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
- first_name: Reinhold
full_name: Weiss, Reinhold
last_name: Weiss
citation:
ama: Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative
Simulation in Industrial Applications. e & i Elektrotechnik und Informationstechnik.
1997;114:13-18.
apa: Platzner, M., Rinner, B., & Weiss, R. (1997). A Computer Architecture to
Support Qualitative Simulation in Industrial Applications. E & i Elektrotechnik
Und Informationstechnik, 114, 13–18.
bibtex: '@article{Platzner_Rinner_Weiss_1997, title={A Computer Architecture to
Support Qualitative Simulation in Industrial Applications}, volume={114}, journal={e
& i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner,
Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={13–18} }'
chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “A Computer Architecture
to Support Qualitative Simulation in Industrial Applications.” E & i Elektrotechnik
Und Informationstechnik 114 (1997): 13–18.'
ieee: M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support
Qualitative Simulation in Industrial Applications,” e & i Elektrotechnik
und Informationstechnik, vol. 114, pp. 13–18, 1997.
mla: Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation
in Industrial Applications.” E & i Elektrotechnik Und Informationstechnik,
vol. 114, Springer, 1997, pp. 13–18.
short: M. Platzner, B. Rinner, R. Weiss, E & i Elektrotechnik Und Informationstechnik
114 (1997) 13–18.
date_created: 2019-07-10T09:23:09Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
extern: '1'
intvolume: ' 114'
language:
- iso: eng
page: 13-18
publication: e & i Elektrotechnik und Informationstechnik
publisher: Springer
status: public
title: A Computer Architecture to Support Qualitative Simulation in Industrial Applications
type: journal_article
user_id: '398'
volume: 114
year: '1997'
...
---
_id: '10724'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
- first_name: Reinhold
full_name: Weiss, Reinhold
last_name: Weiss
citation:
ama: Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation
Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6
apa: Platzner, M., Rinner, B., & Weiss, R. (1997). Parallel qualitative simulation.
Simulation Practice and Theory, 5(7–8), 623–638. https://doi.org/10.1016/s0928-4869(97)00008-6
bibtex: '@article{Platzner_Rinner_Weiss_1997, title={Parallel qualitative simulation},
volume={5}, DOI={10.1016/s0928-4869(97)00008-6},
number={7–8}, journal={Simulation Practice and Theory}, publisher={Elsevier},
author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997},
pages={623–638} }'
chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Parallel Qualitative
Simulation.” Simulation Practice and Theory 5, no. 7–8 (1997): 623–38.
https://doi.org/10.1016/s0928-4869(97)00008-6.'
ieee: M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation
Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997.
mla: Platzner, Marco, et al. “Parallel Qualitative Simulation.” Simulation Practice
and Theory, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:10.1016/s0928-4869(97)00008-6.
short: M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997)
623–638.
date_created: 2019-07-10T11:54:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1016/s0928-4869(97)00008-6
extern: '1'
intvolume: ' 5'
issue: 7-8
language:
- iso: eng
page: 623-638
publication: Simulation Practice and Theory
publisher: Elsevier
status: public
title: Parallel qualitative simulation
type: journal_article
user_id: '398'
volume: 5
year: '1997'
...
---
_id: '13603'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Liliane
full_name: Peters, Liliane
last_name: Peters
citation:
ama: 'Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture.
In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods
for Image Processing. Vol 3166. ; 1997.'
apa: 'Platzner, M., & Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP
Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed
Methods for Image Processing (Vol. 3166).'
bibtex: '@inproceedings{Platzner_Peters_1997, title={Fast Signature Segmentation
on a Multi-DSP Architecture}, volume={3166}, booktitle={Proceedings of the SPIE:
Conference on Parallel and Distributed Methods for Image Processing}, author={Platzner,
Marco and Peters, Liliane}, year={1997} }'
chicago: 'Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a
Multi-DSP Architecture.” In Proceedings of the SPIE: Conference on Parallel
and Distributed Methods for Image Processing, Vol. 3166, 1997.'
ieee: 'M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,”
in Proceedings of the SPIE: Conference on Parallel and Distributed Methods
for Image Processing, 1997, vol. 3166.'
mla: 'Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP
Architecture.” Proceedings of the SPIE: Conference on Parallel and Distributed
Methods for Image Processing, vol. 3166, 1997.'
short: 'M. Platzner, L. Peters, in: Proceedings of the SPIE: Conference on Parallel
and Distributed Methods for Image Processing, 1997.'
date_created: 2019-10-04T20:40:55Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
intvolume: ' 3166'
language:
- iso: eng
publication: 'Proceedings of the SPIE: Conference on Parallel and Distributed Methods
for Image Processing'
status: public
title: Fast Signature Segmentation on a Multi-DSP Architecture
type: conference
user_id: '398'
volume: 3166
year: '1997'
...
---
_id: '13604'
author:
- first_name: Thomas
full_name: Röwekamp, Thomas
last_name: Röwekamp
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: 'Liliane '
full_name: 'Peters, Liliane '
last_name: Peters
citation:
ama: 'Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow
Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings
of the 8th International Conference on Signal Processing Applications & Technology
(ICSPAT). ; 1997:829-833.'
apa: 'Röwekamp, T., Platzner, M., & Peters, L. (1997). Specialized Architectures
for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.
In Proceedings of the 8th International Conference on Signal Processing Applications
& Technology (ICSPAT) (pp. 829–833).'
bibtex: '@inproceedings{Röwekamp_Platzner_Peters_1997, title={Specialized Architectures
for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP},
booktitle={Proceedings of the 8th International Conference on Signal Processing
Applications & Technology (ICSPAT)}, author={Röwekamp, Thomas and Platzner,
Marco and Peters, Liliane }, year={1997}, pages={829–833} }'
chicago: 'Röwekamp, Thomas, Marco Platzner, and Liliane Peters. “Specialized Architectures
for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.”
In Proceedings of the 8th International Conference on Signal Processing Applications
& Technology (ICSPAT), 829–33, 1997.'
ieee: 'T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical
Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in Proceedings
of the 8th International Conference on Signal Processing Applications & Technology
(ICSPAT), 1997, pp. 829–833.'
mla: 'Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation:
A Performance Comparison of ASIC, DSP, and Multi-DSP.” Proceedings of the 8th
International Conference on Signal Processing Applications & Technology (ICSPAT),
1997, pp. 829–33.'
short: 'T. Röwekamp, M. Platzner, L. Peters, in: Proceedings of the 8th International
Conference on Signal Processing Applications & Technology (ICSPAT), 1997,
pp. 829–833.'
date_created: 2019-10-04T20:43:29Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
page: 829-833
publication: Proceedings of the 8th International Conference on Signal Processing
Applications & Technology (ICSPAT)
status: public
title: 'Specialized Architectures for Optical Flow Computation: A Performance Comparison
of ASIC, DSP, and Multi-DSP'
type: conference
user_id: '398'
year: '1997'
...
---
_id: '13602'
author:
- first_name: Erich
full_name: Lind, Erich
last_name: Lind
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: 'Bernhard '
full_name: 'Rinner, Bernhard '
last_name: Rinner
citation:
ama: 'Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable
Processors. In: Proceedings of the 7th International Conference on Signal Processing
Applications & Technology (ICSPAT). ; 1996.'
apa: Lind, E., Platzner, M., & Rinner, B. (1996). A Multi-DSP System with Dynamically
Reconfigurable Processors. In Proceedings of the 7th International Conference
on Signal Processing Applications & Technology (ICSPAT).
bibtex: '@inproceedings{Lind_Platzner_Rinner_1996, title={A Multi-DSP System with
Dynamically Reconfigurable Processors}, booktitle={Proceedings of the 7th International
Conference on Signal Processing Applications & Technology (ICSPAT)}, author={Lind,
Erich and Platzner, Marco and Rinner, Bernhard }, year={1996} }'
chicago: Lind, Erich, Marco Platzner, and Bernhard Rinner. “A Multi-DSP System
with Dynamically Reconfigurable Processors.” In Proceedings of the 7th International
Conference on Signal Processing Applications & Technology (ICSPAT), 1996.
ieee: E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically
Reconfigurable Processors,” in Proceedings of the 7th International Conference
on Signal Processing Applications & Technology (ICSPAT), 1996.
mla: Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.”
Proceedings of the 7th International Conference on Signal Processing Applications
& Technology (ICSPAT), 1996.
short: 'E. Lind, M. Platzner, B. Rinner, in: Proceedings of the 7th International
Conference on Signal Processing Applications & Technology (ICSPAT), 1996.'
date_created: 2019-10-04T20:37:59Z
date_updated: 2022-01-06T06:51:40Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publication: Proceedings of the 7th International Conference on Signal Processing
Applications & Technology (ICSPAT)
status: public
title: A Multi-DSP System with Dynamically Reconfigurable Processors
type: conference
user_id: '398'
year: '1996'
...
---
_id: '10610'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
- first_name: Reinhold
full_name: Weiss, Reinhold
last_name: Weiss
citation:
ama: Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction
for Qualitative Simulation. JUCS Journal of Universal Computer Science.
1995;12:811-820.
apa: Platzner, M., Rinner, B., & Weiss, R. (1995). Exploiting Parallelism in
Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal
Computer Science, 12, 811–820.
bibtex: '@article{Platzner_Rinner_Weiss_1995, title={Exploiting Parallelism in Constraint
Satisfaction for Qualitative Simulation}, volume={12}, journal={J.UCS Journal
of Universal Computer Science}, publisher={Springer}, author={Platzner, Marco
and Rinner, Bernhard and Weiss, Reinhold}, year={1995}, pages={811–820} }'
chicago: 'Platzner, Marco, Bernhard Rinner, and Reinhold Weiss. “Exploiting Parallelism
in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal
Computer Science 12 (1995): 811–20.'
ieee: M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint
Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer
Science, vol. 12, pp. 811–820, 1995.
mla: Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction
for Qualitative Simulation.” J.UCS Journal of Universal Computer Science,
vol. 12, Springer, 1995, pp. 811–20.
short: M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science
12 (1995) 811–820.
date_created: 2019-07-10T09:23:10Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
extern: '1'
intvolume: ' 12'
language:
- iso: eng
page: 811-820
publication: J.UCS Journal of Universal Computer Science
publisher: Springer
status: public
title: Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation
type: journal_article
user_id: '398'
volume: 12
year: '1995'
...