---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '29541'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated
ROS 2 Applications. Published online 2022.'
apa: 'Lienen, C., & Platzner, M. (2022). ReconROS Executor: Event-Driven
Programming of FPGA-accelerated ROS 2 Applications.'
bibtex: '@article{Lienen_Platzner_2022, title={ReconROS Executor: Event-Driven Programming
of FPGA-accelerated ROS 2 Applications}, author={Lienen, Christian and Platzner,
Marco}, year={2022} }'
chicago: 'Lienen, Christian, and Marco Platzner. “ReconROS Executor: Event-Driven
Programming of FPGA-Accelerated ROS 2 Applications,” 2022.'
ieee: 'C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of
FPGA-accelerated ROS 2 Applications.” 2022.'
mla: 'Lienen, Christian, and Marco Platzner. ReconROS Executor: Event-Driven
Programming of FPGA-Accelerated ROS 2 Applications. 2022.'
short: C. Lienen, M. Platzner, (2022).
date_created: 2022-01-26T08:52:20Z
date_updated: 2022-01-28T08:30:16Z
department:
- _id: '78'
language:
- iso: eng
main_file_link:
- url: https://arxiv.org/abs/2201.07454
status: public
title: 'ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications'
type: preprint
user_id: '60323'
year: '2022'
...
---
_id: '34007'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications
using ReconROS.
apa: Lienen, C., & Platzner, M. (n.d.). Task Mapping for Hardware-Accelerated
Robotics Applications using ReconROS. 2022 Sixth IEEE International Conference
on Robotic Computing (IRC) , Neaples, Italy.
bibtex: '@inproceedings{Lienen_Platzner, title={Task Mapping for Hardware-Accelerated
Robotics Applications using ReconROS}, author={Lienen, Christian and Platzner,
Marco} }'
chicago: Lienen, Christian, and Marco Platzner. “Task Mapping for Hardware-Accelerated
Robotics Applications Using ReconROS,” n.d.
ieee: C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics
Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference
on Robotic Computing (IRC) , Neaples, Italy.
mla: Lienen, Christian, and Marco Platzner. Task Mapping for Hardware-Accelerated
Robotics Applications Using ReconROS.
short: 'C. Lienen, M. Platzner, in: n.d.'
conference:
location: Neaples, Italy
name: '2022 Sixth IEEE International Conference on Robotic Computing (IRC) '
date_created: 2022-11-04T09:26:42Z
date_updated: 2022-11-04T09:26:47Z
department:
- _id: '78'
language:
- iso: eng
publication_status: accepted
status: public
title: Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS
type: conference
user_id: '60323'
year: '2022'
...
---
_id: '34005'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics
Applications. In: 2022 25th Euromicro Conference on Digital System Design (DSD).
doi:10.1109/DSD57027.2022.00088'
apa: Lienen, C., & Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications. 2022 25th Euromicro Conference on Digital System
Design (DSD). 25th Euromicro Conference on Digital System Design (DSD), Maspalomas,
Gran Canaria, Spain. https://doi.org/10.1109/DSD57027.2022.00088
bibtex: '@inproceedings{Lienen_Platzner, title={Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications}, DOI={10.1109/DSD57027.2022.00088},
booktitle={2022 25th Euromicro Conference on Digital System Design (DSD)}, author={Lienen,
Christian and Platzner, Marco} }'
chicago: Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated
ROS 2 Robotics Applications.” In 2022 25th Euromicro Conference on Digital
System Design (DSD), n.d. https://doi.org/10.1109/DSD57027.2022.00088.
ieee: 'C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated
ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital
System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: 10.1109/DSD57027.2022.00088.'
mla: Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated
ROS 2 Robotics Applications.” 2022 25th Euromicro Conference on Digital System
Design (DSD), doi:10.1109/DSD57027.2022.00088.
short: 'C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System
Design (DSD), n.d.'
conference:
location: Maspalomas, Gran Canaria, Spain
name: 25th Euromicro Conference on Digital System Design (DSD)
date_created: 2022-11-04T09:24:47Z
date_updated: 2023-01-06T06:38:27Z
department:
- _id: '78'
doi: 10.1109/DSD57027.2022.00088
language:
- iso: eng
publication: 2022 25th Euromicro Conference on Digital System Design (DSD)
publication_status: accepted
status: public
title: Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
type: conference
user_id: '60323'
year: '2022'
...
---
_id: '34041'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. Frameworks and Methodologies for Search-Based Approximate Logic
Synthesis.; 2022. doi:10.17619/UNIPB/1-1649
apa: Witschen, L. M. (2022). Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. https://doi.org/10.17619/UNIPB/1-1649
bibtex: '@book{Witschen_2022, title={Frameworks and Methodologies for Search-based
Approximate Logic Synthesis}, DOI={10.17619/UNIPB/1-1649},
author={Witschen, Linus Matthias}, year={2022} }'
chicago: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis, 2022. https://doi.org/10.17619/UNIPB/1-1649.
ieee: L. M. Witschen, Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. 2022.
mla: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis. 2022, doi:10.17619/UNIPB/1-1649.
short: L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate
Logic Synthesis, 2022.
date_created: 2022-11-09T06:26:22Z
date_updated: 2023-01-19T06:41:22Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1649
language:
- iso: eng
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Frameworks and Methodologies for Search-based Approximate Logic Synthesis
type: dissertation
user_id: '15504'
year: '2022'
...
---
_id: '32342'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level
Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022);
2022.'
apa: Ahmed, Q. A., & Platzner, M. (2022). On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium
on VLSI Aliathon Resort, Pafos, Cyprus.
bibtex: '@inproceedings{Ahmed_Platzner_2022, place={Pafos, Cyprus}, title={On the
Detection and Circumvention of Bitstream-Level Trojans in FPGAs}, publisher={IEEE
Computer Society Annual Symposium on VLSI (ISVLSI,2022)}, author={Ahmed, Qazi
Arbab and Platzner, Marco}, year={2022} }'
chicago: 'Ahmed, Qazi Arbab, and Marco Platzner. “On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs.” Pafos, Cyprus: IEEE Computer Society Annual
Symposium on VLSI (ISVLSI,2022), 2022.'
ieee: Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level
Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on
VLSI Aliathon Resort, Pafos, Cyprus, 2022.
mla: Ahmed, Qazi Arbab, and Marco Platzner. On the Detection and Circumvention
of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium
on VLSI (ISVLSI,2022), 2022.
short: 'Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI
(ISVLSI,2022), Pafos, Cyprus, 2022.'
conference:
end_date: July 6, 2022
location: Pafos, Cyprus
name: IEEE Computer Society Annual Symposium on VLSI Aliathon Resort,
start_date: ' July 4, 2022'
date_created: 2022-07-12T19:56:48Z
date_updated: 2023-04-19T15:04:30Z
department:
- _id: '78'
language:
- iso: eng
place: Pafos, Cyprus
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
publisher: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)
status: public
title: On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs
type: conference
user_id: '72764'
year: '2022'
...
---
_id: '33990'
abstract:
- lang: eng
text: Deep neural networks (DNNs) are penetrating into a broad spectrum of applications
and replacing manual algorithmic implementations, including the radio frequency
communications domain with classical signal processing algorithms. However, the
high throughput (gigasamples per second) and low latency requirements of this
application domain pose a significant hurdle for adopting computationally demanding
DNNs. In this article, we explore highly specialized DNN inference accelerator
approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification.
Using an automated end-to-end flow for the generation of the FPGA solution, we
can easily explore a spectrum of solutions that optimize for different design
targets, including accuracy, power efficiency, resources, throughput, and latency.
By leveraging reduced precision arithmetic and customized streaming dataflow,
we demonstrate a solution that meets the application requirements and outperforms
alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded
graphics processing units (GPUs), we measure >10x higher throughput and >100x
lower latency under comparable accuracy and power envelopes.
author:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Yaman
full_name: Umuroglu, Yaman
last_name: Umuroglu
- first_name: Alessandro
full_name: Pappalardo, Alessandro
last_name: Pappalardo
- first_name: Michaela
full_name: Blott, Michaela
last_name: Blott
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN:
Enabling Future RF Applications With FPGA Streaming Architectures. IEEE Micro.
2022;42(6):125-133. doi:10.1109/MM.2022.3202091'
apa: 'Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., & Platzner, M.
(2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming
Architectures. IEEE Micro, 42(6), 125–133. https://doi.org/10.1109/MM.2022.3202091'
bibtex: '@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML
Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures},
volume={42}, DOI={10.1109/MM.2022.3202091},
number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and
Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco},
year={2022}, pages={125–133} }'
chicago: 'Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott,
and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With
FPGA Streaming Architectures.” IEEE Micro 42, no. 6 (2022): 125–33. https://doi.org/10.1109/MM.2022.3202091.'
ieee: 'F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML
Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,”
IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi: 10.1109/MM.2022.3202091.'
mla: 'Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications
With FPGA Streaming Architectures.” IEEE Micro, vol. 42, no. 6, IEEE, 2022,
pp. 125–33, doi:10.1109/MM.2022.3202091.'
short: F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro
42 (2022) 125–133.
date_created: 2022-11-03T14:42:16Z
date_updated: 2023-04-04T15:09:17Z
department:
- _id: '78'
doi: 10.1109/MM.2022.3202091
intvolume: ' 42'
issue: '6'
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9933377
page: 125-133
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: IEEE Micro
publication_status: published
publisher: IEEE
status: public
title: 'RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures'
type: journal_article
user_id: '55631'
volume: 42
year: '2022'
...
---
_id: '45715'
author:
- first_name: Vanessa Ingrid
full_name: Tcheussi Ngayap, Vanessa Ingrid
last_name: Tcheussi Ngayap
citation:
ama: Tcheussi Ngayap VI. FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators.; 2022.
apa: Tcheussi Ngayap, V. I. (2022). FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators.
bibtex: '@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022}
}'
chicago: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core
Processor with Hardware Accelerators, 2022.
ieee: V. I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with
Hardware Accelerators. 2022.
mla: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators. 2022.
short: V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators, 2022.
date_created: 2023-06-22T12:04:57Z
date_updated: 2023-06-22T12:07:53Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators
type: mastersthesis
user_id: '74287'
year: '2022'
...
---
_id: '45914'
author:
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
citation:
ama: Manjunatha S. Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance. Paderborn University ; 2022.
apa: Manjunatha, S. (2022). Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance. Paderborn University .
bibtex: '@book{Manjunatha_2022, title={Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance}, publisher={Paderborn University
}, author={Manjunatha, Suraj}, year={2022} }'
chicago: Manjunatha, Suraj. Dealing With Pre-Processing And Feature Extraction
Of Time-Series Data In Predictive Maintenance. Paderborn University , 2022.
ieee: S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance. Paderborn University , 2022.
mla: Manjunatha, Suraj. Dealing With Pre-Processing And Feature Extraction Of
Time-Series Data In Predictive Maintenance. Paderborn University , 2022.
short: S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series
Data In Predictive Maintenance, Paderborn University , 2022.
date_created: 2023-07-09T12:54:08Z
date_updated: 2023-07-09T13:05:11Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publisher: 'Paderborn University '
status: public
supervisor:
- first_name: 'Marco '
full_name: 'Platzner, Marco '
last_name: Platzner
title: Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive
Maintenance
type: mastersthesis
user_id: '398'
year: '2022'
...
---
_id: '45915'
author:
- first_name: Parvinder
full_name: Kaur , Parvinder
last_name: 'Kaur '
citation:
ama: Kaur P. Analysis of Time-Series Classification in Conditional Monitoring
Systems.; 2022.
apa: Kaur , P. (2022). Analysis of Time-Series Classification in Conditional
Monitoring Systems.
bibtex: '@book{Kaur _2022, place={Paderborn University }, title={Analysis of Time-Series
Classification in Conditional Monitoring Systems}, author={Kaur , Parvinder},
year={2022} }'
chicago: Kaur , Parvinder. Analysis of Time-Series Classification in Conditional
Monitoring Systems. Paderborn University , 2022.
ieee: P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring
Systems. Paderborn University , 2022.
mla: Kaur , Parvinder. Analysis of Time-Series Classification in Conditional
Monitoring Systems. 2022.
short: P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring
Systems, Paderborn University , 2022.
date_created: 2023-07-09T12:58:06Z
date_updated: 2023-07-09T13:05:55Z
department:
- _id: '78'
language:
- iso: eng
place: 'Paderborn University '
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: Analysis of Time-Series Classification in Conditional Monitoring Systems
type: mastersthesis
user_id: '398'
year: '2022'
...
---
_id: '64115'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
last_name: Awais
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Awais M, Platzner M. Automated Framework for Fast Synthesis of Approximate
Hardware Accelerators. In: 2022 IFIP/IEEE 30th International Conference on
Very Large Scale Integration (VLSI-SoC). IEEE; 2022. doi:10.1109/vlsi-soc54400.2022.9939606'
apa: Awais, M., & Platzner, M. (2022). Automated Framework for Fast Synthesis
of Approximate Hardware Accelerators. 2022 IFIP/IEEE 30th International Conference
on Very Large Scale Integration (VLSI-SoC). https://doi.org/10.1109/vlsi-soc54400.2022.9939606
bibtex: '@inproceedings{Awais_Platzner_2022, title={Automated Framework for Fast
Synthesis of Approximate Hardware Accelerators}, DOI={10.1109/vlsi-soc54400.2022.9939606},
booktitle={2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration
(VLSI-SoC)}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2022}
}'
chicago: Awais, Muhammad, and Marco Platzner. “Automated Framework for Fast Synthesis
of Approximate Hardware Accelerators.” In 2022 IFIP/IEEE 30th International
Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. https://doi.org/10.1109/vlsi-soc54400.2022.9939606.
ieee: 'M. Awais and M. Platzner, “Automated Framework for Fast Synthesis of Approximate
Hardware Accelerators,” 2022, doi: 10.1109/vlsi-soc54400.2022.9939606.'
mla: Awais, Muhammad, and Marco Platzner. “Automated Framework for Fast Synthesis
of Approximate Hardware Accelerators.” 2022 IFIP/IEEE 30th International Conference
on Very Large Scale Integration (VLSI-SoC), IEEE, 2022, doi:10.1109/vlsi-soc54400.2022.9939606.
short: 'M. Awais, M. Platzner, in: 2022 IFIP/IEEE 30th International Conference
on Very Large Scale Integration (VLSI-SoC), IEEE, 2022.'
date_created: 2026-02-11T10:20:04Z
date_updated: 2026-02-11T10:20:33Z
department:
- _id: '78'
doi: 10.1109/vlsi-soc54400.2022.9939606
publication: 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration
(VLSI-SoC)
publication_status: published
publisher: IEEE
status: public
title: Automated Framework for Fast Synthesis of Approximate Hardware Accelerators
type: conference
user_id: '64665'
year: '2022'
...
---
_id: '26746'
abstract:
- lang: eng
text: "Previous research in proof-carrying hardware has established the feasibility
and utility of the approach, and provided a concrete solution for employing it
for the certification of functional equivalence checking against a specification,
but fell short in connecting it to state-of-the-art formal verification insights,
methods and tools. Due to the immense complexity of modern circuits, and verification
challenges such as the state explosion problem for sequential circuits, this restriction
of readily-available verification solutions severely limited the applicability
of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
PCH approach and current advances in formal hardware verification, provides methods
and tools to express and certify a wide range of circuit properties, both functional
and non-functional, and presents for the first time prototypes in which circuits
that are implemented on actual reconfigurable hardware are verified with PCH methods.
Using these results, designers can now apply PCH to establish trust in more complex
circuits, by using more diverse properties which they can express using modern,
efficient property specification techniques."
- lang: ger
text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
werden können."
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University; 2021.
apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn University.
bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
University}, author={Wiersema, Tobias}, year={2021} }'
chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University, 2021.
short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '29150'
abstract:
- lang: eng
text: Robotics applications process large amounts of data in real time and require
compute platforms that provide high performance and energy efficiency. FPGAs are
well suited for many of these applications, but there is a reluctance in the robotics
community to use hardware acceleration due to increased design complexity and
a lack of consistent programming models across the software/hardware boundary.
In this article, we present ReconROS, a framework that integrates the widely used
robot operating system (ROS) with ReconOS, which features multithreaded programming
of hardware and software threads for reconfigurable computers. This unique combination
gives ROS 2 developers the flexibility to transparently accelerate parts of their
robotics applications in hardware. We elaborate on the architecture and the design
flow for ReconROS and report on a set of experiments that underline the feasibility
and flexibility of our approach.
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems
with ReconROS. ACM Transactions on Reconfigurable Technology and Systems.
Published online 2021:1-20. doi:10.1145/3494571
apa: Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable
Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology
and Systems, 1–20. https://doi.org/10.1145/3494571
bibtex: '@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable
Robotics Systems with ReconROS}, DOI={10.1145/3494571},
journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen,
Christian and Platzner, Marco}, year={2021}, pages={1–20} }'
chicago: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, 1–20. https://doi.org/10.1145/3494571.
ieee: 'C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics
Systems with ReconROS,” ACM Transactions on Reconfigurable Technology and Systems,
pp. 1–20, 2021, doi: 10.1145/3494571.'
mla: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, pp. 1–20, doi:10.1145/3494571.
short: C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and
Systems (2021) 1–20.
date_created: 2022-01-04T08:30:10Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
doi: 10.1145/3494571
language:
- iso: eng
page: 1-20
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
status: public
title: Design of Distributed Reconfigurable Robotics Systems with ReconROS
type: journal_article
user_id: '60323'
year: '2021'
...
---
_id: '29151'
abstract:
- lang: eng
text: Automation becomes a vital part in the High-Performance computing system in
situational dynamics to take the decisions on the fly. Heterogeneous compute nodes
consist of computing resources such as CPU, GPU and FPGA and are the important
components of the high-performance computing system that can adapt the automation
to achieve the given goal. While implanting automation in the computing resources,
management of the resources is one of the essential aspects that need to be taken
care of. Tasks are continuously executed on the resources using its unique characteristics.
Effective scheduling is essential to make the best use of the characteristics
provided by each resource. Scheduling enables the execution of each task by allocating
resources so that they take advantage of all the characteristics of the compute
resources. Various scheduling heuristics can be used to create effective scheduling,
which might require the execution time to schedule the task efficiently. Providing
actual execution time is not possible in many cases; hence we can provide the
estimations for the actual execution time . The purpose of this master's thesis
is to design a predictive model or system that estimates the execution time required
to execute tasks using historical execution time data on the heterogeneous compute
nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive
Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction
accuracy in order to determine which technique produces reliable predictions for
the execution time. These estimations must be generated in an online learning
environment in which data points arrive in any sequence, one by one, and the regression
model must learn from them. After evaluating the regression algorithms, it is
seen that the XCSF regressor provides the highest overall prediction accuracy
for the supplied data sets. The regression technique's parameters also play a
significant role in achieving an acceptable prediction accuracy. As a remark,
when using online learning in regression analysis, the accuracy depends upon both
the order of sequential data points that are coming to train the model and the
parameter configuration for each regression technique.
author:
- first_name: Chinmay
full_name: Kashikar, Chinmay
last_name: Kashikar
citation:
ama: Kashikar C. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University; 2021.
apa: Kashikar, C. (2021). A Comparison of Machine Learning Techniques for the
On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn University.
bibtex: '@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine
Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous
Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay},
year={2021} }'
chicago: 'Kashikar, Chinmay. A Comparison of Machine Learning Techniques for
the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn: Paderborn University, 2021.'
ieee: 'C. Kashikar, A Comparison of Machine Learning Techniques for the On-line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn:
Paderborn University, 2021.'
mla: Kashikar, Chinmay. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University, 2021.
short: C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University,
Paderborn, 2021.
date_created: 2022-01-04T09:24:52Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: A Comparison of Machine Learning Techniques for the On-line Characterization
of Tasks Executed on Heterogeneous Compute Nodes
type: mastersthesis
user_id: '49992'
year: '2021'
...
---
_id: '21610'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast
Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings
of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32.
doi:https://doi.org/10.1145/3453688.3461506'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2021). LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 (pp.
27–32). Virtual: ACM. https://doi.org/10.1145/3453688.3461506'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX:
A Learning-based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis}, DOI={https://doi.org/10.1145/3453688.3461506},
booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021},
publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and
Platzner, Marco}, year={2021}, pages={27–32} }'
chicago: 'Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX:
A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis.” In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
2021, 27–32. ACM, 2021. https://doi.org/10.1145/3453688.3461506.'
ieee: 'M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual,
2021, pp. 27–32.'
mla: 'Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration
Framework for Approximate Circuit Synthesis.” Proceedings of the ACM Great
Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32, doi:https://doi.org/10.1145/3453688.3461506.'
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.'
conference:
end_date: 2021-06-25
location: Virtual
name: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
start_date: 2021-06-22
date_created: 2021-04-13T10:17:47Z
date_updated: 2022-01-06T06:55:07Z
department:
- _id: '78'
doi: https://doi.org/10.1145/3453688.3461506
language:
- iso: eng
page: 27-32
publication: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
publication_status: published
publisher: ACM
status: public
title: 'LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate
Circuit Synthesis'
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '22216'
author:
- first_name: Jakob Werner
full_name: Rehnen, Jakob Werner
last_name: Rehnen
citation:
ama: Rehnen JW. Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib.; 2021.
apa: Rehnen, J. W. (2021). Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib.
bibtex: '@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner},
year={2021} }'
chicago: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib, 2021.
ieee: J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
mla: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
short: J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib, 2021.
date_created: 2021-05-19T16:56:11Z
date_updated: 2022-01-06T06:55:29Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Decomposition of Arithmetic Components for the Approximate Circuit Synthesis
with EvoApproxLib
type: bachelorsthesis
user_id: '49051'
year: '2021'
...
---
_id: '22309'
abstract:
- lang: eng
text: Approximate computing (AC) has acquired significant maturity in recent years
as a promising approach to obtain energy and area-efficient hardware. Automated
approximate accelerator synthesis involves a great deal of complexity on the size
of design space which exponentially grows with the number of possible approximations.
Design space exploration of approximate accelerator synthesis is usually targeted
via heuristic-based search methods. The majority of existing frameworks prune
a large part of the design space using a greedy-based approach to keep the problem
tractable. Therefore, they result in inferior solutions since many potential solutions
are neglected in the pruning process without the possibility of backtracking of
removed approximate instances. In this paper, we address the aforementioned issue
by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based
search algorithm, in the context of automated synthesis of approximate accelerators.
This enables the synthesis frameworks to deeply subsamples the design space of
approximate accelerator synthesis toward most promising approximate instances
based on the required performance goals, i.e., power consumption, area, or/and
delay. We investigated the challenges of providing an efficient open-source framework
that benefits analytical and search-based approximation techniques simultaneously
to both speed up the synthesis runtime and improve the quality of obtained results.
Besides, we studied the utilization of machine learning algorithms to improve
the performance of several critical steps, i.e., accelerator quality testing,
in the synthesis framework. The proposed framework can help the community to rapidly
generate efficient approximate accelerators in a reasonable runtime.
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators.
In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE;
2021:384-389.'
apa: Awais, M., & Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient
Approximate Accelerators. Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–389.
bibtex: '@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards
Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society
Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner,
Marco}, year={2021}, pages={384–389} }'
chicago: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” In Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–89. IEEE, 2021.
ieee: M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate
Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on
VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
mla: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–89.
short: 'M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–389.'
conference:
end_date: 2021-07-09
location: Tampa, Florida USA (Virtual)
name: IEEE Computer Society Annual Symposium on VLSI
start_date: 2021-07-07
date_created: 2021-06-14T14:05:17Z
date_updated: 2022-01-06T06:55:31Z
department:
- _id: '78'
keyword:
- Approximate computing
- Design space exploration
- Accelerator synthesis
language:
- iso: eng
page: 384-389
publication: Proceedings of IEEE Computer Society Annual Symposium on VLSI
publisher: IEEE
status: public
title: MCTS-Based Synthesis Towards Efficient Approximate Accelerators
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '22483'
abstract:
- lang: eng
text: This bachelor thesis presents a C/C++ implementation of the XCS algorithm
for an embedded system and profiling results concerning the execution time of
the functions. These are then analyzed in relation to the input characteristics
of the examined learning environments and compared with related work. Three main
conclusions can be drawn from the measured results. First, the maximum size of
the population of the classifiers influences the runtime of the genetic algorithm;
second, the size of the input space has a direct effect on the execution time
of the matching function; and last, a larger action space results in a longer
runtime generating the prediction for the possible actions. The dependencies identified
here can serve to optimize the computational efficiency and make XCS more suitable
for embedded systems.
author:
- first_name: Mathis
full_name: Brede, Mathis
last_name: Brede
citation:
ama: 'Brede M. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University; 2021.'
apa: 'Brede, M. (2021). Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University.'
bibtex: '@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling
of XCS in the Context of Embedded Systems}, publisher={Paderborn University},
author={Brede, Mathis}, year={2021} }'
chicago: 'Brede, Mathis. Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University, 2021.'
ieee: 'M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University, 2021.'
mla: Brede, Mathis. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn University, 2021.
short: M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems, Paderborn University, Paderborn, 2021.
date_created: 2021-06-21T09:35:03Z
date_updated: 2022-01-06T06:55:33Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: Implementation and Profiling of XCS in the Context of Embedded Systems
type: bachelorsthesis
user_id: '477'
year: '2021'
...
---
_id: '21953'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Masood
full_name: Raeisi Nafchi, Masood
last_name: Raeisi Nafchi
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization
for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D,
eds. Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications.
Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4'
apa: Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., & Platzner,
M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig,
S. Derrien, P. Diniz, & D. Chillet (Eds.), Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21). Springer Lecture Notes
in Computer Science. https://doi.org/10.1007/978-3-030-79025-7_4
bibtex: '@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable
Computing: Architectures, Tools, and Applications}, title={Timing Optimization
for Virtual FPGA Configurations}, DOI={10.1007/978-3-030-79025-7_4},
booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne
and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro
and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools,
and Applications} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne
Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.”
In Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21), edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel
Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer
Lecture Notes in Computer Science, n.d. https://doi.org/10.1007/978-3-030-79025-7_4.'
ieee: 'L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner,
“Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference,
doi: 10.1007/978-3-030-79025-7_4.'
mla: Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.”
Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21), edited by Frank Hannig et al., Springer Lecture Notes in Computer
Science, doi:10.1007/978-3-030-79025-7_4.
short: 'L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner,
in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes
in Computer Science, n.d.'
conference:
end_date: 2021-07-01
location: Virtual conference
name: International Symposium on Applied Reconfigurable Computing
start_date: 2021-06-29
date_created: 2021-05-04T14:18:46Z
date_updated: 2022-02-14T11:03:09Z
department:
- _id: '78'
doi: 10.1007/978-3-030-79025-7_4
editor:
- first_name: Frank
full_name: Hannig, Frank
last_name: Hannig
- first_name: Steven
full_name: Derrien, Steven
last_name: Derrien
- first_name: Pedro
full_name: Diniz, Pedro
last_name: Diniz
- first_name: Daniel
full_name: Chillet, Daniel
last_name: Chillet
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC'21)
publication_status: accepted
publisher: Springer Lecture Notes in Computer Science
series_title: 'Reconfigurable Computing: Architectures, Tools, and Applications'
status: public
title: Timing Optimization for Virtual FPGA Configurations
type: conference
user_id: '3118'
year: '2021'
...
---
_id: '30906'
abstract:
- lang: eng
text: "Abstract\r\n Background\r\n
\ Hand amputation can have a truly debilitating impact on
the life of the affected person. A multifunctional myoelectric prosthesis controlled
using pattern classification can be used to restore some of the lost motor abilities.
However, learning to control an advanced prosthesis can be a challenging task,
but virtual and augmented reality (AR) provide means to create an engaging and
motivating training.\r\n \r\n Methods\r\n
\ In this study, we present a novel training framework that
integrates virtual elements within a real scene (AR) while allowing the view from
the first-person perspective. The framework was evaluated in 13 able-bodied subjects
and a limb-deficient person divided into intervention (IG) and control (CG) groups.
The IG received training by performing simulated clothespin task and both groups
conducted a pre- and posttest with a real prosthesis. When training with the AR,
the subjects received visual feedback on the generated grasping force. The main
outcome measure was the number of pins that were successfully transferred within
20 min (task duration), while the number of dropped and broken pins were also
registered. The participants were asked to score the difficulty of the real task
(posttest), fun-factor and motivation, as well as the utility of the feedback.\r\n
\ \r\n Results\r\n
\ The performance (median/interquartile range) consistently
increased during the training sessions (4/3 to 22/4). While the results were similar
for the two groups in the pretest, the performance improved in the posttest only
in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5
versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9)
significantly fewer pins in the posttest compared to CG. The participants in IG
assigned (mean ± std) significantly lower scores to the difficulty compared to
CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3)
and usefulness of feedback (8.5 ± 1.7).\r\n \r\n
\ Conclusion\r\n The
results demonstrated that the proposed AR system allows for the transfer of skills
from the simulated to the real task while providing a positive user experience.
The present study demonstrates the effectiveness and flexibility of the proposed
AR framework. Importantly, the developed system is open source and available for
download and further development.\r\n "
article_number: '25'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Dorothee
full_name: Neuhaus, Dorothee
last_name: Neuhaus
- first_name: Sarah
full_name: Vogt, Sarah
last_name: Vogt
- first_name: Christian
full_name: Kaltschmidt, Christian
last_name: Kaltschmidt
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Strahinja
full_name: Dosen, Strahinja
last_name: Dosen
citation:
ama: Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive
augmented reality system for the training of pattern classification control with
a myoelectric prosthesis. Journal of NeuroEngineering and Rehabilitation.
2021;18(1). doi:10.1186/s12984-021-00822-6
apa: Boschmann, A., Neuhaus, D., Vogt, S., Kaltschmidt, C., Platzner, M., &
Dosen, S. (2021). Immersive augmented reality system for the training of pattern
classification control with a myoelectric prosthesis. Journal of NeuroEngineering
and Rehabilitation, 18(1), Article 25. https://doi.org/10.1186/s12984-021-00822-6
bibtex: '@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive
augmented reality system for the training of pattern classification control with
a myoelectric prosthesis}, volume={18}, DOI={10.1186/s12984-021-00822-6},
number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer
Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee
and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja},
year={2021} }'
chicago: Boschmann, Alexander, Dorothee Neuhaus, Sarah Vogt, Christian Kaltschmidt,
Marco Platzner, and Strahinja Dosen. “Immersive Augmented Reality System for the
Training of Pattern Classification Control with a Myoelectric Prosthesis.” Journal
of NeuroEngineering and Rehabilitation 18, no. 1 (2021). https://doi.org/10.1186/s12984-021-00822-6.
ieee: 'A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen,
“Immersive augmented reality system for the training of pattern classification
control with a myoelectric prosthesis,” Journal of NeuroEngineering and Rehabilitation,
vol. 18, no. 1, Art. no. 25, 2021, doi: 10.1186/s12984-021-00822-6.'
mla: Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training
of Pattern Classification Control with a Myoelectric Prosthesis.” Journal of
NeuroEngineering and Rehabilitation, vol. 18, no. 1, 25, Springer Science
and Business Media LLC, 2021, doi:10.1186/s12984-021-00822-6.
short: A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen,
Journal of NeuroEngineering and Rehabilitation 18 (2021).
date_created: 2022-04-18T10:02:20Z
date_updated: 2022-04-18T10:04:16Z
department:
- _id: '78'
doi: 10.1186/s12984-021-00822-6
intvolume: ' 18'
issue: '1'
keyword:
- Health Informatics
- Rehabilitation
language:
- iso: eng
publication: Journal of NeuroEngineering and Rehabilitation
publication_identifier:
issn:
- 1743-0003
publication_status: published
publisher: Springer Science and Business Media LLC
status: public
title: Immersive augmented reality system for the training of pattern classification
control with a myoelectric prosthesis
type: journal_article
user_id: '398'
volume: 18
year: '2021'
...