---
_id: '29150'
abstract:
- lang: eng
text: Robotics applications process large amounts of data in real time and require
compute platforms that provide high performance and energy efficiency. FPGAs are
well suited for many of these applications, but there is a reluctance in the robotics
community to use hardware acceleration due to increased design complexity and
a lack of consistent programming models across the software/hardware boundary.
In this article, we present ReconROS, a framework that integrates the widely used
robot operating system (ROS) with ReconOS, which features multithreaded programming
of hardware and software threads for reconfigurable computers. This unique combination
gives ROS 2 developers the flexibility to transparently accelerate parts of their
robotics applications in hardware. We elaborate on the architecture and the design
flow for ReconROS and report on a set of experiments that underline the feasibility
and flexibility of our approach.
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems
with ReconROS. ACM Transactions on Reconfigurable Technology and Systems.
Published online 2021:1-20. doi:10.1145/3494571
apa: Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable
Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology
and Systems, 1–20. https://doi.org/10.1145/3494571
bibtex: '@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable
Robotics Systems with ReconROS}, DOI={10.1145/3494571},
journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen,
Christian and Platzner, Marco}, year={2021}, pages={1–20} }'
chicago: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, 1–20. https://doi.org/10.1145/3494571.
ieee: 'C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics
Systems with ReconROS,” ACM Transactions on Reconfigurable Technology and Systems,
pp. 1–20, 2021, doi: 10.1145/3494571.'
mla: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, pp. 1–20, doi:10.1145/3494571.
short: C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and
Systems (2021) 1–20.
date_created: 2022-01-04T08:30:10Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
doi: 10.1145/3494571
language:
- iso: eng
page: 1-20
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
status: public
title: Design of Distributed Reconfigurable Robotics Systems with ReconROS
type: journal_article
user_id: '60323'
year: '2021'
...
---
_id: '29151'
abstract:
- lang: eng
text: Automation becomes a vital part in the High-Performance computing system in
situational dynamics to take the decisions on the fly. Heterogeneous compute nodes
consist of computing resources such as CPU, GPU and FPGA and are the important
components of the high-performance computing system that can adapt the automation
to achieve the given goal. While implanting automation in the computing resources,
management of the resources is one of the essential aspects that need to be taken
care of. Tasks are continuously executed on the resources using its unique characteristics.
Effective scheduling is essential to make the best use of the characteristics
provided by each resource. Scheduling enables the execution of each task by allocating
resources so that they take advantage of all the characteristics of the compute
resources. Various scheduling heuristics can be used to create effective scheduling,
which might require the execution time to schedule the task efficiently. Providing
actual execution time is not possible in many cases; hence we can provide the
estimations for the actual execution time . The purpose of this master's thesis
is to design a predictive model or system that estimates the execution time required
to execute tasks using historical execution time data on the heterogeneous compute
nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive
Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction
accuracy in order to determine which technique produces reliable predictions for
the execution time. These estimations must be generated in an online learning
environment in which data points arrive in any sequence, one by one, and the regression
model must learn from them. After evaluating the regression algorithms, it is
seen that the XCSF regressor provides the highest overall prediction accuracy
for the supplied data sets. The regression technique's parameters also play a
significant role in achieving an acceptable prediction accuracy. As a remark,
when using online learning in regression analysis, the accuracy depends upon both
the order of sequential data points that are coming to train the model and the
parameter configuration for each regression technique.
author:
- first_name: Chinmay
full_name: Kashikar, Chinmay
last_name: Kashikar
citation:
ama: Kashikar C. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University; 2021.
apa: Kashikar, C. (2021). A Comparison of Machine Learning Techniques for the
On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn University.
bibtex: '@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine
Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous
Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay},
year={2021} }'
chicago: 'Kashikar, Chinmay. A Comparison of Machine Learning Techniques for
the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn: Paderborn University, 2021.'
ieee: 'C. Kashikar, A Comparison of Machine Learning Techniques for the On-line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn:
Paderborn University, 2021.'
mla: Kashikar, Chinmay. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University, 2021.
short: C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University,
Paderborn, 2021.
date_created: 2022-01-04T09:24:52Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: A Comparison of Machine Learning Techniques for the On-line Characterization
of Tasks Executed on Heterogeneous Compute Nodes
type: mastersthesis
user_id: '49992'
year: '2021'
...
---
_id: '21610'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast
Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings
of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32.
doi:https://doi.org/10.1145/3453688.3461506'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2021). LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 (pp.
27–32). Virtual: ACM. https://doi.org/10.1145/3453688.3461506'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX:
A Learning-based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis}, DOI={https://doi.org/10.1145/3453688.3461506},
booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021},
publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and
Platzner, Marco}, year={2021}, pages={27–32} }'
chicago: 'Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX:
A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis.” In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
2021, 27–32. ACM, 2021. https://doi.org/10.1145/3453688.3461506.'
ieee: 'M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual,
2021, pp. 27–32.'
mla: 'Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration
Framework for Approximate Circuit Synthesis.” Proceedings of the ACM Great
Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32, doi:https://doi.org/10.1145/3453688.3461506.'
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.'
conference:
end_date: 2021-06-25
location: Virtual
name: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
start_date: 2021-06-22
date_created: 2021-04-13T10:17:47Z
date_updated: 2022-01-06T06:55:07Z
department:
- _id: '78'
doi: https://doi.org/10.1145/3453688.3461506
language:
- iso: eng
page: 27-32
publication: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
publication_status: published
publisher: ACM
status: public
title: 'LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate
Circuit Synthesis'
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '22216'
author:
- first_name: Jakob Werner
full_name: Rehnen, Jakob Werner
last_name: Rehnen
citation:
ama: Rehnen JW. Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib.; 2021.
apa: Rehnen, J. W. (2021). Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib.
bibtex: '@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner},
year={2021} }'
chicago: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib, 2021.
ieee: J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
mla: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
short: J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib, 2021.
date_created: 2021-05-19T16:56:11Z
date_updated: 2022-01-06T06:55:29Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Decomposition of Arithmetic Components for the Approximate Circuit Synthesis
with EvoApproxLib
type: bachelorsthesis
user_id: '49051'
year: '2021'
...
---
_id: '22309'
abstract:
- lang: eng
text: Approximate computing (AC) has acquired significant maturity in recent years
as a promising approach to obtain energy and area-efficient hardware. Automated
approximate accelerator synthesis involves a great deal of complexity on the size
of design space which exponentially grows with the number of possible approximations.
Design space exploration of approximate accelerator synthesis is usually targeted
via heuristic-based search methods. The majority of existing frameworks prune
a large part of the design space using a greedy-based approach to keep the problem
tractable. Therefore, they result in inferior solutions since many potential solutions
are neglected in the pruning process without the possibility of backtracking of
removed approximate instances. In this paper, we address the aforementioned issue
by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based
search algorithm, in the context of automated synthesis of approximate accelerators.
This enables the synthesis frameworks to deeply subsamples the design space of
approximate accelerator synthesis toward most promising approximate instances
based on the required performance goals, i.e., power consumption, area, or/and
delay. We investigated the challenges of providing an efficient open-source framework
that benefits analytical and search-based approximation techniques simultaneously
to both speed up the synthesis runtime and improve the quality of obtained results.
Besides, we studied the utilization of machine learning algorithms to improve
the performance of several critical steps, i.e., accelerator quality testing,
in the synthesis framework. The proposed framework can help the community to rapidly
generate efficient approximate accelerators in a reasonable runtime.
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators.
In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE;
2021:384-389.'
apa: Awais, M., & Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient
Approximate Accelerators. Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–389.
bibtex: '@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards
Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society
Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner,
Marco}, year={2021}, pages={384–389} }'
chicago: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” In Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–89. IEEE, 2021.
ieee: M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate
Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on
VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
mla: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–89.
short: 'M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–389.'
conference:
end_date: 2021-07-09
location: Tampa, Florida USA (Virtual)
name: IEEE Computer Society Annual Symposium on VLSI
start_date: 2021-07-07
date_created: 2021-06-14T14:05:17Z
date_updated: 2022-01-06T06:55:31Z
department:
- _id: '78'
keyword:
- Approximate computing
- Design space exploration
- Accelerator synthesis
language:
- iso: eng
page: 384-389
publication: Proceedings of IEEE Computer Society Annual Symposium on VLSI
publisher: IEEE
status: public
title: MCTS-Based Synthesis Towards Efficient Approximate Accelerators
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '22483'
abstract:
- lang: eng
text: This bachelor thesis presents a C/C++ implementation of the XCS algorithm
for an embedded system and profiling results concerning the execution time of
the functions. These are then analyzed in relation to the input characteristics
of the examined learning environments and compared with related work. Three main
conclusions can be drawn from the measured results. First, the maximum size of
the population of the classifiers influences the runtime of the genetic algorithm;
second, the size of the input space has a direct effect on the execution time
of the matching function; and last, a larger action space results in a longer
runtime generating the prediction for the possible actions. The dependencies identified
here can serve to optimize the computational efficiency and make XCS more suitable
for embedded systems.
author:
- first_name: Mathis
full_name: Brede, Mathis
last_name: Brede
citation:
ama: 'Brede M. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University; 2021.'
apa: 'Brede, M. (2021). Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University.'
bibtex: '@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling
of XCS in the Context of Embedded Systems}, publisher={Paderborn University},
author={Brede, Mathis}, year={2021} }'
chicago: 'Brede, Mathis. Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University, 2021.'
ieee: 'M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University, 2021.'
mla: Brede, Mathis. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn University, 2021.
short: M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems, Paderborn University, Paderborn, 2021.
date_created: 2021-06-21T09:35:03Z
date_updated: 2022-01-06T06:55:33Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: Implementation and Profiling of XCS in the Context of Embedded Systems
type: bachelorsthesis
user_id: '477'
year: '2021'
...
---
_id: '21953'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Masood
full_name: Raeisi Nafchi, Masood
last_name: Raeisi Nafchi
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization
for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D,
eds. Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications.
Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4'
apa: Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., & Platzner,
M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig,
S. Derrien, P. Diniz, & D. Chillet (Eds.), Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21). Springer Lecture Notes
in Computer Science. https://doi.org/10.1007/978-3-030-79025-7_4
bibtex: '@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable
Computing: Architectures, Tools, and Applications}, title={Timing Optimization
for Virtual FPGA Configurations}, DOI={10.1007/978-3-030-79025-7_4},
booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne
and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro
and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools,
and Applications} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne
Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.”
In Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21), edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel
Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer
Lecture Notes in Computer Science, n.d. https://doi.org/10.1007/978-3-030-79025-7_4.'
ieee: 'L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner,
“Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference,
doi: 10.1007/978-3-030-79025-7_4.'
mla: Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.”
Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC’21), edited by Frank Hannig et al., Springer Lecture Notes in Computer
Science, doi:10.1007/978-3-030-79025-7_4.
short: 'L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner,
in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International
Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes
in Computer Science, n.d.'
conference:
end_date: 2021-07-01
location: Virtual conference
name: International Symposium on Applied Reconfigurable Computing
start_date: 2021-06-29
date_created: 2021-05-04T14:18:46Z
date_updated: 2022-02-14T11:03:09Z
department:
- _id: '78'
doi: 10.1007/978-3-030-79025-7_4
editor:
- first_name: Frank
full_name: Hannig, Frank
last_name: Hannig
- first_name: Steven
full_name: Derrien, Steven
last_name: Derrien
- first_name: Pedro
full_name: Diniz, Pedro
last_name: Diniz
- first_name: Daniel
full_name: Chillet, Daniel
last_name: Chillet
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of International Symposium on Applied Reconfigurable Computing
(ARC'21)
publication_status: accepted
publisher: Springer Lecture Notes in Computer Science
series_title: 'Reconfigurable Computing: Architectures, Tools, and Applications'
status: public
title: Timing Optimization for Virtual FPGA Configurations
type: conference
user_id: '3118'
year: '2021'
...
---
_id: '30906'
abstract:
- lang: eng
text: "Abstract\r\n Background\r\n
\ Hand amputation can have a truly debilitating impact on
the life of the affected person. A multifunctional myoelectric prosthesis controlled
using pattern classification can be used to restore some of the lost motor abilities.
However, learning to control an advanced prosthesis can be a challenging task,
but virtual and augmented reality (AR) provide means to create an engaging and
motivating training.\r\n \r\n Methods\r\n
\ In this study, we present a novel training framework that
integrates virtual elements within a real scene (AR) while allowing the view from
the first-person perspective. The framework was evaluated in 13 able-bodied subjects
and a limb-deficient person divided into intervention (IG) and control (CG) groups.
The IG received training by performing simulated clothespin task and both groups
conducted a pre- and posttest with a real prosthesis. When training with the AR,
the subjects received visual feedback on the generated grasping force. The main
outcome measure was the number of pins that were successfully transferred within
20 min (task duration), while the number of dropped and broken pins were also
registered. The participants were asked to score the difficulty of the real task
(posttest), fun-factor and motivation, as well as the utility of the feedback.\r\n
\ \r\n Results\r\n
\ The performance (median/interquartile range) consistently
increased during the training sessions (4/3 to 22/4). While the results were similar
for the two groups in the pretest, the performance improved in the posttest only
in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5
versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9)
significantly fewer pins in the posttest compared to CG. The participants in IG
assigned (mean ± std) significantly lower scores to the difficulty compared to
CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3)
and usefulness of feedback (8.5 ± 1.7).\r\n \r\n
\ Conclusion\r\n The
results demonstrated that the proposed AR system allows for the transfer of skills
from the simulated to the real task while providing a positive user experience.
The present study demonstrates the effectiveness and flexibility of the proposed
AR framework. Importantly, the developed system is open source and available for
download and further development.\r\n "
article_number: '25'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Dorothee
full_name: Neuhaus, Dorothee
last_name: Neuhaus
- first_name: Sarah
full_name: Vogt, Sarah
last_name: Vogt
- first_name: Christian
full_name: Kaltschmidt, Christian
last_name: Kaltschmidt
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Strahinja
full_name: Dosen, Strahinja
last_name: Dosen
citation:
ama: Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive
augmented reality system for the training of pattern classification control with
a myoelectric prosthesis. Journal of NeuroEngineering and Rehabilitation.
2021;18(1). doi:10.1186/s12984-021-00822-6
apa: Boschmann, A., Neuhaus, D., Vogt, S., Kaltschmidt, C., Platzner, M., &
Dosen, S. (2021). Immersive augmented reality system for the training of pattern
classification control with a myoelectric prosthesis. Journal of NeuroEngineering
and Rehabilitation, 18(1), Article 25. https://doi.org/10.1186/s12984-021-00822-6
bibtex: '@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive
augmented reality system for the training of pattern classification control with
a myoelectric prosthesis}, volume={18}, DOI={10.1186/s12984-021-00822-6},
number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer
Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee
and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja},
year={2021} }'
chicago: Boschmann, Alexander, Dorothee Neuhaus, Sarah Vogt, Christian Kaltschmidt,
Marco Platzner, and Strahinja Dosen. “Immersive Augmented Reality System for the
Training of Pattern Classification Control with a Myoelectric Prosthesis.” Journal
of NeuroEngineering and Rehabilitation 18, no. 1 (2021). https://doi.org/10.1186/s12984-021-00822-6.
ieee: 'A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen,
“Immersive augmented reality system for the training of pattern classification
control with a myoelectric prosthesis,” Journal of NeuroEngineering and Rehabilitation,
vol. 18, no. 1, Art. no. 25, 2021, doi: 10.1186/s12984-021-00822-6.'
mla: Boschmann, Alexander, et al. “Immersive Augmented Reality System for the Training
of Pattern Classification Control with a Myoelectric Prosthesis.” Journal of
NeuroEngineering and Rehabilitation, vol. 18, no. 1, 25, Springer Science
and Business Media LLC, 2021, doi:10.1186/s12984-021-00822-6.
short: A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen,
Journal of NeuroEngineering and Rehabilitation 18 (2021).
date_created: 2022-04-18T10:02:20Z
date_updated: 2022-04-18T10:04:16Z
department:
- _id: '78'
doi: 10.1186/s12984-021-00822-6
intvolume: ' 18'
issue: '1'
keyword:
- Health Informatics
- Rehabilitation
language:
- iso: eng
publication: Journal of NeuroEngineering and Rehabilitation
publication_identifier:
issn:
- 1743-0003
publication_status: published
publisher: Springer Science and Business Media LLC
status: public
title: Immersive augmented reality system for the training of pattern classification
control with a myoelectric prosthesis
type: journal_article
user_id: '398'
volume: 18
year: '2021'
...
---
_id: '30907'
author:
- first_name: Alfonso
full_name: Rodriguez, Alfonso
last_name: Rodriguez
- first_name: Andres
full_name: Otero, Andres
last_name: Otero
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Eduardo
full_name: De la Torre, Eduardo
last_name: De la Torre
citation:
ama: Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196
apa: Rodriguez, A., Otero, A., Platzner, M., & De la Torre, E. (2021). Exploiting
Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing
in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2021.3107196
bibtex: '@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs}, DOI={10.1109/tc.2021.3107196},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and
Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }'
chicago: Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre.
“Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge
Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, 2021,
1–1. https://doi.org/10.1109/tc.2021.3107196.
ieee: 'A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.'
mla: Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading
Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions
on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021,
pp. 1–1, doi:10.1109/tc.2021.3107196.
short: A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on
Computers (2021) 1–1.
date_created: 2022-04-18T10:03:16Z
date_updated: 2022-04-18T10:04:21Z
department:
- _id: '78'
doi: 10.1109/tc.2021.3107196
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
- 1557-9956
- 2326-3814
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart
Edge Computing in Reconfigurable FPGAs
type: journal_article
user_id: '398'
year: '2021'
...
---
_id: '29137'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: 'Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the
Learning Classifier System XCS. In: HEART ’21: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
Association for Computing Machinery (ACM); 2021. doi:10.1145/3468044.3468055'
apa: 'Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes
using the Learning Classifier System XCS. HEART ’21: Proceedings of the 11th
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
(HEART ’21), Online. https://doi.org/10.1145/3468044.3468055'
bibtex: '@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware
Operation of Heterogeneous Compute Nodes using the Learning Classifier System
XCS}, DOI={10.1145/3468044.3468055},
booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies}, publisher={Association
for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }'
chicago: 'Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using
the Learning Classifier System XCS.” In HEART ’21: Proceedings of the 11th
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
New York, NY, United States: Association for Computing Machinery (ACM), 2021.
https://doi.org/10.1145/3468044.3468055.'
ieee: 'T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using
the Learning Classifier System XCS,” presented at the International Symposium
on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21),
Online, 2021, doi: 10.1145/3468044.3468055.'
mla: 'Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using
the Learning Classifier System XCS.” HEART ’21: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
Association for Computing Machinery (ACM), 2021, doi:10.1145/3468044.3468055.'
short: 'T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium
on Highly Efficient Accelerators and Reconfigurable Technologies, Association
for Computing Machinery (ACM), New York, NY, United States, 2021.'
conference:
end_date: 2021-06-23
location: Online
name: International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies (HEART ’21)
start_date: 2021-06-21
date_created: 2021-12-27T12:01:02Z
date_updated: 2022-11-18T10:03:24Z
department:
- _id: '78'
doi: 10.1145/3468044.3468055
language:
- iso: eng
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication: 'HEART ''21: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies'
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier
System XCS
type: conference
user_id: '477'
year: '2021'
...
---
_id: '29540'
abstract:
- lang: eng
text: "Autonomous mobile robots are becoming increasingly more capable and widespread.
Reliable Obstacle avoidance is an integral part of autonomous navigation. This
involves real time interpretation and processing of a complex environment. Strict
time and energy constraints of a mobile autonomous system make efficient computation
extremely desirable. The benefits of employing Hardware/Software co-designed applications
are obvious and significant. Hardware accelerators are used for efficient processing
of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators,
which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software
co-designed application. However, there is a reluctance when it comes to adoption
of these devices in well established application domains, such as Robotics, due
to a steep learning curve needed for FPGA application design. ReconROS has successfully
bridged the gap between robotic and FPGA application development, by providing
an intuitive, common development platform for robotic application development
for FPGA. It does so by integrating Robotics Operating System(ROS) which is an
industry and academia standard for robotics application development, with ReconOS,
an operating system for re-configurable hardware. In this thesis an obstacle avoidance
system is designed and implemented for an autonomous vehicle using ReconROS. The
objectives of the thesis is to demonstrate and explore ReconROS integration within
the ROS ecosystem and explore the design process within ReconROS framework, and
to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing
the resulting architectures for Latency and Power Consumption."
author:
- first_name: Muhammad Aamir
full_name: Sheikh, Muhammad Aamir
last_name: Sheikh
citation:
ama: Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance
System. Paderborn University; 2021.
apa: Sheikh, M. A. (2021). Design and Implementation of a ReconROS-based Obstacle
Avoidance System. Paderborn University.
bibtex: '@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based
Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh,
Muhammad Aamir}, year={2021} }'
chicago: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based
Obstacle Avoidance System. Paderborn University, 2021.
ieee: M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance
System. Paderborn University, 2021.
mla: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based Obstacle
Avoidance System. Paderborn University, 2021.
short: M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance
System, Paderborn University, 2021.
date_created: 2022-01-26T08:50:52Z
date_updated: 2022-01-28T08:30:46Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
title: Design and Implementation of a ReconROS-based Obstacle Avoidance System
type: mastersthesis
user_id: '60323'
year: '2021'
...
---
_id: '22764'
abstract:
- lang: eng
text: Robotics applications process large amounts of data in real-time and require
compute platforms that provide high performance and energy-efficiency. FPGAs are
well-suited for many of these applications, but there is a reluctance in the robotics
community to use hardware acceleration due to increased design complexity and
a lack of consistent programming models across the software/hardware boundary.
In this paper we present ReconROS, a framework that integrates the widely-used
robot operating system (ROS) with ReconOS, which features multithreaded programming
of hardware and software threads for reconfigurable computers. This unique combination
gives ROS2 developers the flexibility to transparently accelerate parts of their
robotics applications in hardware. We elaborate on the architecture and the design
flow for ReconROS and report on a set of experiments that underline the feasibility
and flexibility of our approach.
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems
with ReconROS. arXiv:210707208. Published online 2021.
apa: Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable
Robotics Systems with ReconROS. In arXiv:2107.07208.
bibtex: '@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable
Robotics Systems with ReconROS}, journal={arXiv:2107.07208}, author={Lienen, Christian
and Platzner, Marco}, year={2021} }'
chicago: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.
ieee: C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics
Systems with ReconROS,” arXiv:2107.07208. 2021.
mla: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.
short: C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).
date_created: 2021-07-16T05:38:56Z
date_updated: 2022-01-28T08:30:24Z
department:
- _id: '78'
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://arxiv.org/abs/2107.07208
oa: '1'
page: '19'
publication: arXiv:2107.07208
status: public
title: Design of Distributed Reconfigurable Robotics Systems with ReconROS
type: preprint
user_id: '60323'
year: '2021'
...
---
_id: '21813'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies
for the Learning Classifier System XCS. In: GECCO ’21: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. Association for Computing
Machinery (ACM); 2021:1639–1647. doi:10.1145/3449726.3463159'
apa: 'Hansmeier, T., & Platzner, M. (2021). An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS. GECCO ’21: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
https://doi.org/10.1145/3449726.3463159'
bibtex: '@inproceedings{Hansmeier_Platzner_2021, place={New York, NY, United States},
title={An Experimental Comparison of Explore/Exploit Strategies for the Learning
Classifier System XCS}, DOI={10.1145/3449726.3463159},
booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Platzner, Marco}, year={2021}, pages={1639–1647} }'
chicago: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” In GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
New York, NY, United States: Association for Computing Machinery (ACM), 2021.
https://doi.org/10.1145/3449726.3463159.'
ieee: 'T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Lille, France,
2021, pp. 1639–1647, doi: 10.1145/3449726.3463159.'
mla: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Association
for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:10.1145/3449726.3463159.'
short: 'T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, Association for Computing Machinery
(ACM), New York, NY, United States, 2021, pp. 1639–1647.'
conference:
end_date: 2021-07-14
location: Lille, France
name: International Workshop on Learning Classifier Systems (IWLCS 2021)
start_date: 2021-07-10
date_created: 2021-04-28T09:08:17Z
date_updated: 2022-09-02T09:42:38Z
department:
- _id: '78'
doi: 10.1145/3449726.3463159
language:
- iso: eng
page: 1639–1647
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-8351-6
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier
System XCS
type: conference
user_id: '49992'
year: '2021'
...
---
_id: '27841'
abstract:
- lang: eng
text: Verification of software and processor hardware usually proceeds separately,
software analysis relying on the correctness of processors executing machine instructions.
This assumption is valid as long as the software runs on standard CPUs that have
been extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption. In
this paper we present a novel formal approach for hardware/software co-verification
targeting processors with custom instruction set extensions. We detail two different
approaches for checking whether the hardware fulfills the requirements expected
by the software analysis. The approaches are designed to explore a trade-off between
generality of the verification and computational effort. Then, we describe the
integration of software and hardware analyses for both techniques and describe
a fully automated tool chain implementing the approaches. Finally, we demonstrate
and compare the two approaches on example source code with custom instructions,
using state-of-the-art software analysis and hardware verification techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Felix
full_name: Pauck, Felix
id: '22398'
last_name: Pauck
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware
Co-Verification for Custom Instruction Set Processors. IEEE Access. Published
online 2021. doi:10.1109/ACCESS.2021.3131213
apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021).
Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE
Access. https://doi.org/10.1109/ACCESS.2021.3131213
bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware
Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213},
journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck,
Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021}
}'
chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and
Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set
Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.
ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware
Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021,
doi: 10.1109/ACCESS.2021.3131213.'
mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom
Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.
short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access
(2021).
date_created: 2021-11-25T14:12:22Z
date_updated: 2023-01-18T08:34:50Z
department:
- _id: '78'
doi: 10.1109/ACCESS.2021.3131213
funded_apc: '1'
keyword:
- Software Analysis
- Abstract Interpretation
- Custom Instruction
- Hardware Verification
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: IEEE Access
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Software/Hardware Co-Verification for Custom Instruction Set Processors
type: journal_article
user_id: '22398'
year: '2021'
...
---
_id: '29138'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: 'Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE
29th International Conference on Very Large Scale Integration (VLSI-SoC).
; 2021. doi:10.1109/vlsi-soc53125.2021.9606974'
apa: Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC).
https://doi.org/10.1109/vlsi-soc53125.2021.9606974
bibtex: '@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing},
DOI={10.1109/vlsi-soc53125.2021.9606974},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }'
chicago: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021. https://doi.org/10.1109/vlsi-soc53125.2021.9606974.
ieee: 'Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.'
mla: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021, doi:10.1109/vlsi-soc53125.2021.9606974.
short: 'Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large
Scale Integration (VLSI-SoC), 2021.'
date_created: 2021-12-30T00:02:24Z
date_updated: 2023-04-19T15:03:45Z
department:
- _id: '78'
doi: 10.1109/vlsi-soc53125.2021.9606974
language:
- iso: eng
project:
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
- _id: '1'
name: 'SFB 901: SFB 901'
publication: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)
publication_status: published
status: public
title: Hardware Trojans in Reconfigurable Computing
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '20681'
abstract:
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. The advanced stealthy malicious look-up-table (LUT) attack activates a
Trojan only when generating the FPGA bitstream and can thus not be detected by
register transfer and gate level testing and verification. However, also this
attack was recently revealed by a bitstream-level proof-carrying hardware (PCH)
approach. In this paper, we present a novel attack that leverages malicious routing
of the inserted Trojan circuit to acquire a dormant state even in the generated
and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs
of the FPGA via a programmable interconnect point (PIP). The Trojan is detached
from inputs/outputs during place-and-route and re-connected only when the FPGA
is being programmed, thus activating the Trojan circuit without any need for a
trigger logic. Since the Trojan is injected in a post-synthesis step and remains
unconnected in the bitstream, the presented attack can currently neither be prevented
by conventional testing and verification methods nor by recent bitstream-level
verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level
Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference
(DATE); 2021. doi:10.23919/DATE51398.2021.9474026'
apa: 'Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing:
Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Design, Automation
and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026'
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble,
France}, title={Malicious Routing: Circumventing Bitstream-level Verification
for FPGAs}, DOI={10.23919/DATE51398.2021.9474026},
booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition
(DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)},
author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021}
}'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing:
Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble,
France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing
Bitstream-level Verification for FPGAs,” presented at the Design, Automation and
Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.'
mla: 'Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level
Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference
(DATE), 2021, doi:10.23919/DATE51398.2021.9474026.'
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation &
Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and
Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.'
conference:
end_date: 2021-02-05
location: Alpexpo | Grenoble, France
name: Design, Automation and Test in Europe Conference (DATE'21)
start_date: 2021-02-01
date_created: 2020-12-07T14:03:00Z
date_updated: 2023-05-11T09:16:34Z
ddc:
- '006'
department:
- _id: '78'
doi: 10.23919/DATE51398.2021.9474026
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:16:15Z
date_updated: 2023-05-11T09:16:15Z
file_id: '44752'
file_name: 1812.pdf
file_size: 394011
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:16:15Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Alpexpo | Grenoble, France
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
publication_identifier:
eisbn:
- 978-3-9819263-5-4
publication_status: published
publisher: 2021 Design, Automation and Test in Europe Conference (DATE)
status: public
title: 'Malicious Routing: Circumventing Bitstream-level Verification for FPGAs'
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '30909'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: 'Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
ACM; 2021. doi:10.1145/3468044.3468056'
apa: 'Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
https://doi.org/10.1145/3468044.3468056'
bibtex: '@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded
Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={10.1145/3468044.3468056}, booktitle={Proceedings
of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }'
chicago: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for
Industrial Analytics on a Reconfigurable System-on-Chip.” In Proceedings of
the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies. ACM, 2021. https://doi.org/10.1145/3468044.3468056.'
ieee: 'L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.'
mla: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip.” Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
ACM, 2021, doi:10.1145/3468044.3468056.'
short: 'L. Clausing, in: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.'
date_created: 2022-04-18T10:17:47Z
date_updated: 2023-07-09T13:09:11Z
department:
- _id: '78'
doi: 10.1145/3468044.3468056
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: Proceedings of the 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies
publication_status: published
publisher: ACM
status: public
title: 'ReconOS64: High-Performance Embedded Computing for Industrial Analytics on
a Reconfigurable System-on-Chip'
type: conference
user_id: '398'
year: '2021'
...
---
_id: '30908'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Maurice
full_name: Kuschel, Maurice
last_name: Kuschel
- first_name: 'Rahil '
full_name: 'Arshad, Rahil '
last_name: Arshad
- first_name: Sneha
full_name: Rautmare, Sneha
last_name: Rautmare
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: 'Dirk '
full_name: 'Schollbach, Dirk '
last_name: Schollbach
citation:
ama: 'Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration
of Lightweight DNN Model Inference in Industrial Analytics. In: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases. Springer;
2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27'
apa: 'Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare,
S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021).
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Machine Learning and Principles and Practice of Knowledge Discovery in Databases.
https://doi.org/10.1007/978-3-030-93736-2_27'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021,
title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics}, DOI={https://doi.org/10.1007/978-3-030-93736-2_27},
booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery
in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and
Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and
Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach,
Dirk }, year={2021} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil Arshad,
Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk Schollbach.
“FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.”
In Machine Learning and Principles and Practice of Knowledge Discovery in
Databases. Springer, 2021. https://doi.org/10.1007/978-3-030-93736-2_27.'
ieee: 'H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics.” Machine Learning and Principles
and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.'
short: 'H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare,
S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.'
date_created: 2022-04-18T10:16:55Z
date_updated: 2023-09-15T15:09:07Z
department:
- _id: '78'
doi: https://doi.org/10.1007/978-3-030-93736-2_27
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: ' Machine Learning and Principles and Practice of Knowledge Discovery
in Databases'
publisher: Springer
status: public
title: 'FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics'
type: conference
user_id: '477'
year: '2021'
...
---
_id: '3583'
author:
- first_name: Zakarya
full_name: ' Guetttatfi, Zakarya'
last_name: ' Guetttatfi'
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches
for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.
In: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC). ; 2020.'
apa: Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices. In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC).
bibtex: '@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices}, booktitle={Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul
and Platzner, Marco}, year={2020} }'
chicago: Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices.” In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC), 2020.
ieee: Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic
Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing
Devices,” in Proceedings of the International Workshop on Applied Reconfigurable
Computing (ARC), 2020.
mla: Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling
and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings
of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
short: 'Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), 2020.'
date_created: 2018-07-20T14:07:15Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC)
status: public
title: Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware
Tasks to Reconfigurable Computing Devices
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21324'
author:
- first_name: Khushboo
full_name: Chandrakar, Khushboo
last_name: Chandrakar
citation:
ama: Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis.; 2020.
apa: Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis.
bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
}'
chicago: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to
Improve Approximate Circuit Synthesis, 2020.
ieee: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis. 2020.
mla: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis. 2020.
short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...