---
_id: '30907'
author:
- first_name: Alfonso
full_name: Rodriguez, Alfonso
last_name: Rodriguez
- first_name: Andres
full_name: Otero, Andres
last_name: Otero
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Eduardo
full_name: De la Torre, Eduardo
last_name: De la Torre
citation:
ama: Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196
apa: Rodriguez, A., Otero, A., Platzner, M., & De la Torre, E. (2021). Exploiting
Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing
in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2021.3107196
bibtex: '@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs}, DOI={10.1109/tc.2021.3107196},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and
Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }'
chicago: Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre.
“Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge
Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, 2021,
1–1. https://doi.org/10.1109/tc.2021.3107196.
ieee: 'A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.'
mla: Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading
Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions
on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021,
pp. 1–1, doi:10.1109/tc.2021.3107196.
short: A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on
Computers (2021) 1–1.
date_created: 2022-04-18T10:03:16Z
date_updated: 2022-04-18T10:04:21Z
department:
- _id: '78'
doi: 10.1109/tc.2021.3107196
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
- 1557-9956
- 2326-3814
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart
Edge Computing in Reconfigurable FPGAs
type: journal_article
user_id: '398'
year: '2021'
...
---
_id: '29137'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: 'Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the
Learning Classifier System XCS. In: HEART ’21: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
Association for Computing Machinery (ACM); 2021. doi:10.1145/3468044.3468055'
apa: 'Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes
using the Learning Classifier System XCS. HEART ’21: Proceedings of the 11th
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
(HEART ’21), Online. https://doi.org/10.1145/3468044.3468055'
bibtex: '@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware
Operation of Heterogeneous Compute Nodes using the Learning Classifier System
XCS}, DOI={10.1145/3468044.3468055},
booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies}, publisher={Association
for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }'
chicago: 'Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using
the Learning Classifier System XCS.” In HEART ’21: Proceedings of the 11th
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
New York, NY, United States: Association for Computing Machinery (ACM), 2021.
https://doi.org/10.1145/3468044.3468055.'
ieee: 'T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using
the Learning Classifier System XCS,” presented at the International Symposium
on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21),
Online, 2021, doi: 10.1145/3468044.3468055.'
mla: 'Hansmeier, Tim. “Self-Aware Operation of Heterogeneous Compute Nodes Using
the Learning Classifier System XCS.” HEART ’21: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
Association for Computing Machinery (ACM), 2021, doi:10.1145/3468044.3468055.'
short: 'T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium
on Highly Efficient Accelerators and Reconfigurable Technologies, Association
for Computing Machinery (ACM), New York, NY, United States, 2021.'
conference:
end_date: 2021-06-23
location: Online
name: International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies (HEART ’21)
start_date: 2021-06-21
date_created: 2021-12-27T12:01:02Z
date_updated: 2022-11-18T10:03:24Z
department:
- _id: '78'
doi: 10.1145/3468044.3468055
language:
- iso: eng
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication: 'HEART ''21: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies'
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier
System XCS
type: conference
user_id: '477'
year: '2021'
...
---
_id: '29540'
abstract:
- lang: eng
text: "Autonomous mobile robots are becoming increasingly more capable and widespread.
Reliable Obstacle avoidance is an integral part of autonomous navigation. This
involves real time interpretation and processing of a complex environment. Strict
time and energy constraints of a mobile autonomous system make efficient computation
extremely desirable. The benefits of employing Hardware/Software co-designed applications
are obvious and significant. Hardware accelerators are used for efficient processing
of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators,
which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software
co-designed application. However, there is a reluctance when it comes to adoption
of these devices in well established application domains, such as Robotics, due
to a steep learning curve needed for FPGA application design. ReconROS has successfully
bridged the gap between robotic and FPGA application development, by providing
an intuitive, common development platform for robotic application development
for FPGA. It does so by integrating Robotics Operating System(ROS) which is an
industry and academia standard for robotics application development, with ReconOS,
an operating system for re-configurable hardware. In this thesis an obstacle avoidance
system is designed and implemented for an autonomous vehicle using ReconROS. The
objectives of the thesis is to demonstrate and explore ReconROS integration within
the ROS ecosystem and explore the design process within ReconROS framework, and
to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing
the resulting architectures for Latency and Power Consumption."
author:
- first_name: Muhammad Aamir
full_name: Sheikh, Muhammad Aamir
last_name: Sheikh
citation:
ama: Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance
System. Paderborn University; 2021.
apa: Sheikh, M. A. (2021). Design and Implementation of a ReconROS-based Obstacle
Avoidance System. Paderborn University.
bibtex: '@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based
Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh,
Muhammad Aamir}, year={2021} }'
chicago: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based
Obstacle Avoidance System. Paderborn University, 2021.
ieee: M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance
System. Paderborn University, 2021.
mla: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based Obstacle
Avoidance System. Paderborn University, 2021.
short: M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance
System, Paderborn University, 2021.
date_created: 2022-01-26T08:50:52Z
date_updated: 2022-01-28T08:30:46Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
title: Design and Implementation of a ReconROS-based Obstacle Avoidance System
type: mastersthesis
user_id: '60323'
year: '2021'
...
---
_id: '22764'
abstract:
- lang: eng
text: Robotics applications process large amounts of data in real-time and require
compute platforms that provide high performance and energy-efficiency. FPGAs are
well-suited for many of these applications, but there is a reluctance in the robotics
community to use hardware acceleration due to increased design complexity and
a lack of consistent programming models across the software/hardware boundary.
In this paper we present ReconROS, a framework that integrates the widely-used
robot operating system (ROS) with ReconOS, which features multithreaded programming
of hardware and software threads for reconfigurable computers. This unique combination
gives ROS2 developers the flexibility to transparently accelerate parts of their
robotics applications in hardware. We elaborate on the architecture and the design
flow for ReconROS and report on a set of experiments that underline the feasibility
and flexibility of our approach.
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems
with ReconROS. arXiv:210707208. Published online 2021.
apa: Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable
Robotics Systems with ReconROS. In arXiv:2107.07208.
bibtex: '@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable
Robotics Systems with ReconROS}, journal={arXiv:2107.07208}, author={Lienen, Christian
and Platzner, Marco}, year={2021} }'
chicago: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.
ieee: C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics
Systems with ReconROS,” arXiv:2107.07208. 2021.
mla: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ArXiv:2107.07208, 2021.
short: C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).
date_created: 2021-07-16T05:38:56Z
date_updated: 2022-01-28T08:30:24Z
department:
- _id: '78'
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://arxiv.org/abs/2107.07208
oa: '1'
page: '19'
publication: arXiv:2107.07208
status: public
title: Design of Distributed Reconfigurable Robotics Systems with ReconROS
type: preprint
user_id: '60323'
year: '2021'
...
---
_id: '21813'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies
for the Learning Classifier System XCS. In: GECCO ’21: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. Association for Computing
Machinery (ACM); 2021:1639–1647. doi:10.1145/3449726.3463159'
apa: 'Hansmeier, T., & Platzner, M. (2021). An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS. GECCO ’21: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
https://doi.org/10.1145/3449726.3463159'
bibtex: '@inproceedings{Hansmeier_Platzner_2021, place={New York, NY, United States},
title={An Experimental Comparison of Explore/Exploit Strategies for the Learning
Classifier System XCS}, DOI={10.1145/3449726.3463159},
booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Platzner, Marco}, year={2021}, pages={1639–1647} }'
chicago: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” In GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 1639–1647.
New York, NY, United States: Association for Computing Machinery (ACM), 2021.
https://doi.org/10.1145/3449726.3463159.'
ieee: 'T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Lille, France,
2021, pp. 1639–1647, doi: 10.1145/3449726.3463159.'
mla: 'Hansmeier, Tim, and Marco Platzner. “An Experimental Comparison of Explore/Exploit
Strategies for the Learning Classifier System XCS.” GECCO ’21: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, Association
for Computing Machinery (ACM), 2021, pp. 1639–1647, doi:10.1145/3449726.3463159.'
short: 'T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, Association for Computing Machinery
(ACM), New York, NY, United States, 2021, pp. 1639–1647.'
conference:
end_date: 2021-07-14
location: Lille, France
name: International Workshop on Learning Classifier Systems (IWLCS 2021)
start_date: 2021-07-10
date_created: 2021-04-28T09:08:17Z
date_updated: 2022-09-02T09:42:38Z
department:
- _id: '78'
doi: 10.1145/3449726.3463159
language:
- iso: eng
page: 1639–1647
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''21: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-8351-6
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier
System XCS
type: conference
user_id: '49992'
year: '2021'
...
---
_id: '27841'
abstract:
- lang: eng
text: Verification of software and processor hardware usually proceeds separately,
software analysis relying on the correctness of processors executing machine instructions.
This assumption is valid as long as the software runs on standard CPUs that have
been extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption. In
this paper we present a novel formal approach for hardware/software co-verification
targeting processors with custom instruction set extensions. We detail two different
approaches for checking whether the hardware fulfills the requirements expected
by the software analysis. The approaches are designed to explore a trade-off between
generality of the verification and computational effort. Then, we describe the
integration of software and hardware analyses for both techniques and describe
a fully automated tool chain implementing the approaches. Finally, we demonstrate
and compare the two approaches on example source code with custom instructions,
using state-of-the-art software analysis and hardware verification techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Felix
full_name: Pauck, Felix
id: '22398'
last_name: Pauck
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware
Co-Verification for Custom Instruction Set Processors. IEEE Access. Published
online 2021. doi:10.1109/ACCESS.2021.3131213
apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021).
Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE
Access. https://doi.org/10.1109/ACCESS.2021.3131213
bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware
Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213},
journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck,
Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021}
}'
chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and
Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set
Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.
ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware
Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021,
doi: 10.1109/ACCESS.2021.3131213.'
mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom
Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.
short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access
(2021).
date_created: 2021-11-25T14:12:22Z
date_updated: 2023-01-18T08:34:50Z
department:
- _id: '78'
doi: 10.1109/ACCESS.2021.3131213
funded_apc: '1'
keyword:
- Software Analysis
- Abstract Interpretation
- Custom Instruction
- Hardware Verification
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: IEEE Access
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Software/Hardware Co-Verification for Custom Instruction Set Processors
type: journal_article
user_id: '22398'
year: '2021'
...
---
_id: '29138'
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: 'Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE
29th International Conference on Very Large Scale Integration (VLSI-SoC).
; 2021. doi:10.1109/vlsi-soc53125.2021.9606974'
apa: Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC).
https://doi.org/10.1109/vlsi-soc53125.2021.9606974
bibtex: '@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing},
DOI={10.1109/vlsi-soc53125.2021.9606974},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }'
chicago: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021. https://doi.org/10.1109/vlsi-soc53125.2021.9606974.
ieee: 'Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.'
mla: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” 2021
IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC),
2021, doi:10.1109/vlsi-soc53125.2021.9606974.
short: 'Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large
Scale Integration (VLSI-SoC), 2021.'
date_created: 2021-12-30T00:02:24Z
date_updated: 2023-04-19T15:03:45Z
department:
- _id: '78'
doi: 10.1109/vlsi-soc53125.2021.9606974
language:
- iso: eng
project:
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
- _id: '1'
name: 'SFB 901: SFB 901'
publication: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration
(VLSI-SoC)
publication_status: published
status: public
title: Hardware Trojans in Reconfigurable Computing
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '20681'
abstract:
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. The advanced stealthy malicious look-up-table (LUT) attack activates a
Trojan only when generating the FPGA bitstream and can thus not be detected by
register transfer and gate level testing and verification. However, also this
attack was recently revealed by a bitstream-level proof-carrying hardware (PCH)
approach. In this paper, we present a novel attack that leverages malicious routing
of the inserted Trojan circuit to acquire a dormant state even in the generated
and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs
of the FPGA via a programmable interconnect point (PIP). The Trojan is detached
from inputs/outputs during place-and-route and re-connected only when the FPGA
is being programmed, thus activating the Trojan circuit without any need for a
trigger logic. Since the Trojan is injected in a post-synthesis step and remains
unconnected in the bitstream, the presented attack can currently neither be prevented
by conventional testing and verification methods nor by recent bitstream-level
verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level
Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference
(DATE); 2021. doi:10.23919/DATE51398.2021.9474026'
apa: 'Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing:
Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Design, Automation
and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026'
bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble,
France}, title={Malicious Routing: Circumventing Bitstream-level Verification
for FPGAs}, DOI={10.23919/DATE51398.2021.9474026},
booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition
(DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)},
author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021}
}'
chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing:
Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation
& Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble,
France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.'
ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing
Bitstream-level Verification for FPGAs,” presented at the Design, Automation and
Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.'
mla: 'Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level
Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference
(DATE), 2021, doi:10.23919/DATE51398.2021.9474026.'
short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation &
Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and
Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.'
conference:
end_date: 2021-02-05
location: Alpexpo | Grenoble, France
name: Design, Automation and Test in Europe Conference (DATE'21)
start_date: 2021-02-01
date_created: 2020-12-07T14:03:00Z
date_updated: 2023-05-11T09:16:34Z
ddc:
- '006'
department:
- _id: '78'
doi: 10.23919/DATE51398.2021.9474026
file:
- access_level: closed
content_type: application/pdf
creator: qazi
date_created: 2023-05-11T09:16:15Z
date_updated: 2023-05-11T09:16:15Z
file_id: '44752'
file_name: 1812.pdf
file_size: 394011
relation: main_file
success: 1
file_date_updated: 2023-05-11T09:16:15Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Alpexpo | Grenoble, France
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
publication_identifier:
eisbn:
- 978-3-9819263-5-4
publication_status: published
publisher: 2021 Design, Automation and Test in Europe Conference (DATE)
status: public
title: 'Malicious Routing: Circumventing Bitstream-level Verification for FPGAs'
type: conference
user_id: '72764'
year: '2021'
...
---
_id: '30909'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: 'Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
ACM; 2021. doi:10.1145/3468044.3468056'
apa: 'Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
https://doi.org/10.1145/3468044.3468056'
bibtex: '@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded
Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={10.1145/3468044.3468056}, booktitle={Proceedings
of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }'
chicago: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for
Industrial Analytics on a Reconfigurable System-on-Chip.” In Proceedings of
the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies. ACM, 2021. https://doi.org/10.1145/3468044.3468056.'
ieee: 'L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.'
mla: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip.” Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
ACM, 2021, doi:10.1145/3468044.3468056.'
short: 'L. Clausing, in: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.'
date_created: 2022-04-18T10:17:47Z
date_updated: 2023-07-09T13:09:11Z
department:
- _id: '78'
doi: 10.1145/3468044.3468056
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: Proceedings of the 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies
publication_status: published
publisher: ACM
status: public
title: 'ReconOS64: High-Performance Embedded Computing for Industrial Analytics on
a Reconfigurable System-on-Chip'
type: conference
user_id: '398'
year: '2021'
...
---
_id: '30908'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Maurice
full_name: Kuschel, Maurice
last_name: Kuschel
- first_name: 'Rahil '
full_name: 'Arshad, Rahil '
last_name: Arshad
- first_name: Sneha
full_name: Rautmare, Sneha
last_name: Rautmare
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: 'Dirk '
full_name: 'Schollbach, Dirk '
last_name: Schollbach
citation:
ama: 'Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration
of Lightweight DNN Model Inference in Industrial Analytics. In: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases. Springer;
2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27'
apa: 'Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare,
S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021).
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Machine Learning and Principles and Practice of Knowledge Discovery in Databases.
https://doi.org/10.1007/978-3-030-93736-2_27'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021,
title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics}, DOI={https://doi.org/10.1007/978-3-030-93736-2_27},
booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery
in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and
Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and
Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach,
Dirk }, year={2021} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil Arshad,
Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk Schollbach.
“FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.”
In Machine Learning and Principles and Practice of Knowledge Discovery in
Databases. Springer, 2021. https://doi.org/10.1007/978-3-030-93736-2_27.'
ieee: 'H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics.” Machine Learning and Principles
and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.'
short: 'H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare,
S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.'
date_created: 2022-04-18T10:16:55Z
date_updated: 2023-09-15T15:09:07Z
department:
- _id: '78'
doi: https://doi.org/10.1007/978-3-030-93736-2_27
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: ' Machine Learning and Principles and Practice of Knowledge Discovery
in Databases'
publisher: Springer
status: public
title: 'FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics'
type: conference
user_id: '477'
year: '2021'
...
---
_id: '3583'
author:
- first_name: Zakarya
full_name: ' Guetttatfi, Zakarya'
last_name: ' Guetttatfi'
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches
for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.
In: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC). ; 2020.'
apa: Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices. In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC).
bibtex: '@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices}, booktitle={Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul
and Platzner, Marco}, year={2020} }'
chicago: Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices.” In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC), 2020.
ieee: Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic
Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing
Devices,” in Proceedings of the International Workshop on Applied Reconfigurable
Computing (ARC), 2020.
mla: Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling
and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings
of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
short: 'Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), 2020.'
date_created: 2018-07-20T14:07:15Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC)
status: public
title: Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware
Tasks to Reconfigurable Computing Devices
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21324'
author:
- first_name: Khushboo
full_name: Chandrakar, Khushboo
last_name: Chandrakar
citation:
ama: Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis.; 2020.
apa: Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis.
bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
}'
chicago: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to
Improve Approximate Circuit Synthesis, 2020.
ieee: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis. 2020.
mla: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis. 2020.
short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...
---
_id: '21432'
abstract:
- lang: eng
text: "Robots are becoming increasingly autonomous and more capable. Because of
a limited portable energy budget by e.g. batteries, and more demanding algorithms,
an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs)
for example can provide fast and efficient processing and the Robot Operating
System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel
ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework
for integrating reconfigurable hardware. It provides a unified interface between
software and hardware. ReconROS is evaluated in this thesis by implementing a
Sobel filter as the video processing application, running on a Zynq-7000 series
System on Chip. Timing measurements were taken of execution and transfer times
and were compared to theoretical values. Designing the hardware implementation
is done by C code using High Level Synthesis and with the interface and functionality
provided by ReconROS. An important aspect is the publish/subscribe mechanism of
ROS. The Operating System interface functions for publishing and subscribing are
reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface
performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing
to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces
consistency to the execution times and performs twice as fast as the software
implementation."
author:
- first_name: Luca-Sebastian
full_name: Henke, Luca-Sebastian
last_name: Henke
citation:
ama: Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application.; 2020.
apa: Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a
Video Processing Application.
bibtex: '@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based
on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020}
}'
chicago: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based
on a Video Processing Application, 2020.
ieee: L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing
Application. 2020.
mla: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on
a Video Processing Application. 2020.
short: L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application, 2020.
date_created: 2021-03-10T07:07:01Z
date_updated: 2022-01-06T06:54:59Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
type: bachelorsthesis
user_id: '60323'
year: '2020'
...
---
_id: '21584'
author:
- first_name: Carlos Paiz
full_name: Gatica, Carlos Paiz
last_name: Gatica
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions
on Edge-Devices using Reconfigurable Architectures. In: Machine Learning for
Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg; 2020. doi:10.1007/978-3-662-59084-3_9'
apa: Gatica, C. P., & Platzner, M. (2020). Adaptable Realization of Industrial
Analytics Functions on Edge-Devices using Reconfigurable Architectures. In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-59084-3_9
bibtex: '@inproceedings{Gatica_Platzner_2020, place={Berlin, Heidelberg}, title={Adaptable
Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable
Architectures}, DOI={10.1007/978-3-662-59084-3_9},
booktitle={Machine Learning for Cyber Physical Systems (ML4CPS 2017)}, author={Gatica,
Carlos Paiz and Platzner, Marco}, year={2020} }'
chicago: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg, 2020.
https://doi.org/10.1007/978-3-662-59084-3_9.
ieee: C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics
Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning
for Cyber Physical Systems (ML4CPS 2017), 2020.
mla: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” Machine
Learning for Cyber Physical Systems (ML4CPS 2017), 2020, doi:10.1007/978-3-662-59084-3_9.
short: 'C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems
(ML4CPS 2017), Berlin, Heidelberg, 2020.'
date_created: 2021-03-31T08:58:59Z
date_updated: 2022-01-06T06:55:06Z
department:
- _id: '78'
doi: 10.1007/978-3-662-59084-3_9
language:
- iso: eng
place: Berlin, Heidelberg
publication: Machine Learning for Cyber Physical Systems (ML4CPS 2017)
publication_identifier:
isbn:
- '9783662590836'
- '9783662590843'
issn:
- 2522-8579
- 2522-8587
publication_status: published
status: public
title: Adaptable Realization of Industrial Analytics Functions on Edge-Devices using
Reconfigurable Architectures
type: conference
user_id: '398'
year: '2020'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '17369'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings.
International Journal of Hybrid intelligent Systems. 2020.
apa: Ho, N., Kaufmann, P., & Platzner, M. (2020). Evolution of Application-Specific
Cache Mappings. International Journal of Hybrid Intelligent Systems.
bibtex: '@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific
Cache Mappings}, journal={International Journal of Hybrid intelligent Systems},
publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco},
year={2020} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific
Cache Mappings.” International Journal of Hybrid Intelligent Systems, 2020.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache
Mappings,” International Journal of Hybrid intelligent Systems, 2020.
mla: Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” International
Journal of Hybrid Intelligent Systems, IOS Press, 2020.
short: N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent
Systems (2020).
date_created: 2020-07-10T18:55:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
language:
- iso: eng
publication: International Journal of Hybrid intelligent Systems
publisher: IOS Press
status: public
title: Evolution of Application-Specific Cache Mappings
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '20748'
abstract:
- lang: eng
text: "On the circuit level, the design paradigm Approximate Computing seeks to
trade off computational accuracy against a target metric, e.g., energy consumption.
This trade-off is possible for many applications due to their inherent resiliency
against inaccuracies.\r\nIn the past, several automated approximation frameworks
have been presented, which either utilize designated approximation techniques
or libraries to replace approximable circuit parts with inaccurate versions. The
frameworks invoke a search algorithm to iteratively explore the search space of
performance degraded circuits, and validate their quality individually. \r\nIn
this paper, we propose to reverse this procedure. Rather than exploring the search
space, we delineate the approximate parts of the search space which are guaranteed
to lead to valid approximate circuits. Our methodology is supported by formal
verification and independent of approximation techniques. Eventually, the user
is provided with quality bounds of the individual approximable circuit parts.
Consequently, our approach guarantees that any approximate circuit which implements
these parts within the determined quality constraints satisfies the global quality
constraints, superseding a subsequent quality verification.\r\nIn our experimental
results, we present the runtimes of our approach."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC
Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization
for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
bibtex: '@article{Witschen_Wiersema_Platzner, title={Search Space Characterization
for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search
Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing
(AxC 2020), n.d.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization
for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020).
.
mla: Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.”
Fifth Workshop on Approximate Computing (AxC 2020).
short: L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing
(AxC 2020) (n.d.).
date_created: 2020-12-15T15:13:49Z
date_updated: 2022-01-06T06:54:35Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-12-15T15:11:06Z
date_updated: 2020-12-15T15:11:06Z
file_id: '20749'
file_name: witschen20_axc.pdf
file_size: 250870
relation: main_file
success: 1
file_date_updated: 2020-12-15T15:11:06Z
has_accepted_license: '1'
language:
- iso: eng
page: '2'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: Fifth Workshop on Approximate Computing (AxC 2020)
publication_status: accepted
status: public
title: Search Space Characterization for AxC Synthesis
type: preprint
user_id: '3118'
year: '2020'
...
---
_id: '20750'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for
ROS2 Applications. In: Proceedings of the 2020 International Conference on
Field-Programmable Technology (FPT). ; 2020.'
apa: 'Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware
Acceleration for ROS2 Applications. In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT).'
bibtex: '@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware
Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian
and Platzner, Marco and Rinner, Bernhard}, year={2020} }'
chicago: 'Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible
Hardware Acceleration for ROS2 Applications.” In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
ieee: 'C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration
for ROS2 Applications,” in Proceedings of the 2020 International Conference
on Field-Programmable Technology (FPT), 2020.'
mla: 'Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2
Applications.” Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT), 2020.'
short: 'C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
conference:
end_date: 2020-12-11
name: International Conference on Field Programmable Technology (ICFPT)
start_date: 2020-12-09
date_created: 2020-12-16T05:20:01Z
date_updated: 2022-01-06T06:54:35Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT)
status: public
title: 'ReconROS: Flexible Hardware Acceleration for ROS2 Applications'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '20820'
author:
- first_name: Simon
full_name: Thiele, Simon
last_name: Thiele
citation:
ama: Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.;
2020.
apa: Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA
Overlays.
bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
chicago: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA
Overlays, 2020.
ieee: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
mla: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
full_name: Jaganath, Vivek
last_name: Jaganath
citation:
ama: Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows.; 2020.
apa: Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows.
bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
chicago: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level
Synthesis Tool Flows, 2020.
ieee: V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis
Tool Flows. 2020.
mla: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows. 2020.
short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...