---
_id: '3583'
author:
- first_name: Zakarya
full_name: ' Guetttatfi, Zakarya'
last_name: ' Guetttatfi'
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Guetttatfi Z, Kaufmann P, Platzner M. Optimal and Greedy Heuristic Approaches
for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.
In: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC). ; 2020.'
apa: Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices. In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC).
bibtex: '@inproceedings{ Guetttatfi_Kaufmann_Platzner_2020, title={Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices}, booktitle={Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC)}, author={ Guetttatfi, Zakarya and Kaufmann, Paul
and Platzner, Marco}, year={2020} }'
chicago: Guetttatfi, Zakarya, Paul Kaufmann, and Marco Platzner. “Optimal and Greedy
Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable
Computing Devices.” In Proceedings of the International Workshop on Applied
Reconfigurable Computing (ARC), 2020.
ieee: Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic
Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing
Devices,” in Proceedings of the International Workshop on Applied Reconfigurable
Computing (ARC), 2020.
mla: Guetttatfi, Zakarya, et al. “Optimal and Greedy Heuristic Approaches for Scheduling
and Mapping of Hardware Tasks to Reconfigurable Computing Devices.” Proceedings
of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
short: 'Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International
Workshop on Applied Reconfigurable Computing (ARC), 2020.'
date_created: 2018-07-20T14:07:15Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
publication: Proceedings of the International Workshop on Applied Reconfigurable Computing
(ARC)
status: public
title: Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware
Tasks to Reconfigurable Computing Devices
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21324'
author:
- first_name: Khushboo
full_name: Chandrakar, Khushboo
last_name: Chandrakar
citation:
ama: Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis.; 2020.
apa: Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis.
bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
}'
chicago: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to
Improve Approximate Circuit Synthesis, 2020.
ieee: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis. 2020.
mla: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis. 2020.
short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...
---
_id: '21432'
abstract:
- lang: eng
text: "Robots are becoming increasingly autonomous and more capable. Because of
a limited portable energy budget by e.g. batteries, and more demanding algorithms,
an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs)
for example can provide fast and efficient processing and the Robot Operating
System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel
ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework
for integrating reconfigurable hardware. It provides a unified interface between
software and hardware. ReconROS is evaluated in this thesis by implementing a
Sobel filter as the video processing application, running on a Zynq-7000 series
System on Chip. Timing measurements were taken of execution and transfer times
and were compared to theoretical values. Designing the hardware implementation
is done by C code using High Level Synthesis and with the interface and functionality
provided by ReconROS. An important aspect is the publish/subscribe mechanism of
ROS. The Operating System interface functions for publishing and subscribing are
reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface
performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing
to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces
consistency to the execution times and performs twice as fast as the software
implementation."
author:
- first_name: Luca-Sebastian
full_name: Henke, Luca-Sebastian
last_name: Henke
citation:
ama: Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application.; 2020.
apa: Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a
Video Processing Application.
bibtex: '@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based
on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020}
}'
chicago: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based
on a Video Processing Application, 2020.
ieee: L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing
Application. 2020.
mla: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on
a Video Processing Application. 2020.
short: L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application, 2020.
date_created: 2021-03-10T07:07:01Z
date_updated: 2022-01-06T06:54:59Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
type: bachelorsthesis
user_id: '60323'
year: '2020'
...
---
_id: '21584'
author:
- first_name: Carlos Paiz
full_name: Gatica, Carlos Paiz
last_name: Gatica
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Gatica CP, Platzner M. Adaptable Realization of Industrial Analytics Functions
on Edge-Devices using Reconfigurable Architectures. In: Machine Learning for
Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg; 2020. doi:10.1007/978-3-662-59084-3_9'
apa: Gatica, C. P., & Platzner, M. (2020). Adaptable Realization of Industrial
Analytics Functions on Edge-Devices using Reconfigurable Architectures. In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-59084-3_9
bibtex: '@inproceedings{Gatica_Platzner_2020, place={Berlin, Heidelberg}, title={Adaptable
Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable
Architectures}, DOI={10.1007/978-3-662-59084-3_9},
booktitle={Machine Learning for Cyber Physical Systems (ML4CPS 2017)}, author={Gatica,
Carlos Paiz and Platzner, Marco}, year={2020} }'
chicago: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” In Machine
Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg, 2020.
https://doi.org/10.1007/978-3-662-59084-3_9.
ieee: C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics
Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning
for Cyber Physical Systems (ML4CPS 2017), 2020.
mla: Gatica, Carlos Paiz, and Marco Platzner. “Adaptable Realization of Industrial
Analytics Functions on Edge-Devices Using Reconfigurable Architectures.” Machine
Learning for Cyber Physical Systems (ML4CPS 2017), 2020, doi:10.1007/978-3-662-59084-3_9.
short: 'C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems
(ML4CPS 2017), Berlin, Heidelberg, 2020.'
date_created: 2021-03-31T08:58:59Z
date_updated: 2022-01-06T06:55:06Z
department:
- _id: '78'
doi: 10.1007/978-3-662-59084-3_9
language:
- iso: eng
place: Berlin, Heidelberg
publication: Machine Learning for Cyber Physical Systems (ML4CPS 2017)
publication_identifier:
isbn:
- '9783662590836'
- '9783662590843'
issn:
- 2522-8579
- 2522-8587
publication_status: published
status: public
title: Adaptable Realization of Industrial Analytics Functions on Edge-Devices using
Reconfigurable Architectures
type: conference
user_id: '398'
year: '2020'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '17369'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Ho N, Kaufmann P, Platzner M. Evolution of Application-Specific Cache Mappings.
International Journal of Hybrid intelligent Systems. 2020.
apa: Ho, N., Kaufmann, P., & Platzner, M. (2020). Evolution of Application-Specific
Cache Mappings. International Journal of Hybrid Intelligent Systems.
bibtex: '@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific
Cache Mappings}, journal={International Journal of Hybrid intelligent Systems},
publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco},
year={2020} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolution of Application-Specific
Cache Mappings.” International Journal of Hybrid Intelligent Systems, 2020.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache
Mappings,” International Journal of Hybrid intelligent Systems, 2020.
mla: Ho, Nam, et al. “Evolution of Application-Specific Cache Mappings.” International
Journal of Hybrid Intelligent Systems, IOS Press, 2020.
short: N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid Intelligent
Systems (2020).
date_created: 2020-07-10T18:55:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
language:
- iso: eng
publication: International Journal of Hybrid intelligent Systems
publisher: IOS Press
status: public
title: Evolution of Application-Specific Cache Mappings
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '20748'
abstract:
- lang: eng
text: "On the circuit level, the design paradigm Approximate Computing seeks to
trade off computational accuracy against a target metric, e.g., energy consumption.
This trade-off is possible for many applications due to their inherent resiliency
against inaccuracies.\r\nIn the past, several automated approximation frameworks
have been presented, which either utilize designated approximation techniques
or libraries to replace approximable circuit parts with inaccurate versions. The
frameworks invoke a search algorithm to iteratively explore the search space of
performance degraded circuits, and validate their quality individually. \r\nIn
this paper, we propose to reverse this procedure. Rather than exploring the search
space, we delineate the approximate parts of the search space which are guaranteed
to lead to valid approximate circuits. Our methodology is supported by formal
verification and independent of approximation techniques. Eventually, the user
is provided with quality bounds of the individual approximable circuit parts.
Consequently, our approach guarantees that any approximate circuit which implements
these parts within the determined quality constraints satisfies the global quality
constraints, superseding a subsequent quality verification.\r\nIn our experimental
results, we present the runtimes of our approach."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC
Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization
for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
bibtex: '@article{Witschen_Wiersema_Platzner, title={Search Space Characterization
for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)},
author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }'
chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search
Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing
(AxC 2020), n.d.
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization
for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020).
.
mla: Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.”
Fifth Workshop on Approximate Computing (AxC 2020).
short: L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing
(AxC 2020) (n.d.).
date_created: 2020-12-15T15:13:49Z
date_updated: 2022-01-06T06:54:35Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-12-15T15:11:06Z
date_updated: 2020-12-15T15:11:06Z
file_id: '20749'
file_name: witschen20_axc.pdf
file_size: 250870
relation: main_file
success: 1
file_date_updated: 2020-12-15T15:11:06Z
has_accepted_license: '1'
language:
- iso: eng
page: '2'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: Fifth Workshop on Approximate Computing (AxC 2020)
publication_status: accepted
status: public
title: Search Space Characterization for AxC Synthesis
type: preprint
user_id: '3118'
year: '2020'
...
---
_id: '20750'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Lienen C, Platzner M, Rinner B. ReconROS: Flexible Hardware Acceleration for
ROS2 Applications. In: Proceedings of the 2020 International Conference on
Field-Programmable Technology (FPT). ; 2020.'
apa: 'Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware
Acceleration for ROS2 Applications. In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT).'
bibtex: '@inproceedings{Lienen_Platzner_Rinner_2020, title={ReconROS: Flexible Hardware
Acceleration for ROS2 Applications}, booktitle={Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT)}, author={Lienen, Christian
and Platzner, Marco and Rinner, Bernhard}, year={2020} }'
chicago: 'Lienen, Christian, Marco Platzner, and Bernhard Rinner. “ReconROS: Flexible
Hardware Acceleration for ROS2 Applications.” In Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
ieee: 'C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration
for ROS2 Applications,” in Proceedings of the 2020 International Conference
on Field-Programmable Technology (FPT), 2020.'
mla: 'Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for ROS2
Applications.” Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT), 2020.'
short: 'C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International
Conference on Field-Programmable Technology (FPT), 2020.'
conference:
end_date: 2020-12-11
name: International Conference on Field Programmable Technology (ICFPT)
start_date: 2020-12-09
date_created: 2020-12-16T05:20:01Z
date_updated: 2022-01-06T06:54:35Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 2020 International Conference on Field-Programmable
Technology (FPT)
status: public
title: 'ReconROS: Flexible Hardware Acceleration for ROS2 Applications'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '20820'
author:
- first_name: Simon
full_name: Thiele, Simon
last_name: Thiele
citation:
ama: Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.;
2020.
apa: Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA
Overlays.
bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
chicago: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA
Overlays, 2020.
ieee: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
mla: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
full_name: Jaganath, Vivek
last_name: Jaganath
citation:
ama: Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows.; 2020.
apa: Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows.
bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
chicago: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level
Synthesis Tool Flows, 2020.
ieee: V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis
Tool Flows. 2020.
mla: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows. 2020.
short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '17063'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold
of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764.
doi:10.1145/3377929.3398106'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism
for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO
’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion},
publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim
and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “An Adaption Mechanism
for the Error Threshold of XCSF.” In GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion, 1756–64. New York, NY,
United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3398106.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the
Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi:
10.1145/3377929.3398106.'
mla: 'Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.”
GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference
Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: International Workshop on Learning Classifier Systems (IWLCS 2020)
start_date: 2020-07-08
date_created: 2020-05-27T14:14:58Z
date_updated: 2022-01-06T06:53:03Z
department:
- _id: '78'
doi: 10.1145/3377929.3398106
language:
- iso: eng
page: 1756-1764
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Adaption Mechanism for the Error Threshold of XCSF
type: conference
user_id: '477'
year: '2020'
...
---
_id: '17092'
abstract:
- lang: eng
text: Radiation tolerance in FPGAs is an important field of research particularly
for reliable computation in electronics used in aerospace and satellite missions.
The motivation behind this research is the degradation of reliability in FPGA
hardware due to single-event effects caused by radiation particles. Redundancy
is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive
applications. However, redundancy comes with an overhead in terms of excessive
area consumption, latency, and power dissipation. Moreover, the redundant circuit
implementations vary in structure and resource usage with the redundancy insertion
algorithms as well as number of used redundant stages. The radiation environment
varies during the operation time span of the mission depending on the orbit and
space weather conditions. Therefore, the overheads due to redundancy should also
be optimized at run-time with respect to the current radiation level. In this
paper, we propose a technique called Dynamic Reliability Management (DRM) that
utilizes the radiation data, interprets it, selects a suitable redundancy level,
and performs the run-time reconfiguration, thus varying the reliability levels
of the target computation modules. DRM is composed of two parts. The design-time
tool flow of DRM generates a library of various redundant implementations of the
circuit with different magnitudes of performance factors. The run-time tool flow,
while utilizing the radiation/error-rate data, selects a required redundancy level
and reconfigures the computation module with the corresponding redundant implementation.
Both parts of DRM have been verified by experimentation on various benchmarks.
The most significant finding we have from this experimentation is that the performance
can be scaled multiple times by using partial reconfiguration feature of DRM,
e.g., 7.7 and 3.7 times better performance results obtained for our data sorter
and matrix multiplier case studies compared with static reliability management
techniques. Therefore, DRM allows for maintaining a suitable trade-off between
computation reliability and performance overhead during run-time of an application.
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Meisner S, Platzner M. Dynamic Reliability Management for FPGA-Based
Systems. International Journal of Reconfigurable Computing. 2020:1-19.
doi:10.1155/2020/2808710
apa: Anwer, J., Meisner, S., & Platzner, M. (2020). Dynamic Reliability Management
for FPGA-Based Systems. International Journal of Reconfigurable Computing,
1–19. https://doi.org/10.1155/2020/2808710
bibtex: '@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management
for FPGA-Based Systems}, DOI={10.1155/2020/2808710},
journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb
and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }'
chicago: Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management for FPGA-Based Systems.” International Journal of Reconfigurable
Computing, 2020, 1–19. https://doi.org/10.1155/2020/2808710.
ieee: J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for
FPGA-Based Systems,” International Journal of Reconfigurable Computing,
pp. 1–19, 2020.
mla: Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.”
International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710.
short: J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable
Computing (2020) 1–19.
date_created: 2020-06-15T11:25:07Z
date_updated: 2022-01-06T06:53:04Z
department:
- _id: '78'
doi: 10.1155/2020/2808710
language:
- iso: eng
page: 1-19
publication: International Journal of Reconfigurable Computing
publication_identifier:
issn:
- 1687-7195
- 1687-7209
publication_status: published
status: public
title: Dynamic Reliability Management for FPGA-Based Systems
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '15836'
author:
- first_name: K.
full_name: Bellman, K.
last_name: Bellman
- first_name: N.
full_name: Dutt, N.
last_name: Dutt
- first_name: L.
full_name: Esterle, L.
last_name: Esterle
- first_name: A.
full_name: Herkersdorf, A.
last_name: Herkersdorf
- first_name: A.
full_name: Jantsch, A.
last_name: Jantsch
- first_name: C.
full_name: Landauer, C.
last_name: Landauer
- first_name: P.
full_name: R. Lewis, P.
last_name: R. Lewis
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: N.
full_name: TaheriNejad, N.
last_name: TaheriNejad
- first_name: K.
full_name: Tammemäe, K.
last_name: Tammemäe
citation:
ama: Bellman K, Dutt N, Esterle L, et al. Self-aware Cyber-Physical Systems. ACM
Transactions on Cyber-Physical Systems. 2020;Accepted for Publication:1-24.
apa: Bellman, K., Dutt, N., Esterle, L., Herkersdorf, A., Jantsch, A., Landauer,
C., … Tammemäe, K. (2020). Self-aware Cyber-Physical Systems. ACM Transactions
on Cyber-Physical Systems, Accepted for Publication, 1–24.
bibtex: '@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020,
title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication},
journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and
Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C.
and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020},
pages={1–24} }'
chicago: 'Bellman, K., N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, Marco Platzner, N. TaheriNejad, and K. Tammemäe. “Self-Aware Cyber-Physical
Systems.” ACM Transactions on Cyber-Physical Systems Accepted for Publication
(2020): 1–24.'
ieee: K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
mla: Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.
short: K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical
Systems Accepted for Publication (2020) 1–24.
date_created: 2020-02-06T15:05:45Z
date_updated: 2022-01-06T06:52:37Z
department:
- _id: '78'
language:
- iso: eng
page: 1-24
publication: ACM Transactions on Cyber-Physical Systems
status: public
title: Self-aware Cyber-Physical Systems
type: journal_article
user_id: '398'
volume: Accepted for Publication
year: '2020'
...
---
_id: '16213'
abstract:
- lang: eng
text: 'Automated synthesis of approximate circuits via functional approximations
is of prominent importance to provide efficiency in energy, runtime, and chip
area required to execute an application. Approximate circuits are usually obtained
either through analytical approximation methods leveraging approximate transformations
such as bit-width scaling or via iterative search-based optimization methods when
a library of approximate components, e.g., approximate adders and multipliers,
is available. For the latter, exploring the extremely large design space is challenging
in terms of both computations and quality of results. While the combination of
both methods can create more room for further approximations, the \textit{Design
Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such
a hybrid synthesis methodology that applies a low-cost analytical method followed
by parallel stochastic search-based optimization. We address the DSE challenge
through efficient pruning of the design space and skipping unnecessary expensive
testing and/or verification steps. The experimental results reveal up to 10.57x
area savings in comparison with both purely analytical or search-based approaches. '
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology
for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid
Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China:
ACM. https://doi.org/10.1145/3386263.3406952'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid
Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952},
booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan
and Platzner, Marco}, year={2020}, pages={421–426} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid
Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology
for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
mla: Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”
Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020,
ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.'
conference:
location: Beijing, China
name: ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
date_created: 2020-03-02T15:49:38Z
date_updated: 2022-01-06T06:52:45Z
department:
- _id: '78'
doi: 10.1145/3386263.3406952
language:
- iso: eng
page: 421-426
publication: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
publication_status: published
publisher: ACM
status: public
title: A Hybrid Synthesis Methodology for Approximate Circuits
type: conference
user_id: '64665'
year: '2020'
...
---
_id: '16363'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments
via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. New York, NY, United States:
Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126).
New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive
Error Threshold}, DOI={10.1145/3377929.3389968},
booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126}
}'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 125–26.
New York, NY, United States: Association for Computing Machinery (ACM), 2020.
https://doi.org/10.1145/3377929.3389968.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic
Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico,
2020, pp. 125–126.'
mla: 'Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via
an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Association for Computing Machinery (ACM),
2020, pp. 125–26, doi:10.1145/3377929.3389968.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: The Genetic and Evolutionary Computation Conference (GECCO 2020)
start_date: 2020-07-08
date_created: 2020-04-02T10:07:10Z
date_updated: 2022-01-06T06:52:49Z
department:
- _id: '78'
doi: 10.1145/3377929.3389968
language:
- iso: eng
page: 125-126
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold
type: conference
user_id: '477'
year: '2020'
...
---
_id: '20838'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020.'
date_created: 2020-12-23T09:07:11Z
date_updated: 2023-01-03T22:07:12Z
department:
- _id: '78'
doi: 10.1109/ipdpsw50202.2020.00012
language:
- iso: eng
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
isbn:
- '9781728174457'
publication_status: published
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '35152'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020:6-16. doi:10.1109/IPDPSW50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 6–16. https://doi.org/10.1109/IPDPSW50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/IPDPSW50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020}, pages={6–16}
}'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 6–16, 2020. https://doi.org/10.1109/IPDPSW50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” in 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi: 10.1109/IPDPSW50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi:10.1109/IPDPSW50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16.'
date_created: 2023-01-03T22:05:08Z
date_updated: 2024-04-30T09:14:00Z
department:
- _id: '78'
doi: 10.1109/IPDPSW50202.2020.00012
page: 6-16
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
text: "Modern machine learning (ML) techniques continue to move into the embedded
system space because traditional centralized compute resources do not suit certain
application domains, for example in mobile or real-time environments. Google’s
TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
and makes ML inference accessible on resource-constrained devices. While it offers
the possibility to partially delegate computation to hardware accelerators, there
is no such “delegate” available to utilize the promising characteristics of reconfigurable
hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
a modular delegate framework, which allows accelerators within the programmable
logic to take over the execution of neural network layers. To facilitate the necessary
hardware/software codesign, the FPGA delegate is based on the operating system
for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
enables the instantiation of model-tailored accelerator architectures. In the
hardware back-end, a streaming-based prototype accelerator for the MobileNet model
family showcases the working order of the platform, but falls short of the desired
performance. Thus, it indicates the need for further exploration of alternative
accelerator designs, which the delegate could automatically synthesize to meet
a model’s demands."
author:
- first_name: Felix P.
full_name: Jentzsch, Felix P.
last_name: Jentzsch
citation:
ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture.; 2020.
apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture.
bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
}'
chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture, 2020.
ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture. 2020.
mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture. 2020.
short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '3585'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
volume={99}, DOI={10.1016/j.microrel.2019.04.003},
journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019):
277–90. https://doi.org/10.1016/j.microrel.2019.04.003.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Microelectronics Reliability, vol. 99, pp. 277–290, 2019.'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Microelectronics Reliability,
vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Microelectronics Reliability 99 (2019) 277–290.
date_created: 2018-07-20T14:08:49Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
doi: 10.1016/j.microrel.2019.04.003
intvolume: ' 99'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: 277-290
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Microelectronics Reliability
publication_identifier:
issn:
- 0026-2714
publication_status: published
publisher: Elsevier
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: journal_article
user_id: '49051'
volume: 99
year: '2019'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...