--- _id: '3365' author: - first_name: Jan-Philip full_name: Schnuer, Jan-Philip last_name: Schnuer citation: ama: Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn; 2018. apa: Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn. bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }' chicago: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018. ieee: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018. mla: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018. short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes, Universität Paderborn, 2018. date_created: 2018-06-26T14:10:18Z date_updated: 2022-01-06T06:59:13Z department: - _id: '78' language: - iso: eng project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C publisher: Universität Paderborn status: public supervisor: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Static Scheduling Algorithms for Heterogeneous Compute Nodes type: bachelorsthesis user_id: '477' year: '2018' ... --- _id: '3366' author: - first_name: Marcel full_name: Croce, Marcel last_name: Croce citation: ama: Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn; 2018. apa: Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn. bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }' chicago: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018. ieee: M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn, 2018. mla: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018. short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn, 2018. date_created: 2018-06-26T14:12:00Z date_updated: 2022-01-06T06:59:13Z department: - _id: '78' language: - iso: eng project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C publisher: Universität Paderborn status: public supervisor: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Evaluation of OpenCL-based Compilation for FPGAs type: bachelorsthesis user_id: '477' year: '2018' ... --- _id: '3373' abstract: - lang: eng text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. author: - first_name: Tim full_name: Hansmeier, Tim id: '49992' last_name: Hansmeier orcid: 0000-0003-1377-3339 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: David full_name: Andrews, David last_name: Andrews citation: ama: 'Hansmeier T, Platzner M, Andrews D. An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Vol 10824. Lecture Notes in Computer Science. Springer International Publishing; 2018:153-165. doi:10.1007/978-3-319-78890-6_13' apa: 'Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini, Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13' bibtex: '@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking}, volume={10824}, DOI={10.1007/978-3-319-78890-6_13}, booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture Notes in Computer Science} }' chicago: 'Hansmeier, Tim, Marco Platzner, and David Andrews. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, 10824:153–65. Lecture Notes in Computer Science. Springer International Publishing, 2018. https://doi.org/10.1007/978-3-319-78890-6_13.' ieee: 'T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824, pp. 153–165.' mla: 'Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.” ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, vol. 10824, Springer International Publishing, 2018, pp. 153–65, doi:10.1007/978-3-319-78890-6_13.' short: 'T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2018, pp. 153–165.' conference: end_date: 2018-05-04 location: Santorini, Greece name: 'ARC: International Symposium on Applied Reconfigurable Computing' start_date: 2018-05-02 date_created: 2018-06-27T09:30:24Z date_updated: 2022-01-06T06:59:13Z ddc: - '000' department: - _id: '78' doi: 10.1007/978-3-319-78890-6_13 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T13:55:07Z date_updated: 2018-11-02T13:55:07Z file_id: '5257' file_name: AnFPGAHMC-BasedAcceleratorForR.pdf file_size: 612367 relation: main_file success: 1 file_date_updated: 2018-11-02T13:55:07Z has_accepted_license: '1' intvolume: ' 10824' language: - iso: eng page: 153-165 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication: 'ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications' publication_identifier: isbn: - '9783319788890' - '9783319788906' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer International Publishing series_title: Lecture Notes in Computer Science status: public title: An FPGA/HMC-Based Accelerator for Resolution Proof Checking type: conference user_id: '3118' volume: 10824 year: '2018' ... --- _id: '3586' abstract: - lang: eng text: Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).' apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).' bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018), n.d.' ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). .' mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).' short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Third Workshop on Approximate Computing (AxC 2018) (n.d.). date_created: 2018-07-20T14:10:46Z date_updated: 2022-01-06T06:59:26Z ddc: - '000' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: tobias82 date_created: 2018-07-20T14:13:31Z date_updated: 2018-07-20T14:13:31Z file_id: '3587' file_name: WitschenWMAP2018.pdf file_size: 285348 relation: main_file success: 1 file_date_updated: 2018-07-20T14:13:31Z has_accepted_license: '1' keyword: - Approximate Computing - Framework - Pareto Front - Accuracy language: - iso: eng page: '6' project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Third Workshop on Approximate Computing (AxC 2018) publication_status: accepted status: public title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation' type: preprint user_id: '49051' year: '2018' ... --- _id: '3720' abstract: - lang: eng text: Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches. - lang: ger text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion. Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen, kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware. Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen, wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz im Vergleich zu konventionellen Caches erhöhen können. author: - first_name: Nam full_name: Ho, Nam last_name: Ho citation: ama: 'Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376' apa: 'Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376' bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }' chicago: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.' ieee: 'N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018.' mla: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.' short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization, Universität Paderborn, 2018.' date_created: 2018-07-27T06:41:13Z date_updated: 2022-01-06T06:59:31Z department: - _id: '78' doi: 10.17619/UNIPB/1-376 language: - iso: eng page: '139' project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication_status: published publisher: Universität Paderborn status: public supervisor: - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization' type: dissertation user_id: '477' year: '2018' ... --- _id: '1165' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018. apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018} }' chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018. ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018. mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018. short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018). date_created: 2018-02-01T14:24:54Z date_updated: 2022-01-06T06:51:06Z ddc: - '000' department: - _id: '7' - _id: '34' - _id: '78' file: - access_level: closed content_type: application/pdf creator: tobias82 date_created: 2018-11-26T08:00:53Z date_updated: 2018-11-26T08:00:53Z file_id: '5821' file_name: WitschenWP2018[1].pdf file_size: 287224 relation: main_file success: 1 file_date_updated: 2018-11-26T08:00:53Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 4th Workshop On Approximate Computing (WAPCO 2018) status: public title: Making the Case for Proof-carrying Approximate Circuits type: preprint user_id: '49051' year: '2018' ... --- _id: '5547' author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018. doi:10.1109/asap.2018.8445098' apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098' bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }' chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098. ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 2018. mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018, doi:10.1109/asap.2018.8445098. short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.' conference: end_date: 2018-07-12 location: Milan, Italy name: The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors start_date: 2018-07-10 date_created: 2018-11-14T09:26:53Z date_updated: 2022-01-06T07:01:59Z ddc: - '040' department: - _id: '78' doi: 10.1109/asap.2018.8445098 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T09:40:42Z date_updated: 2018-11-14T09:40:42Z file_id: '5552' file_name: loesch_asap2018.pdf file_size: 2464949 relation: main_file success: 1 file_date_updated: 2018-11-14T09:40:42Z has_accepted_license: '1' language: - iso: eng project: - _id: '14' name: SFB 901 - Subproject C2 - _id: '4' name: SFB 901 - Project Area C - _id: '1' name: SFB 901 publication: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) publication_identifier: isbn: - '9781538674796' publication_status: published publisher: IEEE status: public title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes type: conference user_id: '43646' year: '2018' ... --- _id: '10598' abstract: - lang: eng text: "Approximate computing has become a very popular design\r\nstrategy that exploits error resilient computations to achieve higher\r\nperformance and energy efficiency. Automated synthesis of approximate\r\ncircuits is performed via functional approximation, in which various\r\nparts of the target circuit are extensively examined with a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy and computational budget (i.e., power). However, as the number\r\nof possible approximate transformations increases, traditional search\r\ntechniques suffer from a combinatorial explosion due to the large\r\nbranching factor. In this work, we present a comprehensive framework\r\nfor automated synthesis of approximate circuits from either structural\r\nor behavioral descriptions. We adapt the Monte Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the large design\r\nspace exploration, which enables a broader range of potential possible\r\napproximations through lightweight random simulations. The proposed\r\nframework is able to recognize the design Pareto set even with low\r\ncomputational budgets. Experimental results highlight the capabilities of\r\nthe proposed synthesis framework by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined quality constraints." author: - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026' apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026 bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026}, booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2018}, pages={219–224} }' chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 219–24, 2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026. ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224. mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026. short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.' date_created: 2019-07-10T09:21:38Z date_updated: 2022-01-06T06:50:46Z department: - _id: '78' doi: 10.1109/VLSI-SoC.2018.8645026 keyword: - Approximate computing - High-level synthesis - Accuracy - Monte-Carlo tree search - Circuit simulation language: - iso: eng page: 219-224 publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) status: public title: An MCTS-based Framework for Synthesis of Approximate Circuits type: conference user_id: '64665' year: '2018' ... --- _id: '10782' author: - first_name: Lennart full_name: Clausing, Lennart id: '74287' last_name: Clausing orcid: 0000-0003-3789-6034 citation: ama: Clausing L. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018. apa: Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum. bibtex: '@book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }' chicago: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018. ieee: L. Clausing, Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum, 2018. mla: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018. short: L. Clausing, Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018. date_created: 2019-07-10T12:13:18Z date_updated: 2022-01-06T06:50:50Z department: - _id: '78' extern: '1' language: - iso: eng publisher: Ruhr-University Bochum status: public title: Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data type: mastersthesis user_id: '3118' year: '2018' ... --- _id: '1097' author: - first_name: Felix Paul full_name: Jentzsch, Felix Paul last_name: Jentzsch citation: ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018. apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn. bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }' chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018. ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018. mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018. short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018. date_created: 2018-01-15T16:48:05Z date_updated: 2022-01-06T06:50:54Z department: - _id: '78' keyword: - Approximate Computing - Proof-Carrying Hardware - Formal Verification language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publisher: Universität Paderborn status: public supervisor: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema title: Enforcing IP Core Connection Properties with Verifiable Security Monitors type: bachelorsthesis user_id: '477' year: '2018' ... --- _id: '12965' author: - first_name: Ines full_name: Ghribi, Ines last_name: Ghribi - first_name: Riadh Ben full_name: Abdallah, Riadh Ben last_name: Abdallah - first_name: Mohamed full_name: Khalgui, Mohamed last_name: Khalgui - first_name: Zhiwu full_name: Li, Zhiwu last_name: Li - first_name: Khalid full_name: Alnowibet, Khalid last_name: Alnowibet - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852' apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner, M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852' bibtex: '@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={10.1109/access.2018.2799852}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }' chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet, and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92. https://doi.org/10.1109/access.2018.2799852.' ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.' mla: 'Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92, doi:10.1109/access.2018.2799852.' short: I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018) 14078–14092. date_created: 2019-08-26T13:33:00Z date_updated: 2022-01-06T06:51:27Z department: - _id: '78' doi: 10.1109/access.2018.2799852 language: - iso: eng page: 14078-14092 publication: IEEE Access publication_identifier: issn: - 2169-3536 publication_status: published status: public title: 'R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints' type: journal_article user_id: '398' year: '2018' ... --- _id: '3580' author: - first_name: Tim full_name: Hansmeier, Tim id: '49992' last_name: Hansmeier orcid: 0000-0003-1377-3339 citation: ama: Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn; 2017. apa: Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn. bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }' chicago: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017. ieee: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017. mla: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017. short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität Paderborn, 2017. date_created: 2018-07-20T13:44:34Z date_updated: 2022-01-06T06:59:25Z department: - _id: '78' - _id: '34' - _id: '7' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publisher: Universität Paderborn status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: An FPGA Accelerator for Checking Resolution Proofs type: bachelorsthesis user_id: '3118' year: '2017' ... --- _id: '1157' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen citation: ama: Witschen LM. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn; 2017. apa: Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits. Universität Paderborn. bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }' chicago: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017. ieee: L. M. Witschen, A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017. mla: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017. short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität Paderborn, 2017. date_created: 2018-02-01T14:21:19Z date_updated: 2022-01-06T06:51:03Z department: - _id: '78' - _id: '7' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publisher: Universität Paderborn status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema title: A Framework for the Synthesis of Approximate Circuits type: mastersthesis user_id: '477' year: '2017' ... --- _id: '74' author: - first_name: Christoph full_name: Knorr, Christoph last_name: Knorr citation: ama: Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn; 2017. apa: Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn. bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }' chicago: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017. ieee: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017. mla: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017. short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten, Universität Paderborn, 2017. date_created: 2017-10-17T12:41:05Z date_updated: 2022-01-06T07:03:36Z department: - _id: '78' language: - iso: ger project: - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publisher: Universität Paderborn status: public supervisor: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten type: mastersthesis user_id: '477' year: '2017' ... --- _id: '9919' abstract: - lang: eng text: This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network. author: - first_name: Cong full_name: Shen, Cong last_name: Shen - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Martin full_name: Braun, Martin last_name: Braun citation: ama: Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017;94:287-299. doi:10.1016/j.ijepes.2017.07.007 apa: Shen, C., Kaufmann, P., & Braun, M. (2017). Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 94, 287–299. https://doi.org/10.1016/j.ijepes.2017.07.007 bibtex: '@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={287–299} }' chicago: 'Shen, Cong, Paul Kaufmann, and Martin Braun. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017): 287–99. https://doi.org/10.1016/j.ijepes.2017.07.007.' ieee: C. Shen, P. Kaufmann, and M. Braun, “Three-Stage Power System Restoration Methodology Considering Renewable Energies,” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, pp. 287–299, 2017. mla: Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007. short: C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) 94 (2017) 287–299. date_created: 2019-05-22T13:14:20Z date_updated: 2019-10-06T21:56:18Z department: - _id: '78' doi: 10.1016/j.ijepes.2017.07.007 intvolume: ' 94' keyword: - Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations language: - iso: eng page: 287-299 publication: Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) publication_status: published status: public title: Three-Stage Power System Restoration Methodology Considering Renewable Energies type: journal_article user_id: '3118' volume: 94 year: '2017' ... --- _id: '65' abstract: - lang: eng text: Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272' apa: 'Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272' bibtex: '@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }' chicago: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.' ieee: 'A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017.' mla: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.' short: 'A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.' date_created: 2017-10-17T12:41:04Z date_updated: 2022-01-06T07:03:08Z ddc: - '040' department: - _id: '78' doi: 10.1109/ASAP.2017.7995272 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T09:37:55Z date_updated: 2018-11-14T09:37:55Z file_id: '5550' file_name: loesch_asap2017.pdf file_size: 467545 relation: main_file success: 1 file_date_updated: 2018-11-14T09:37:55Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) status: public title: 'reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements' type: conference user_id: '477' year: '2017' ... --- _id: '68' abstract: - lang: eng text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. author: - first_name: Tobias full_name: Isenberg, Tobias last_name: Isenberg - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems. 2017;(4):61:1--61:23. doi:10.1145/3054743 apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743 bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={10.1145/3054743}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }' chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.' ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017. mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743. short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23. date_created: 2017-10-17T12:41:04Z date_updated: 2022-01-06T07:03:20Z ddc: - '000' department: - _id: '77' - _id: '78' doi: 10.1145/3054743 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T16:08:17Z date_updated: 2018-11-02T16:08:17Z file_id: '5324' file_name: a61-isenberg.pdf file_size: 806356 relation: main_file success: 1 file_date_updated: 2018-11-02T16:08:17Z has_accepted_license: '1' issue: '4' language: - iso: eng page: 61:1--61:23 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: ACM Transactions on Design Automation of Electronic Systems publisher: ACM status: public title: Proof-Carrying Hardware via Inductive Invariants type: journal_article user_id: '3118' year: '2017' ... --- _id: '10600' author: - first_name: Philip full_name: H.W. Leong, Philip last_name: H.W. Leong - first_name: Hideharu full_name: Amano, Hideharu last_name: Amano - first_name: Jason full_name: Anderson, Jason last_name: Anderson - first_name: Koen full_name: Bertels, Koen last_name: Bertels - first_name: Jo\~{a}o full_name: M.P. Cardoso, Jo\~{a}o last_name: M.P. Cardoso - first_name: Oliver full_name: Diessel, Oliver last_name: Diessel - first_name: Guy full_name: Gogniat, Guy last_name: Gogniat - first_name: Mike full_name: Hutton, Mike last_name: Hutton - first_name: JunKyu full_name: Lee, JunKyu last_name: Lee - first_name: Wayne full_name: Luk, Wayne last_name: Luk - first_name: Patrick full_name: Lysaght, Patrick last_name: Lysaght - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Viktor full_name: K. Prasanna, Viktor last_name: K. Prasanna - first_name: Tero full_name: Rissa, Tero last_name: Rissa - first_name: Cristina full_name: Silvano, Cristina last_name: Silvano - first_name: Hayden full_name: So, Hayden last_name: So - first_name: Yu full_name: Wang, Yu last_name: Wang citation: ama: H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. 2017. doi:10.1145/2996468 apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468 bibtex: '@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={10.1145/2996468}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }' chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017. https://doi.org/10.1145/2996468. ieee: P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017. mla: H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017, doi:10.1145/2996468. short: P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017). date_created: 2019-07-10T09:22:27Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' doi: 10.1145/2996468 language: - iso: eng publication: ACM Transactions on Reconfigurable Technology and Systems status: public title: The First 25 Years of the FPL Conference – Significant Papers type: journal_article user_id: '398' year: '2017' ... --- _id: '10601' author: - first_name: Ronald full_name: F. DeMara, Ronald last_name: F. DeMara - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Marco full_name: Ottavi, Marco last_name: Ottavi citation: ama: 'F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. 2017. doi:10.1109/TETC.2016.2641599' apa: 'F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599' bibtex: '@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }' chicago: 'F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017. https://doi.org/10.1109/TETC.2016.2641599.' ieee: 'R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.' mla: 'F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.' short: R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017). date_created: 2019-07-10T09:22:28Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' doi: 10.1109/TETC.2016.2641599 language: - iso: eng publication: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing status: public title: 'Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)' type: journal_article user_id: '398' year: '2017' ... --- _id: '10611' author: - first_name: Jahanzeb full_name: Anwer, Jahanzeb last_name: Anwer - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172. doi:10.1016/j.micpro.2017.06.002 apa: Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems, 160–172. https://doi.org/10.1016/j.micpro.2017.06.002 bibtex: '@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }' chicago: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, 2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002. ieee: J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” Microprocessors and Microsystems, pp. 160–172, 2017. mla: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems, Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002. short: J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172. date_created: 2019-07-10T09:23:11Z date_updated: 2022-01-06T06:50:47Z department: - _id: '78' doi: 10.1016/j.micpro.2017.06.002 language: - iso: eng page: 160-172 publication: Microprocessors and Microsystems publisher: Elsevier status: public title: Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus type: journal_article user_id: '3118' year: '2017' ...