---
_id: '17063'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. An Adaption Mechanism for the Error Threshold
of XCSF. In: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion. Association for Computing Machinery (ACM); 2020:1756-1764.
doi:10.1145/3377929.3398106'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism
for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and
Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO
’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion},
publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim
and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “An Adaption Mechanism
for the Error Threshold of XCSF.” In GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion, 1756–64. New York, NY,
United States: Association for Computing Machinery (ACM), 2020. https://doi.org/10.1145/3377929.3398106.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the
Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi:
10.1145/3377929.3398106.'
mla: 'Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.”
GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference
Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: International Workshop on Learning Classifier Systems (IWLCS 2020)
start_date: 2020-07-08
date_created: 2020-05-27T14:14:58Z
date_updated: 2022-01-06T06:53:03Z
department:
- _id: '78'
doi: 10.1145/3377929.3398106
language:
- iso: eng
page: 1756-1764
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: An Adaption Mechanism for the Error Threshold of XCSF
type: conference
user_id: '477'
year: '2020'
...
---
_id: '17092'
abstract:
- lang: eng
text: Radiation tolerance in FPGAs is an important field of research particularly
for reliable computation in electronics used in aerospace and satellite missions.
The motivation behind this research is the degradation of reliability in FPGA
hardware due to single-event effects caused by radiation particles. Redundancy
is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive
applications. However, redundancy comes with an overhead in terms of excessive
area consumption, latency, and power dissipation. Moreover, the redundant circuit
implementations vary in structure and resource usage with the redundancy insertion
algorithms as well as number of used redundant stages. The radiation environment
varies during the operation time span of the mission depending on the orbit and
space weather conditions. Therefore, the overheads due to redundancy should also
be optimized at run-time with respect to the current radiation level. In this
paper, we propose a technique called Dynamic Reliability Management (DRM) that
utilizes the radiation data, interprets it, selects a suitable redundancy level,
and performs the run-time reconfiguration, thus varying the reliability levels
of the target computation modules. DRM is composed of two parts. The design-time
tool flow of DRM generates a library of various redundant implementations of the
circuit with different magnitudes of performance factors. The run-time tool flow,
while utilizing the radiation/error-rate data, selects a required redundancy level
and reconfigures the computation module with the corresponding redundant implementation.
Both parts of DRM have been verified by experimentation on various benchmarks.
The most significant finding we have from this experimentation is that the performance
can be scaled multiple times by using partial reconfiguration feature of DRM,
e.g., 7.7 and 3.7 times better performance results obtained for our data sorter
and matrix multiplier case studies compared with static reliability management
techniques. Therefore, DRM allows for maintaining a suitable trade-off between
computation reliability and performance overhead during run-time of an application.
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Meisner S, Platzner M. Dynamic Reliability Management for FPGA-Based
Systems. International Journal of Reconfigurable Computing. 2020:1-19.
doi:10.1155/2020/2808710
apa: Anwer, J., Meisner, S., & Platzner, M. (2020). Dynamic Reliability Management
for FPGA-Based Systems. International Journal of Reconfigurable Computing,
1–19. https://doi.org/10.1155/2020/2808710
bibtex: '@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management
for FPGA-Based Systems}, DOI={10.1155/2020/2808710},
journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb
and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }'
chicago: Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management for FPGA-Based Systems.” International Journal of Reconfigurable
Computing, 2020, 1–19. https://doi.org/10.1155/2020/2808710.
ieee: J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for
FPGA-Based Systems,” International Journal of Reconfigurable Computing,
pp. 1–19, 2020.
mla: Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.”
International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710.
short: J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable
Computing (2020) 1–19.
date_created: 2020-06-15T11:25:07Z
date_updated: 2022-01-06T06:53:04Z
department:
- _id: '78'
doi: 10.1155/2020/2808710
language:
- iso: eng
page: 1-19
publication: International Journal of Reconfigurable Computing
publication_identifier:
issn:
- 1687-7195
- 1687-7209
publication_status: published
status: public
title: Dynamic Reliability Management for FPGA-Based Systems
type: journal_article
user_id: '398'
year: '2020'
...
---
_id: '15836'
author:
- first_name: K.
full_name: Bellman, K.
last_name: Bellman
- first_name: N.
full_name: Dutt, N.
last_name: Dutt
- first_name: L.
full_name: Esterle, L.
last_name: Esterle
- first_name: A.
full_name: Herkersdorf, A.
last_name: Herkersdorf
- first_name: A.
full_name: Jantsch, A.
last_name: Jantsch
- first_name: C.
full_name: Landauer, C.
last_name: Landauer
- first_name: P.
full_name: R. Lewis, P.
last_name: R. Lewis
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: N.
full_name: TaheriNejad, N.
last_name: TaheriNejad
- first_name: K.
full_name: Tammemäe, K.
last_name: Tammemäe
citation:
ama: Bellman K, Dutt N, Esterle L, et al. Self-aware Cyber-Physical Systems. ACM
Transactions on Cyber-Physical Systems. 2020;Accepted for Publication:1-24.
apa: Bellman, K., Dutt, N., Esterle, L., Herkersdorf, A., Jantsch, A., Landauer,
C., … Tammemäe, K. (2020). Self-aware Cyber-Physical Systems. ACM Transactions
on Cyber-Physical Systems, Accepted for Publication, 1–24.
bibtex: '@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020,
title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication},
journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and
Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C.
and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020},
pages={1–24} }'
chicago: 'Bellman, K., N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, Marco Platzner, N. TaheriNejad, and K. Tammemäe. “Self-Aware Cyber-Physical
Systems.” ACM Transactions on Cyber-Physical Systems Accepted for Publication
(2020): 1–24.'
ieee: K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
mla: Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions
on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.
short: K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer,
P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical
Systems Accepted for Publication (2020) 1–24.
date_created: 2020-02-06T15:05:45Z
date_updated: 2022-01-06T06:52:37Z
department:
- _id: '78'
language:
- iso: eng
page: 1-24
publication: ACM Transactions on Cyber-Physical Systems
status: public
title: Self-aware Cyber-Physical Systems
type: journal_article
user_id: '398'
volume: Accepted for Publication
year: '2020'
...
---
_id: '16213'
abstract:
- lang: eng
text: 'Automated synthesis of approximate circuits via functional approximations
is of prominent importance to provide efficiency in energy, runtime, and chip
area required to execute an application. Approximate circuits are usually obtained
either through analytical approximation methods leveraging approximate transformations
such as bit-width scaling or via iterative search-based optimization methods when
a library of approximate components, e.g., approximate adders and multipliers,
is available. For the latter, exploring the extremely large design space is challenging
in terms of both computations and quality of results. While the combination of
both methods can create more room for further approximations, the \textit{Design
Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such
a hybrid synthesis methodology that applies a low-cost analytical method followed
by parallel stochastic search-based optimization. We address the DSE challenge
through efficient pruning of the design space and skipping unnecessary expensive
testing and/or verification steps. The experimental results reveal up to 10.57x
area savings in comparison with both purely analytical or search-based approaches. '
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology
for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid
Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China:
ACM. https://doi.org/10.1145/3386263.3406952'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid
Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952},
booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan
and Platzner, Marco}, year={2020}, pages={421–426} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid
Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology
for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
mla: Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”
Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020,
ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.'
conference:
location: Beijing, China
name: ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
date_created: 2020-03-02T15:49:38Z
date_updated: 2022-01-06T06:52:45Z
department:
- _id: '78'
doi: 10.1145/3386263.3406952
language:
- iso: eng
page: 421-426
publication: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
publication_status: published
publisher: ACM
status: public
title: A Hybrid Synthesis Methodology for Approximate Circuits
type: conference
user_id: '64665'
year: '2020'
...
---
_id: '16363'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Hansmeier T, Kaufmann P, Platzner M. Enabling XCSF to Cope with Dynamic Environments
via an Adaptive Error Threshold. In: GECCO ’20: Proceedings of the Genetic
and Evolutionary Computation Conference Companion. New York, NY, United States:
Association for Computing Machinery (ACM); 2020:125-126. doi:10.1145/3377929.3389968'
apa: 'Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126).
New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968'
bibtex: '@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United
States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive
Error Threshold}, DOI={10.1145/3377929.3389968},
booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion}, publisher={Association for Computing Machinery (ACM)},
author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126}
}'
chicago: 'Hansmeier, Tim, Paul Kaufmann, and Marco Platzner. “Enabling XCSF to Cope
with Dynamic Environments via an Adaptive Error Threshold.” In GECCO ’20: Proceedings
of the Genetic and Evolutionary Computation Conference Companion, 125–26.
New York, NY, United States: Association for Computing Machinery (ACM), 2020.
https://doi.org/10.1145/3377929.3389968.'
ieee: 'T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic
Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of
the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico,
2020, pp. 125–126.'
mla: 'Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via
an Adaptive Error Threshold.” GECCO ’20: Proceedings of the Genetic and Evolutionary
Computation Conference Companion, Association for Computing Machinery (ACM),
2020, pp. 125–26, doi:10.1145/3377929.3389968.'
short: 'T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the
Genetic and Evolutionary Computation Conference Companion, Association for Computing
Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.'
conference:
end_date: 2020-07-12
location: Cancún, Mexico
name: The Genetic and Evolutionary Computation Conference (GECCO 2020)
start_date: 2020-07-08
date_created: 2020-04-02T10:07:10Z
date_updated: 2022-01-06T06:52:49Z
department:
- _id: '78'
doi: 10.1145/3377929.3389968
language:
- iso: eng
page: 125-126
place: New York, NY, United States
project:
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
publication: 'GECCO ''20: Proceedings of the Genetic and Evolutionary Computation
Conference Companion'
publication_identifier:
isbn:
- 978-1-4503-7127-8
publication_status: published
publisher: Association for Computing Machinery (ACM)
status: public
title: Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold
type: conference
user_id: '477'
year: '2020'
...
---
_id: '20838'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020. doi:10.1109/ipdpsw50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/ipdpsw50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020} }'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 2020. https://doi.org/10.1109/ipdpsw50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020.'
date_created: 2020-12-23T09:07:11Z
date_updated: 2023-01-03T22:07:12Z
department:
- _id: '78'
doi: 10.1109/ipdpsw50202.2020.00012
language:
- iso: eng
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
isbn:
- '9781728174457'
publication_status: published
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '35152'
author:
- first_name: Achim
full_name: Lösch, Achim
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. MigHEFT: DAG-based Scheduling of Migratable Tasks on
Heterogeneous Compute Nodes. In: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW). ; 2020:6-16. doi:10.1109/IPDPSW50202.2020.00012'
apa: 'Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 6–16. https://doi.org/10.1109/IPDPSW50202.2020.00012'
bibtex: '@inproceedings{Lösch_Platzner_2020, title={MigHEFT: DAG-based Scheduling
of Migratable Tasks on Heterogeneous Compute Nodes}, DOI={10.1109/IPDPSW50202.2020.00012},
booktitle={2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, author={Lösch, Achim and Platzner, Marco}, year={2020}, pages={6–16}
}'
chicago: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” In 2020 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 6–16, 2020. https://doi.org/10.1109/IPDPSW50202.2020.00012.'
ieee: 'A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks
on Heterogeneous Compute Nodes,” in 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi: 10.1109/IPDPSW50202.2020.00012.'
mla: 'Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable
Tasks on Heterogeneous Compute Nodes.” 2020 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi:10.1109/IPDPSW50202.2020.00012.'
short: 'A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16.'
date_created: 2023-01-03T22:05:08Z
date_updated: 2024-04-30T09:14:00Z
department:
- _id: '78'
doi: 10.1109/IPDPSW50202.2020.00012
page: 6-16
publication: 2020 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
status: public
title: 'MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute
Nodes'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
text: "Modern machine learning (ML) techniques continue to move into the embedded
system space because traditional centralized compute resources do not suit certain
application domains, for example in mobile or real-time environments. Google’s
TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
and makes ML inference accessible on resource-constrained devices. While it offers
the possibility to partially delegate computation to hardware accelerators, there
is no such “delegate” available to utilize the promising characteristics of reconfigurable
hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
a modular delegate framework, which allows accelerators within the programmable
logic to take over the execution of neural network layers. To facilitate the necessary
hardware/software codesign, the FPGA delegate is based on the operating system
for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
enables the instantiation of model-tailored accelerator architectures. In the
hardware back-end, a streaming-based prototype accelerator for the MobileNet model
family showcases the working order of the platform, but falls short of the desired
performance. Thus, it indicates the need for further exploration of alternative
accelerator designs, which the delegate could automatically synthesize to meet
a model’s demands."
author:
- first_name: Felix P.
full_name: Jentzsch, Felix P.
last_name: Jentzsch
citation:
ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture.; 2020.
apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture.
bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
}'
chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture, 2020.
ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture. 2020.
mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture. 2020.
short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '3585'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
volume={99}, DOI={10.1016/j.microrel.2019.04.003},
journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019):
277–90. https://doi.org/10.1016/j.microrel.2019.04.003.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Microelectronics Reliability, vol. 99, pp. 277–290, 2019.'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Microelectronics Reliability,
vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Microelectronics Reliability 99 (2019) 277–290.
date_created: 2018-07-20T14:08:49Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
doi: 10.1016/j.microrel.2019.04.003
intvolume: ' 99'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: 277-290
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Microelectronics Reliability
publication_identifier:
issn:
- 0026-2714
publication_status: published
publisher: Elsevier
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: journal_article
user_id: '49051'
volume: 99
year: '2019'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '10577'
abstract:
- lang: eng
text: "State-of-the-art frameworks for generating approximate circuits automatically
explore the search space in an iterative process - often greedily. Synthesis and
verification processes are invoked in each iteration to evaluate the found solutions
and to guide the search algorithm. As a result, a large number of approximate
circuits is subjected to analysis - leading to long runtimes - but only a few
approximate circuits might form an acceptable solution.\r\n\r\nIn this paper,
we present our Jump Search (JS) method which seeks to reduce the runtime of an
approximation process by reducing the number of expensive synthesis and verification
steps. To reduce the runtime, JS computes impact factors for each approximation
candidate in the circuit to create a selection of approximate circuits without
invoking synthesis or verification processes. We denote the selection as path
from which JS determines the final solution. In our experimental results, JS achieved
speed-ups of up to 57x while area savings remain comparable to the reference search
method, Simulated Annealing."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY,
USA: ACM; 2019. doi:10.1145/3299874.3317998'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19.
New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998'
bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New
York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits}, DOI={10.1145/3299874.3317998},
booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi,
Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner,
VA, USA, 2019.'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium
on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.'
short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY,
USA, 2019.'
conference:
end_date: 2019-05-11
location: Tysons Corner, VA, USA
name: ACM Great Lakes Symposium on VLSI (GLSVLSI)
start_date: 2019-05-09
date_created: 2019-07-08T15:13:10Z
date_updated: 2022-01-06T06:50:45Z
department:
- _id: '78'
doi: 10.1145/3299874.3317998
keyword:
- Approximate computing
- design automation
- parameter selection
- circuit synthesis
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19
publication_identifier:
isbn:
- '9781450362528'
publication_status: published
publisher: ACM
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: conference
user_id: '49051'
year: '2019'
...
---
_id: '11950'
abstract:
- lang: eng
text: Advances in electromyographic (EMG) sensor technology and machine learning
algorithms have led to an increased research effort into high density EMG-based
pattern recognition methods for prosthesis control. With the goal set on an autonomous
multi-movement prosthesis capable of performing training and classification of
an amputee’s EMG signals, the focus of this paper lies in the acceleration of
the embedded signal processing chain. We present two Xilinx Zynq-based architectures
for accelerating two inherently different high density EMG-based control algorithms.
The first hardware accelerated design achieves speed-ups of up to 4.8 over the
software-only solution, allowing for a processing delay lower than the sample
period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only
version and operates at a still satisfactory low processing delay of up to 15
ms while providing a higher reliability and robustness against electrode shift
and noisy channels.
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Florian
full_name: Kraus, Florian
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based
acceleration of robust high density myoelectric signal processing. Journal
of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004
apa: Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., &
Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric
signal processing. Journal of Parallel and Distributed Computing, 123,
77–89. https://doi.org/10.1016/j.jpdc.2018.07.004
bibtex: '@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based
acceleration of robust high density myoelectric signal processing}, volume={123},
DOI={10.1016/j.jpdc.2018.07.004},
journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier},
author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen,
Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89}
}'
chicago: 'Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen,
Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing
123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.'
ieee: A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner,
“Zynq-based acceleration of robust high density myoelectric signal processing,”
Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
mla: Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing,
vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.
short: A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner,
Journal of Parallel and Distributed Computing 123 (2019) 77–89.
date_created: 2019-07-12T13:13:55Z
date_updated: 2022-01-06T06:51:13Z
department:
- _id: '78'
doi: 10.1016/j.jpdc.2018.07.004
intvolume: ' 123'
keyword:
- High density electromyography
- FPGA acceleration
- Medical signal processing
- Pattern recognition
- Prosthetics
language:
- iso: eng
page: 77-89
publication: Journal of Parallel and Distributed Computing
publication_identifier:
issn:
- 0743-7315
publication_status: published
publisher: Elsevier
status: public
title: Zynq-based acceleration of robust high density myoelectric signal processing
type: journal_article
user_id: '398'
volume: 123
year: '2019'
...
---
_id: '12967'
abstract:
- lang: eng
text: Modern Boolean satisfiability solvers can emit proofs of unsatisfiability.
There is substantial interest in being able to verify such proofs and also in
using them for further computations. In this paper, we present an FPGA accelerator
for checking resolution proofs, a popular proof format. Our accelerator exploits
parallelism at the low level by implementing the basic resolution step in hardware,
and at the high level by instantiating a number of parallel modules for proof
checking. Since proof checking involves highly irregular memory accesses, we employ
Hybrid Memory Cube technology for accelerator memory. The results show that while
the accelerator is scalable and achieves speedups for all benchmark proofs, performance
improvements are currently limited by the overhead of transitioning the proof
into the accelerator memory.
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Md Jubaer Hossain
full_name: Pantho, Md Jubaer Hossain
last_name: Pantho
- first_name: David
full_name: Andrews, David
last_name: Andrews
citation:
ama: Hansmeier T, Platzner M, Pantho MJH, Andrews D. An Accelerator for Resolution
Proof Checking based on FPGA and Hybrid Memory Cube Technology. Journal of
Signal Processing Systems. 2019;91(11):1259-1272. doi:10.1007/s11265-018-1435-y
apa: Hansmeier, T., Platzner, M., Pantho, M. J. H., & Andrews, D. (2019). An
Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube
Technology. Journal of Signal Processing Systems, 91(11), 1259–1272.
https://doi.org/10.1007/s11265-018-1435-y
bibtex: '@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology},
volume={91}, DOI={10.1007/s11265-018-1435-y},
number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier,
Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019},
pages={1259–1272} }'
chicago: 'Hansmeier, Tim, Marco Platzner, Md Jubaer Hossain Pantho, and David Andrews.
“An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory
Cube Technology.” Journal of Signal Processing Systems 91, no. 11 (2019):
1259–72. https://doi.org/10.1007/s11265-018-1435-y.'
ieee: T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator
for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,”
Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
mla: Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based
on FPGA and Hybrid Memory Cube Technology.” Journal of Signal Processing Systems,
vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.
short: T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing
Systems 91 (2019) 1259–1272.
date_created: 2019-08-26T13:41:57Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1007/s11265-018-1435-y
intvolume: ' 91'
issue: '11'
language:
- iso: eng
page: 1259 - 1272
publication: Journal of Signal Processing Systems
publication_identifier:
issn:
- 1939-8018
- 1939-8115
publication_status: published
status: public
title: An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory
Cube Technology
type: journal_article
user_id: '49992'
volume: 91
year: '2019'
...
---
_id: '15422'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Optimization of Application-specific L1 Cache
Translation Functions of the LEON3 Processor. In: World Congress on Nature
and Biologically Inspired Computing (NaBIC). Advances in Nature and Biologically
Inspired Computing. Springer; 2019.'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor. In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Springer.
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2019, series={Advances in Nature and
Biologically Inspired Computing}, title={Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor}, booktitle={World Congress
on Nature and Biologically Inspired Computing (NaBIC)}, publisher={Springer},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2019}, collection={Advances
in Nature and Biologically Inspired Computing} }'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “Optimization of Application-Specific
L1 Cache Translation Functions of the LEON3 Processor.” In World Congress on
Nature and Biologically Inspired Computing (NaBIC). Advances in Nature and
Biologically Inspired Computing. Springer, 2019.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific
L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on
Nature and Biologically Inspired Computing (NaBIC), 2019.
mla: Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation
Functions of the LEON3 Processor.” World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically
Inspired Computing (NaBIC), Springer, 2019.'
date_created: 2019-12-30T13:55:49Z
date_updated: 2022-01-06T06:52:25Z
department:
- _id: '78'
language:
- iso: eng
publication: World Congress on Nature and Biologically Inspired Computing (NaBIC)
publisher: Springer
series_title: Advances in Nature and Biologically Inspired Computing
status: public
title: Optimization of Application-specific L1 Cache Translation Functions of the
LEON3 Processor
type: conference
user_id: '398'
year: '2019'
...
---
_id: '15883'
author:
- first_name: Shankar
full_name: Kumar Jeyakumar, Shankar
last_name: Kumar Jeyakumar
citation:
ama: Kumar Jeyakumar S. Incremental Learning with Support Vector Machine on Embedded
Platforms.; 2019.
apa: Kumar Jeyakumar, S. (2019). Incremental learning with Support Vector Machine
on embedded platforms.
bibtex: '@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector
Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019}
}'
chicago: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms, 2019.
ieee: S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on
embedded platforms. 2019.
mla: Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine
on Embedded Platforms. 2019.
short: S. Kumar Jeyakumar, Incremental Learning with Support Vector Machine on Embedded
Platforms, 2019.
date_created: 2020-02-11T16:43:38Z
date_updated: 2022-01-06T06:52:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
title: Incremental learning with Support Vector Machine on embedded platforms
type: mastersthesis
user_id: '61186'
year: '2019'
...
---
_id: '15920'
abstract:
- lang: eng
text: "Secure hardware design is the most important aspect to be considered in addition
to functional correctness. Achieving hardware security in today’s globalized Integrated
Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
It provides an ap- proach to verify that the systems adhere to security properties
either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
Hardware(PCH) is an approach to verify a functional design prior to using it in
hardware. It is a two-party verification approach, where the target party, the
consumer requests new functionalities with pre-defined properties to the producer.
In response, the producer designs the IP (Intellectual Property) cores with the
requested functionalities that adhere to the consumer-defined properties. The
producer provides the IP cores and a proof certificate combined into a proof-carrying
bitstream to the consumer to verify it. If the verification is successful, the
consumer can use the IP cores in his hardware. In essence, the consumer can only
run verified IP cores. Correctly applied, PCH techniques can help consumers to
defend against many unintentional modifications and malicious alterations of the
modules they receive. There are numerous published examples of how to use PCH
to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
with functional equivalence checking for combinational or sequential circuits.
For non-functional properties, since opening new covert channels to leak secret
information from secure circuits is a viable attack vector for hardware trojans,
i.e., intentionally added malicious circuitry, IFT technique is employed to make
sure that secret/untrusted information never reaches any unclassified/trusted
outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
level enabling consumers to validate the trustworthiness of a module’s information
flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
full_name: Keerthipati, Monica
last_name: Keerthipati
citation:
ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking. Universität Paderborn; 2019.
apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn.
bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
Monica}, year={2019} }'
chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for
Information Flow Tracking. Universität Paderborn, 2019.
mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
full_name: Sabu, Nithin S.
last_name: Sabu
citation:
ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets.
Paderborn University; 2019.
apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University.
bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
}'
chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University, 2019.
ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Stefan
full_name: Böttcher, Stefan
last_name: Böttcher
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '15946'
author:
- first_name: Jinay
full_name: Mehta, Jinay
last_name: Mehta
citation:
ama: "Mehta J. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip.; 2019."
apa: "Mehta, J. (2019). Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip."
bibtex: "@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
ReconOS/freeRTOS on a Recon\U0010FC03gurable System-on-Chip}, author={Mehta, Jinay},
year={2019} }"
chicago: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
ieee: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
mla: "Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip. 2019."
short: "J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
on a Recon\U0010FC03gurable System-on-Chip, 2019."
date_created: 2020-02-20T14:47:12Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
title: "Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon\U0010FC03gurable
System-on-Chip"
type: mastersthesis
user_id: '398'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.
apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn.
bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
Paderborn}, author={Hansmeier, Tim}, year={2019} }'
chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '31067'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Platzner M, Kermia O, Khouas A. An Approach for Mapping Periodic
Real-Time Tasks to Reconfigurable Hardware. In: 2019 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2019. doi:10.1109/ipdpsw.2019.00027'
apa: Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE
International Parallel and Distributed Processing Symposium Workshops (IPDPSW).
https://doi.org/10.1109/ipdpsw.2019.00027
bibtex: '@inproceedings{Guettatfi_Platzner_Kermia_Khouas_2019, title={An Approach
for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}, DOI={10.1109/ipdpsw.2019.00027},
booktitle={2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Guettatfi, Zakarya and Platzner,
Marco and Kermia, Omar and Khouas, Abdelhakim}, year={2019} }'
chicago: Guettatfi, Zakarya, Marco Platzner, Omar Kermia, and Abdelhakim Khouas.
“An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”
In 2019 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW). IEEE, 2019. https://doi.org/10.1109/ipdpsw.2019.00027.
ieee: 'Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping
Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.'
mla: Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks
to Reconfigurable Hardware.” 2019 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.
short: 'Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.'
date_created: 2022-05-05T07:42:26Z
date_updated: 2022-05-05T07:43:29Z
department:
- _id: '78'
doi: 10.1109/ipdpsw.2019.00027
language:
- iso: eng
publication: 2019 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_status: published
publisher: IEEE
status: public
title: An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
type: conference
user_id: '398'
year: '2019'
...