---
_id: '13048'
abstract:
- lang: eng
  text: Marginal hardware introduces severe reliability threats throughout the life
    cycle of a system. Although marginalities may not affect the functionality of
    a circuit immediately after manufacturing, they can degrade into hard failures
    and must be screened out during manufacturing test to prevent early life failures.
    Furthermore, their evolution in the field must be proactively monitored by periodic
    tests before actual failures occur. In recent years small delay faults have gained
    increasing attention as possible indicators of marginal hardware. However, small
    delay faults on short paths may be undetectable even with advanced timing aware
    ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but
    so far FAST has mainly been restricted to manufacturing test.
author:
- first_name: Matthias
  full_name: Kampmann, Matthias
  id: '10935'
  last_name: Kampmann
- first_name: Michael
  full_name: A. Kochte, Michael
  last_name: A. Kochte
- first_name: Chang
  full_name: Liu, Chang
  last_name: Liu
- first_name: Eric
  full_name: Schneider, Eric
  last_name: Schneider
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J.
    Built-in Test for Hidden Delay Faults. <i>IEEE Transactions on Computer-Aided
    Design of Integrated Circuits and Systems (TCAD)</i>. 2019;38(10):1956-1968.
  apa: Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &#38;
    Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. <i>IEEE Transactions
    on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, <i>38</i>(10),
    1956–1968.
  bibtex: '@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in
    Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions
    on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE},
    author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider,
    Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968}
    }'
  chicago: 'Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille
    Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.”
    <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    (TCAD)</i> 38, no. 10 (2019): 1956–68.'
  ieee: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J.
    Wunderlich, “Built-in Test for Hidden Delay Faults,” <i>IEEE Transactions on Computer-Aided
    Design of Integrated Circuits and Systems (TCAD)</i>, vol. 38, no. 10, pp. 1956–1968,
    2019.
  mla: Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” <i>IEEE
    Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>,
    vol. 38, no. 10, IEEE, 2019, pp. 1956–68.
  short: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    (TCAD) 38 (2019) 1956–1968.
date_created: 2019-08-28T11:44:25Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: '        38'
issue: '10'
language:
- iso: eng
page: 1956 - 1968
publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and
  Systems (TCAD)
publication_identifier:
  eissn:
  - 1937-4151
publication_status: published
publisher: IEEE
status: public
title: Built-in Test for Hidden Delay Faults
type: journal_article
user_id: '209'
volume: 38
year: '2019'
...