[{"title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"place":"New York, NY, USA","doi":"10.1145/1950413.1950448","citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>."},"user_id":"15278","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","quality_controlled":"1","date_created":"2018-04-03T15:08:13Z","publisher":"ACM","type":"conference","year":"2011","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"language":[{"iso":"eng"}],"status":"public","_id":"2200","page":"177-180","date_updated":"2023-09-26T13:45:04Z"}]