@inproceedings{37046,
  abstract     = {{In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU.}},
  author       = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Application Programming Interface     User Mode     Kernel Space     System Level Design     Mixed Level}},
  publisher    = {{Springer Verlag}},
  title        = {{{A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}}},
  doi          = {{10.1007/978-3-642-15234-4_15}},
  year         = {{2010}},
}

@inproceedings{37044,
  abstract     = {{In this paper we present new concepts to resolve ECU (Electronic Control Unit) failures in FlexRay networks. Our approach extends the FlexRay bus schedule by redundant slots with modifications in the communication and slot assignment. We introduce additional backup nodes to replace faulty nodes. To reduce the required memory resources of the backup nodes, we distribute redundant tasks over different nodes and propose the migration of tasks to the backup node at runtime. We investigate different solutions to migrate the redundant tasks to the backup node by time-triggered and event-triggered transmissions.}},
  author       = {{Klobedanz, Kay and Defo, Gilles B. and Zabel, Henning and Müller, Wolfgang and Zhi, Yuan}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Faulty Node     Static Segment     Slot Assignment     Task Migration     Communication Controller}},
  publisher    = {{Springer Verlag}},
  title        = {{{Task Migration for Fault-Tolerant FlexRay Networks}}},
  doi          = {{10.1007/978-3-642-15234-4_7}},
  year         = {{2010}},
}

@inproceedings{37048,
  abstract     = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}},
  author       = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Natural Language     UML     SystemVerilog     Testbenches}},
  publisher    = {{Springer Verlag}},
  title        = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}},
  doi          = {{10.1007/978-3-642-15234-4_9}},
  year         = {{2010}},
}

@inproceedings{37047,
  abstract     = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}},
  author       = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Natural Language     UML     SystemVerilog     Testbenches}},
  publisher    = {{Springer Verlag}},
  title        = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}},
  doi          = {{10.1007/978-3-642-15234-4_9}},
  year         = {{2010}},
}