---
_id: '32125'
abstract:
- lang: eng
  text: 'Fault coverage analysis and fault simulation are well-established methods
    for the qualification of test vectors in hardware design. However, their role
    in virtual prototyping and the correlation to later steps in the design process
    need further investigation. We introduce a metric for RISC-V instruction and register
    coverage for binary software. The metric measures if RISC-V instruction types
    are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied
    by the means of a virtual prototype which is based on an abstract instruction
    and register model with direct correspondence to their bit level representation.
    In this context, we analyzed three different openly available test suites: the
    RISC-V architectural testing framework, the RISC-V unit tests, and programs which
    are automatically generated by the RISC-V Torture test generator. We discuss their
    tradeoffs and show that by combining them to a unified test suite we can arrive
    at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage.'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage
    Analysis for Different RISC-V ISA Modules. In: <i>MBMV 2021 - Methods and Description
    Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.
    VDE; 2021.'
  apa: Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and
    Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>MBMV 2021 -
    Methods and Description Languages for Modelling and Verification of Circuits and
    Systems; GMM/ITG/GI-Workshop</i>.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE},
    title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules},
    booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification
    of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt,
    Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021}
    }'
  chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
    “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.”
    In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification
    of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.'
  ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction
    Coverage Analysis for Different RISC-V ISA Modules,” 2021.
  mla: Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different
    RISC-V ISA Modules.” <i>MBMV 2021 - Methods and Description Languages for Modelling
    and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.
  short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods
    and Description Languages for Modelling and Verification of Circuits and Systems;
    GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.'
conference:
  end_date: 2021-03-19
  start_date: 2021-03-18
date_created: 2022-06-23T11:52:50Z
date_updated: 2022-06-23T11:54:16Z
department:
- _id: '58'
language:
- iso: eng
place: Munich, DE
publication: MBMV 2021 - Methods and Description Languages for Modelling and Verification
  of Circuits and Systems; GMM/ITG/GI-Workshop
publication_identifier:
  isbn:
  - 978-3-8007-5500-4
publication_status: published
publisher: VDE
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/9399723
status: public
title: Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
type: conference
user_id: '5603'
year: '2021'
...