---
_id: '2404'
abstract:
- lang: eng
  text: ' In this thesis, we propose to use a reconfigurable processor as main computation
    element in embedded systems for applications from the multi-media and communications
    domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable
    Processing Unit (RPU). Many of our target applications require real-time signal-processing
    of data streams and expose a high computational demand. The key challenge in designing
    embedded systems for these applications is to find an implementation that satisfies
    the performance goals and is adaptable to new applications, while the system cost
    is minimized. Implementations that solely use an embedded CPU are likely to miss
    the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors
    can be used for some high-volume products with fixed functions, but fall short
    for systems with varying applications. We argue that a reconfigurable processor
    with a coarse-grained, dynamically reconfigurable array of modest size provides
    an attractive implementation platform for our application domain. The computational
    intensive application kernels are executed on the RPU, while the remaining parts
    of the application are executed on the CPU. Reconfigurable hardware allows for
    implementing application specific coprocessors with a high performance, while
    the function of the coprocessor can still be adapted due to the programmability.
    So far, reconfigurable technology is used in embedded systems primarily with static
    configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing
    fixed-function coprocessors. Changing the configuration at runtime enables a number
    of interesting application modes, e.g., on-demand loading of coprocessors and
    time-multiplexed execution of coprocessors, which is commonly denoted as hardware
    virtualization. While the use of static configurations is well understood and
    supported by design-tools, the role of dynamic reconfiguration is not well investigated
    yet. Current application specification methods and design-tools do not provide
    an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of
    our approach is to reduce system cost by keeping the size of the reconfigurable
    array small and to use hardware virtualization techniques to compensate for the
    limited hardware resources. The main contribution of this thesis is the codesign
    of a reconfigurable processor architecture named ZIPPY, the corresponding hardware
    and software implementation tools, and an application specification model which
    explicitly considers hardware virtualization. The ZIPPY architecture is widely
    parametrized and allows for specifying a whole family of processor architectures.
    The implementation tools are also parametrized and can target any architectural
    variant. We evaluate the performance of the architecture with a system-level,
    cycle-accurate cosimulation framework. This framework enables us to perform design-space
    exploration for a variety of reconfigurable processor architectures. With two
    case studies, we demonstrate, that hardware virtualization on the Zippy architecture
    is feasible and enables us to trade-off performance for area in embedded systems.
    Finally, we present a novel method for optimal temporal partitioning of sequential
    circuits, which is an important form of hardware virtualization. The method based
    on Slowdown and Retiming allows us to decompose any sequential circuit into a
    number of smaller, communicating subcircuits that can be executed on a dynamically
    reconfigurable architecture. '
author:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Plessl C. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>.
    Aachen, Germany: Shaker Verlag; 2006. doi:<a href="https://doi.org/10.2370/9783832255619">10.2370/9783832255619</a>'
  apa: 'Plessl, C. (2006). <i>Hardware virtualization on a coarse-grained reconfigurable
    processor</i>. Aachen, Germany: Shaker Verlag. <a href="https://doi.org/10.2370/9783832255619">https://doi.org/10.2370/9783832255619</a>'
  bibtex: '@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik},
    title={Hardware virtualization on a coarse-grained reconfigurable processor},
    DOI={<a href="https://doi.org/10.2370/9783832255619">10.2370/9783832255619</a>},
    publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische
    Informatik} }'
  chicago: 'Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable
    Processor</i>. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. <a
    href="https://doi.org/10.2370/9783832255619">https://doi.org/10.2370/9783832255619</a>.'
  ieee: 'C. Plessl, <i>Hardware virtualization on a coarse-grained reconfigurable
    processor</i>. Aachen, Germany: Shaker Verlag, 2006.'
  mla: Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable
    Processor</i>. Shaker Verlag, 2006, doi:<a href="https://doi.org/10.2370/9783832255619">10.2370/9783832255619</a>.
  short: C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor,
    Shaker Verlag, Aachen, Germany, 2006.
date_created: 2018-04-17T13:46:27Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '518'
doi: 10.2370/9783832255619
keyword:
- Zippy
place: Aachen, Germany
publication_identifier:
  isbn:
  - 978-3-8322-5561-3
publisher: Shaker Verlag
series_title: Technische Informatik
status: public
title: Hardware virtualization on a coarse-grained reconfigurable processor
type: dissertation
user_id: '24135'
year: '2006'
...