---
_id: '16427'
abstract:
- lang: eng
  text: "Transactional Memory (TM) has been considered as a promising alternative
    to existing synchronization operations, which are often the largest stumbling
    block to unleashing parallelism of applications. Efficient implementations of
    TM, however, are challenging due to the tension between lowering performance overhead
    and avoiding unnecessary aborts.\r\n\r\nIn this paper, we present Reachability-based
    Optimistic Concurrency Control for Transactional Memory (ROCoCoTM), a novel scheme
    which offloads concurrency control (CC) algorithms, the central building blocks
    of TM systems, to reconfigurable hardware. To reduce the abort rate, an innovative
    formalization of mainstream CC algorithms is developed to reveal a common restriction
    that leads to unnecessary aborts. This restriction is resolved by the ROCoCo algorithm
    with a centralized validation phase, which can be efficiently pipelined in hardware.
    Thanks to a high-performance offloading engine implemented in reconfigurable hardware,
    ROCoCo algorithm results in decreased abort rates and reduced performance overhead.
    The whole system is implemented on Intel's HARP2 platform and evaluated with the
    STAMP benchmark suite. Experiments show 1.55x and 8.05x geomean speedup over TinySTM
    and an HTM based on Intel TSX, respectively. Given the fast-growing deployment
    of commodity CPU-FPGA platforms, ROCoCoTM paves the way for software programmers
    to exploit heterogeneous computing resources with a high-level transactional abstraction
    to effectively extract the parallelism in modern applications."
author:
- first_name: Zhaoshi
  full_name: Li, Zhaoshi
  last_name: Li
- first_name: Leibo
  full_name: Liu, Leibo
  last_name: Liu
- first_name: Yangdong
  full_name: Deng, Yangdong
  last_name: Deng
- first_name: Jiawei
  full_name: Wang, Jiawei
  last_name: Wang
- first_name: Zhiwei
  full_name: Liu, Zhiwei
  last_name: Liu
- first_name: Shouyi
  full_name: Yin, Shouyi
  last_name: Yin
- first_name: Shaojun
  full_name: Wei, Shaojun
  last_name: Wei
citation:
  ama: 'Li Z, Liu L, Deng Y, et al. FPGA-Accelerated Optimistic Concurrency Control
    for Transactional Memory. In: <i>Proceedings of the 52nd Annual IEEE/ACM International
    Symposium on Microarchitecture</i>. ; 2019. doi:<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>'
  apa: Li, Z., Liu, L., Deng, Y., Wang, J., Liu, Z., Yin, S., &#38; Wei, S. (2019).
    FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. In <i>Proceedings
    of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>.
    <a href="https://doi.org/10.1145/3352460.3358270">https://doi.org/10.1145/3352460.3358270</a>
  bibtex: '@inproceedings{Li_Liu_Deng_Wang_Liu_Yin_Wei_2019, title={FPGA-Accelerated
    Optimistic Concurrency Control for Transactional Memory}, DOI={<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>},
    booktitle={Proceedings of the 52nd Annual IEEE/ACM International Symposium on
    Microarchitecture}, author={Li, Zhaoshi and Liu, Leibo and Deng, Yangdong and
    Wang, Jiawei and Liu, Zhiwei and Yin, Shouyi and Wei, Shaojun}, year={2019} }'
  chicago: Li, Zhaoshi, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi
    Yin, and Shaojun Wei. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
    Memory.” In <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium
    on Microarchitecture</i>, 2019. <a href="https://doi.org/10.1145/3352460.3358270">https://doi.org/10.1145/3352460.3358270</a>.
  ieee: Z. Li <i>et al.</i>, “FPGA-Accelerated Optimistic Concurrency Control for
    Transactional Memory,” in <i>Proceedings of the 52nd Annual IEEE/ACM International
    Symposium on Microarchitecture</i>, 2019.
  mla: Li, Zhaoshi, et al. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
    Memory.” <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on
    Microarchitecture</i>, 2019, doi:<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>.
  short: 'Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei, in: Proceedings
    of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019.'
date_created: 2020-04-06T12:49:40Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1145/3352460.3358270
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
publication_identifier:
  isbn:
  - '9781450369381'
publication_status: published
status: public
title: FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
type: conference
user_id: '61189'
year: '2019'
...