---
_id: '56606'
abstract:
- lang: eng
  text: <jats:title>Abstract</jats:title><jats:p>Most FPGA boards in the HPC domain
    are well-suited for parallel scaling because of the direct integration of versatile
    and high-throughput network ports. However, the utilization of their network capabilities is
    often challenging and error-prone because the whole network stack and communication
    patterns have to be implemented and managed on the FPGAs. Also, this approach
    conceptually involves a trade-off between the performance potential of improved
    communication and the impact of resource consumption for communication infrastructure,
    since the utilized resources on the FPGAs could otherwise be used for computations.
    In this work, we investigate this trade-off, firstly, by using synthetic benchmarks
    to evaluate the different configuration options of the communication framework
    ACCL and their impact on communication latency and throughput. Finally, we use
    our findings to implement a shallow water simulation whose scalability heavily
    depends on low-latency communication. With a suitable configuration of ACCL, good
    scaling behavior can be shown to all 48 FPGAs installed in the system. Overall,
    the results show that the availability of inter-FPGA communication frameworks
    as well as the configurability of framework and network stack are crucial to achieve
    the best application performance with low latency communication.</jats:p>
author:
- first_name: Marius
  full_name: Meyer, Marius
  last_name: Meyer
- first_name: Tobias
  full_name: Kenter, Tobias
  last_name: Kenter
- first_name: Lucian
  full_name: Petrica, Lucian
  last_name: Petrica
- first_name: Kenneth
  full_name: O’Brien, Kenneth
  last_name: O’Brien
- first_name: Michaela
  full_name: Blott, Michaela
  last_name: Blott
- first_name: Christian
  full_name: Plessl, Christian
  last_name: Plessl
citation:
  ama: 'Meyer M, Kenter T, Petrica L, O’Brien K, Blott M, Plessl C. Optimizing Communication
    for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. In: <i>Lecture
    Notes in Computer Science</i>. Springer Nature Switzerland; 2024. doi:<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>'
  apa: Meyer, M., Kenter, T., Petrica, L., O’Brien, K., Blott, M., &#38; Plessl, C.
    (2024). Optimizing Communication for Latency Sensitive HPC Applications on up
    to 48 FPGAs Using ACCL. In <i>Lecture Notes in Computer Science</i>. Springer
    Nature Switzerland. <a href="https://doi.org/10.1007/978-3-031-69766-1_9">https://doi.org/10.1007/978-3-031-69766-1_9</a>
  bibtex: '@inbook{Meyer_Kenter_Petrica_O’Brien_Blott_Plessl_2024, place={Cham}, title={Optimizing
    Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL},
    DOI={<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>},
    booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
    author={Meyer, Marius and Kenter, Tobias and Petrica, Lucian and O’Brien, Kenneth
    and Blott, Michaela and Plessl, Christian}, year={2024} }'
  chicago: 'Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela
    Blott, and Christian Plessl. “Optimizing Communication for Latency Sensitive HPC
    Applications on up to 48 FPGAs Using ACCL.” In <i>Lecture Notes in Computer Science</i>.
    Cham: Springer Nature Switzerland, 2024. <a href="https://doi.org/10.1007/978-3-031-69766-1_9">https://doi.org/10.1007/978-3-031-69766-1_9</a>.'
  ieee: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, and C. Plessl, “Optimizing
    Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL,”
    in <i>Lecture Notes in Computer Science</i>, Cham: Springer Nature Switzerland,
    2024.'
  mla: Meyer, Marius, et al. “Optimizing Communication for Latency Sensitive HPC Applications
    on up to 48 FPGAs Using ACCL.” <i>Lecture Notes in Computer Science</i>, Springer
    Nature Switzerland, 2024, doi:<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>.
  short: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, in: Lecture
    Notes in Computer Science, Springer Nature Switzerland, Cham, 2024.'
date_created: 2024-10-14T07:51:51Z
date_updated: 2024-10-14T07:55:50Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-69766-1_9
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Cham
publication: Lecture Notes in Computer Science
publication_identifier:
  isbn:
  - '9783031697654'
  - '9783031697661'
  issn:
  - 0302-9743
  - 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: Optimizing Communication for Latency Sensitive HPC Applications on up to 48
  FPGAs Using ACCL
type: book_chapter
user_id: '3145'
year: '2024'
...
---
_id: '62067'
abstract:
- lang: eng
  text: Most FPGA boards in the HPC domain are well-suited for parallel scaling because
    of the direct integration of versatile and high-throughput network ports. However,
    the utilization of their network capabilities is often challenging and error-prone
    because the whole network stack and communication patterns have to be implemented
    and managed on the FPGAs. Also, this approach conceptually involves a trade-off
    between the performance potential of improved communication and the impact of
    resource consumption for communication infrastructure, since the utilized resources
    on the FPGAs could otherwise be used for computations. In this work, we investigate
    this trade-off, firstly, by using synthetic benchmarks to evaluate the different
    configuration options of the communication framework ACCL and their impact on
    communication latency and throughput. Finally, we use our findings to implement
    a shallow water simulation whose scalability heavily depends on low-latency communication.
    With a suitable configuration of ACCL, good scaling behavior can be shown to all
    48 FPGAs installed in the system. Overall, the results show that the availability
    of inter-FPGA communication frameworks as well as the configurability of framework and
    network stack are crucial to achieve the best application performance with low
    latency communication.
author:
- first_name: Marius
  full_name: Meyer, Marius
  id: '40778'
  last_name: Meyer
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Lucian
  full_name: Petrica, Lucian
  last_name: Petrica
- first_name: Kenneth
  full_name: O’Brien, Kenneth
  last_name: O’Brien
- first_name: Michaela
  full_name: Blott, Michaela
  last_name: Blott
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Meyer M, Kenter T, Petrica L, O’Brien K, Blott M, Plessl C. Optimizing Communication
    for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. In: <i>Lecture
    Notes in Computer Science</i>. Springer Nature Switzerland; 2024. doi:<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>'
  apa: Meyer, M., Kenter, T., Petrica, L., O’Brien, K., Blott, M., &#38; Plessl, C.
    (2024). Optimizing Communication for Latency Sensitive HPC Applications on up
    to 48 FPGAs Using ACCL. In <i>Lecture Notes in Computer Science</i>. Springer
    Nature Switzerland. <a href="https://doi.org/10.1007/978-3-031-69766-1_9">https://doi.org/10.1007/978-3-031-69766-1_9</a>
  bibtex: '@inbook{Meyer_Kenter_Petrica_O’Brien_Blott_Plessl_2024, place={Cham}, title={Optimizing
    Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL},
    DOI={<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>},
    booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
    author={Meyer, Marius and Kenter, Tobias and Petrica, Lucian and O’Brien, Kenneth
    and Blott, Michaela and Plessl, Christian}, year={2024} }'
  chicago: 'Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela
    Blott, and Christian Plessl. “Optimizing Communication for Latency Sensitive HPC
    Applications on up to 48 FPGAs Using ACCL.” In <i>Lecture Notes in Computer Science</i>.
    Cham: Springer Nature Switzerland, 2024. <a href="https://doi.org/10.1007/978-3-031-69766-1_9">https://doi.org/10.1007/978-3-031-69766-1_9</a>.'
  ieee: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, and C. Plessl, “Optimizing
    Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL,”
    in <i>Lecture Notes in Computer Science</i>, Cham: Springer Nature Switzerland,
    2024.'
  mla: Meyer, Marius, et al. “Optimizing Communication for Latency Sensitive HPC Applications
    on up to 48 FPGAs Using ACCL.” <i>Lecture Notes in Computer Science</i>, Springer
    Nature Switzerland, 2024, doi:<a href="https://doi.org/10.1007/978-3-031-69766-1_9">10.1007/978-3-031-69766-1_9</a>.
  short: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, in: Lecture
    Notes in Computer Science, Springer Nature Switzerland, Cham, 2024.'
date_created: 2025-11-04T09:50:24Z
date_updated: 2025-11-04T09:51:22Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-69766-1_9
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Cham
project:
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Lecture Notes in Computer Science
publication_identifier:
  isbn:
  - '9783031697654'
  - '9783031697661'
  issn:
  - 0302-9743
  - 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: Optimizing Communication for Latency Sensitive HPC Applications on up to 48
  FPGAs Using ACCL
type: book_chapter
user_id: '3145'
year: '2024'
...