Rezension zu: Bernardo Bátiz-Lazo: Cash and Dash. How ATMs and Computers Changed Banking - Schmitt, Martin (Vierteljahrschrift für Sozial- und Wirtschaftsgeschichte)
Keywords: Wirtschaftsgeschichte; Bankengeschichte; Geldautomat; ATM; Geschichte; Technikgeschichte

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation - Witschen, Linus Matthias; Wiersema, Tobias; Ghasemzadeh Mohammadi, Hassan; Awais, Muhammad; Platzner, Marco (Microelectronics Reliability)
Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.
Keywords: Approximate Computing; Framework; Pareto Front; Accuracy

A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking - Keerthipati, Monica
Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.

FPGA Acceleration of String Search Techniques in Huge Data Sets - Sabu, Nithin S.

Narratives of Vicarious Experience in Oral History Interviews with Craft Artists - Mildorf, Jarmila (Journal of Pragmatics)

Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (Applied Reconfigurable Computing)
Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.

Efficient demultiplexed single-photon source with a quantum dot coupled to a nanophotonic waveguide - Hummel, Thomas; Ouellet-Plamondon, Claudéric; Ugur, Ela; Kulkova, Irina; Lund-Hansen, Toke; Broome, Matthew A.; Uppu, Ravitej; Lodahl, Peter (Applied Physics Letters)
Planar nanostructures allow near-ideal extraction of emission from a quantum emitter embedded within, thereby realizing deterministic single-photon sources. Such a source can be transformed into M single-photon sources by implementing active temporal-to-spatial mode demultiplexing. We report on the realization of such a demultiplexed source based on a quantum dot embedded in a nanophotonic waveguide. Efficient outcoupling (>60%) from the waveguide into a single mode optical fiber is obtained with high-efficiency grating couplers. As a proof-of-concept, active demultiplexing into M = 4 spatial channels is demonstrated by the use of electro-optic modulators with an end-to-end efficiency of >81% into single-mode fibers. Overall, we demonstrate four-photon coincidence rates of >1 Hz even under nonresonant excitation of the quantum dot. The main limitation of the current source is the residual population of other exciton transitions, which corresponds to a finite preparation efficiency of the desired transition. We quantitatively extract a preparation efficiency of 15% using the second-order correlation function measurements. The experiment highlights the applicability of planar nanostructures as efficient multiphoton sources through temporal-to-spatial demultiplexing and lays out a clear path way of how to scale up toward demonstrating quantum advantages with the quantum dot sources.

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation - Witschen, Linus Matthias; Wiersema, Tobias; Ghasemzadeh Mohammadi, Hassan; Awais, Muhammad; Platzner, Marco (Third Workshop on Approximate Computing (AxC 2018))
Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.
Keywords: Approximate Computing; Framework; Pareto Front; Accuracy

Making the Case for Proof-carrying Approximate Circuits - Witschen, Linus Matthias; Wiersema, Tobias; Platzner, Marco (4th Workshop On Approximate Computing (WAPCO 2018))

Enforcing IP Core Connection Properties with Verifiable Security Monitors - Jentzsch, Felix Paul
Keywords: Approximate Computing; Proof-Carrying Hardware; Formal Veriﬁcation

Streak camera imaging of single photons at telecom wavelength - Allgaier, Markus; Ansari, Vahid; Eigner, Christof; Quiring, Viktor; Ricken, Raimund; Donohue, John Matthew; Czerniuk, Thomas; Aßmann, Marc; Bayer, Manfred; Brecht, Benjamin; Silberhorn, Christine (Applied Physics Letters)

A Framework for the Synthesis of Approximate Circuits - Witschen, Linus Matthias

Noble metal free photocatalytic H2 generation on black TiO2: On the influence of crystal facets vs. crystal damage - Liu, Ning; Steinrück, Hans-Georg; Osvet, Andres; Yang, Yuyun; Schmuki, Patrik (Applied Physics Letters)

Proof-Carrying Hardware via Inductive Invariants - Isenberg, Tobias; Platzner, Marco; Wehrheim, Heike; Wiersema, Tobias (ACM Transactions on Design Automation of Electronic Systems)
Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.

Controlling the optical spin Hall effect with light - Lafont, O.; Luk, S. M. H.; Lewandowski, P.; Kwong, N. H.; Leung, P. T.; Galopin, E.; Lemaitre, A.; Tignon, J.; Schumacher, Stefan; Baudin, E.; Binder, R. (Applied Physics Letters)

Species transport on the target during high power impulse magnetron sputtering - Layes, V.; Monje, S.; Corbella, C.; Trieschmann, J.; de los Arcos de Pedro, Maria Teresa; von Keudell, A. (Applied Physics Letters)

Zwischen Wissenschaft und Lebenswelt. Entwicklung, Stand und Zukunftsperspektiven haushaltsbezogener Bildung. - Schlegel-Matthies, Kirsten

An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Computers & Electrical Engineering)
Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware - Wiersema, Tobias; Platzner, Marco (Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016))
Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.

Near infrared Kerr effect and description of field-induced phase transitions in polymer-stabilized blue phase liquid crystals - Atorf, B.; Rasouli, H.; Nordendorf, G.; Wilkes, D.; Kitzerow, Heinz-Siegfried (Applied Physics Letters)
Keywords: Physics and Astronomy (miscellaneous)