[{"date_created":"2026-07-03T21:13:39Z","type":"journal_article","issue":"5","publication":"IEEE Transactions on Computers","citation":{"ieee":"C. Hakert, A. A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, and J.-J. Chen, “ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees,” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, pp. 1488–1502, 2022, doi: <a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>.","apa":"Hakert, C., Khan, A. A., Chen, K.-H., Hameed, F., Castrillon, J., &#38; Chen, J.-J. (2022). ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>, <i>72</i>(5), 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>","short":"C. Hakert, A.A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, J.-J. Chen, IEEE Transactions on Computers 72 (2022) 1488–1502.","chicago":"Hakert, Christian, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, and Jian-Jia Chen. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i> 72, no. 5 (2022): 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>.","mla":"Hakert, Christian, et al. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 1488–502, doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>.","bibtex":"@article{Hakert_Khan_Chen_Hameed_Castrillon_Chen_2022, title={ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees}, volume={72}, DOI={<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>}, number={5}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hakert, Christian and Khan, Asif Ali and Chen, Kuan-Hsun and Hameed, Fazal and Castrillon, Jeronimo and Chen, Jian-Jia}, year={2022}, pages={1488–1502} }","ama":"Hakert C, Khan AA, Chen K-H, Hameed F, Castrillon J, Chen J-J. ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>. 2022;72(5):1488-1502. doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>"},"page":"1488-1502","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","_id":"66180","user_id":"128464","doi":"10.1109/tc.2022.3197094","volume":72,"title":"ROLLED: <u>R</u>acetrack Memory <u>O</u>ptimized <u>L</u>inear <u>L</u>ayout and <u>E</u>fficient <u>D</u>ecomposition of Decision Trees","status":"public","year":"2022","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"full_name":"Hakert, Christian","last_name":"Hakert","first_name":"Christian"},{"last_name":"Khan","first_name":"Asif Ali","full_name":"Khan, Asif Ali"},{"full_name":"Chen, Kuan-Hsun","first_name":"Kuan-Hsun","last_name":"Chen"},{"last_name":"Hameed","first_name":"Fazal","full_name":"Hameed, Fazal"},{"full_name":"Castrillon, Jeronimo","last_name":"Castrillon","first_name":"Jeronimo"},{"first_name":"Jian-Jia","last_name":"Chen","full_name":"Chen, Jian-Jia"}],"publication_status":"published","date_updated":"2026-07-05T14:46:40Z","intvolume":"        72"},{"volume":72,"user_id":"128464","doi":"10.1109/tc.2022.3197094","_id":"66184","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"1488-1502","intvolume":"        72","publication_status":"published","date_updated":"2026-07-05T14:47:02Z","author":[{"first_name":"Christian","last_name":"Hakert","full_name":"Hakert, Christian"},{"full_name":"Khan, Asif Ali","first_name":"Asif Ali","last_name":"Khan"},{"full_name":"Chen, Kuan-Hsun","first_name":"Kuan-Hsun","last_name":"Chen"},{"full_name":"Hameed, Fazal","first_name":"Fazal","last_name":"Hameed"},{"first_name":"Jeronimo","last_name":"Castrillon","full_name":"Castrillon, Jeronimo"},{"first_name":"Jian-Jia","last_name":"Chen","full_name":"Chen, Jian-Jia"}],"publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"status":"public","title":"ROLLED: <u>R</u>acetrack Memory <u>O</u>ptimized <u>L</u>inear <u>L</u>ayout and <u>E</u>fficient <u>D</u>ecomposition of Decision Trees","year":"2022","type":"journal_article","date_created":"2026-07-03T21:14:25Z","citation":{"ama":"Hakert C, Khan AA, Chen K-H, Hameed F, Castrillon J, Chen J-J. ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>. 2022;72(5):1488-1502. doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>","bibtex":"@article{Hakert_Khan_Chen_Hameed_Castrillon_Chen_2022, title={ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees}, volume={72}, DOI={<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>}, number={5}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hakert, Christian and Khan, Asif Ali and Chen, Kuan-Hsun and Hameed, Fazal and Castrillon, Jeronimo and Chen, Jian-Jia}, year={2022}, pages={1488–1502} }","mla":"Hakert, Christian, et al. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 1488–502, doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>.","short":"C. Hakert, A.A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, J.-J. Chen, IEEE Transactions on Computers 72 (2022) 1488–1502.","chicago":"Hakert, Christian, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, and Jian-Jia Chen. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i> 72, no. 5 (2022): 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>.","apa":"Hakert, C., Khan, A. A., Chen, K.-H., Hameed, F., Castrillon, J., &#38; Chen, J.-J. (2022). ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>, <i>72</i>(5), 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>","ieee":"C. Hakert, A. A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, and J.-J. Chen, “ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees,” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, pp. 1488–1502, 2022, doi: <a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>."},"issue":"5","publication":"IEEE Transactions on Computers"},{"_id":"30907","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","language":[{"iso":"eng"}],"page":"1-1","user_id":"398","doi":"10.1109/tc.2021.3107196","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"first_name":"Alfonso","last_name":"Rodriguez","full_name":"Rodriguez, Alfonso"},{"full_name":"Otero, Andres","first_name":"Andres","last_name":"Otero"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"full_name":"De la Torre, Eduardo","last_name":"De la Torre","first_name":"Eduardo"}],"status":"public","year":"2021","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs","publication_status":"published","date_updated":"2022-04-18T10:04:21Z","date_created":"2022-04-18T10:03:16Z","department":[{"_id":"78"}],"type":"journal_article","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"citation":{"short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>."},"publication":"IEEE Transactions on Computers"},{"type":"journal_article","date_created":"2026-07-03T21:17:58Z","publication":"IEEE Transactions on Computers","issue":"7","citation":{"short":"M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695.","chicago":"Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i> 71, no. 7 (2021): 1681–95. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>.","apa":"Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., &#38; Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>, <i>71</i>(7), 1681–1695. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>","ieee":"M. Yayla <i>et al.</i>, “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, pp. 1681–1695, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>.","ama":"Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>. 2021;71(7):1681-1695. doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>","bibtex":"@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }","mla":"Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>."},"doi":"10.1109/tc.2021.3104736","user_id":"128464","volume":71,"page":"1681-1695","_id":"66206","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2026-07-05T14:45:42Z","publication_status":"published","intvolume":"        71","status":"public","year":"2021","title":"FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"full_name":"Yayla, Mikail","first_name":"Mikail","last_name":"Yayla"},{"first_name":"Sebastian","last_name":"Buschjager","full_name":"Buschjager, Sebastian"},{"last_name":"Gupta","first_name":"Aniket","full_name":"Gupta, Aniket"},{"full_name":"Chen, Jian-Jia","first_name":"Jian-Jia","last_name":"Chen"},{"full_name":"Henkel, Jorg","last_name":"Henkel","first_name":"Jorg"},{"last_name":"Morik","first_name":"Katharina","full_name":"Morik, Katharina"},{"full_name":"Chen, Kuan-Hsun","first_name":"Kuan-Hsun","last_name":"Chen"},{"full_name":"Amrouch, Hussam","first_name":"Hussam","last_name":"Amrouch"}]},{"type":"journal_article","date_created":"2026-07-03T21:17:54Z","citation":{"chicago":"Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i> 71, no. 7 (2021): 1681–95. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>.","short":"M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695.","apa":"Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., &#38; Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>, <i>71</i>(7), 1681–1695. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>","ieee":"M. Yayla <i>et al.</i>, “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, pp. 1681–1695, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>.","ama":"Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>. 2021;71(7):1681-1695. doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>","bibtex":"@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }","mla":"Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>."},"issue":"7","publication":"IEEE Transactions on Computers","volume":71,"user_id":"128464","doi":"10.1109/tc.2021.3104736","_id":"66204","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"1681-1695","intvolume":"        71","publication_status":"published","date_updated":"2026-07-05T14:46:19Z","author":[{"full_name":"Yayla, Mikail","first_name":"Mikail","last_name":"Yayla"},{"full_name":"Buschjager, Sebastian","last_name":"Buschjager","first_name":"Sebastian"},{"last_name":"Gupta","first_name":"Aniket","full_name":"Gupta, Aniket"},{"full_name":"Chen, Jian-Jia","last_name":"Chen","first_name":"Jian-Jia"},{"first_name":"Jorg","last_name":"Henkel","full_name":"Henkel, Jorg"},{"first_name":"Katharina","last_name":"Morik","full_name":"Morik, Katharina"},{"full_name":"Chen, Kuan-Hsun","first_name":"Kuan-Hsun","last_name":"Chen"},{"full_name":"Amrouch, Hussam","first_name":"Hussam","last_name":"Amrouch"}],"publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"status":"public","year":"2021","title":"FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors"},{"page":"1681-1695","_id":"66200","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","user_id":"128464","doi":"10.1109/tc.2021.3104736","volume":71,"title":"FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors","status":"public","year":"2021","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"full_name":"Yayla, Mikail","last_name":"Yayla","first_name":"Mikail"},{"full_name":"Buschjager, Sebastian","last_name":"Buschjager","first_name":"Sebastian"},{"first_name":"Aniket","last_name":"Gupta","full_name":"Gupta, Aniket"},{"last_name":"Chen","first_name":"Jian-Jia","full_name":"Chen, Jian-Jia"},{"last_name":"Henkel","first_name":"Jorg","full_name":"Henkel, Jorg"},{"full_name":"Morik, Katharina","first_name":"Katharina","last_name":"Morik"},{"full_name":"Chen, Kuan-Hsun","first_name":"Kuan-Hsun","last_name":"Chen"},{"full_name":"Amrouch, Hussam","first_name":"Hussam","last_name":"Amrouch"}],"publication_status":"published","date_updated":"2026-07-05T14:46:28Z","intvolume":"        71","date_created":"2026-07-03T21:17:12Z","type":"journal_article","publication":"IEEE Transactions on Computers","issue":"7","citation":{"chicago":"Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i> 71, no. 7 (2021): 1681–95. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>.","short":"M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695.","ieee":"M. Yayla <i>et al.</i>, “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, pp. 1681–1695, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>.","apa":"Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., &#38; Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>, <i>71</i>(7), 1681–1695. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>","bibtex":"@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }","ama":"Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>. 2021;71(7):1681-1695. doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>","mla":"Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>."}},{"volume":67,"doi":"10.1109/tc.2017.2769044","user_id":"128464","_id":"66249","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"484-497","intvolume":"        67","date_updated":"2026-07-05T14:43:18Z","publication_status":"published","publication_identifier":{"issn":["0018-9340"]},"author":[{"last_name":"Chen","first_name":"Kuan-Hsun","full_name":"Chen, Kuan-Hsun"},{"first_name":"Georg von","last_name":"der Bruggen","full_name":"der Bruggen, Georg von"},{"last_name":"Chen","first_name":"Jian-Jia","full_name":"Chen, Jian-Jia"}],"status":"public","title":"Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading","year":"2017","type":"journal_article","date_created":"2026-07-05T14:36:23Z","citation":{"ieee":"K.-H. Chen, G. von der Bruggen, and J.-J. Chen, “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading,” <i>IEEE Transactions on Computers</i>, vol. 67, no. 4, pp. 484–497, 2017, doi: <a href=\"https://doi.org/10.1109/tc.2017.2769044\">10.1109/tc.2017.2769044</a>.","apa":"Chen, K.-H., der Bruggen, G. von, &#38; Chen, J.-J. (2017). Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading. <i>IEEE Transactions on Computers</i>, <i>67</i>(4), 484–497. <a href=\"https://doi.org/10.1109/tc.2017.2769044\">https://doi.org/10.1109/tc.2017.2769044</a>","chicago":"Chen, Kuan-Hsun, Georg von der Bruggen, and Jian-Jia Chen. “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading.” <i>IEEE Transactions on Computers</i> 67, no. 4 (2017): 484–97. <a href=\"https://doi.org/10.1109/tc.2017.2769044\">https://doi.org/10.1109/tc.2017.2769044</a>.","short":"K.-H. Chen, G. von der Bruggen, J.-J. Chen, IEEE Transactions on Computers 67 (2017) 484–497.","mla":"Chen, Kuan-Hsun, et al. “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading.” <i>IEEE Transactions on Computers</i>, vol. 67, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2017, pp. 484–97, doi:<a href=\"https://doi.org/10.1109/tc.2017.2769044\">10.1109/tc.2017.2769044</a>.","bibtex":"@article{Chen_der Bruggen_Chen_2017, title={Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading}, volume={67}, DOI={<a href=\"https://doi.org/10.1109/tc.2017.2769044\">10.1109/tc.2017.2769044</a>}, number={4}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chen, Kuan-Hsun and der Bruggen, Georg von and Chen, Jian-Jia}, year={2017}, pages={484–497} }","ama":"Chen K-H, der Bruggen G von, Chen J-J. Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading. <i>IEEE Transactions on Computers</i>. 2017;67(4):484-497. doi:<a href=\"https://doi.org/10.1109/tc.2017.2769044\">10.1109/tc.2017.2769044</a>"},"publication":"IEEE Transactions on Computers","issue":"4"},{"date_created":"2026-07-05T14:37:53Z","type":"journal_article","issue":"11","publication":"IEEE Transactions on Computers","citation":{"ama":"Chen K-H, Chen J-J, Kriebel F, Rehman S, Shafique M, Henkel J. Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. <i>IEEE Transactions on Computers</i>. 2016;65(11):3441-3455. doi:<a href=\"https://doi.org/10.1109/tc.2016.2532862\">10.1109/tc.2016.2532862</a>","bibtex":"@article{Chen_Chen_Kriebel_Rehman_Shafique_Henkel_2016, title={Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity}, volume={65}, DOI={<a href=\"https://doi.org/10.1109/tc.2016.2532862\">10.1109/tc.2016.2532862</a>}, number={11}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chen, Kuan-Hsun and Chen, Jian-Jia and Kriebel, Florian and Rehman, Semeen and Shafique, Muhammad and Henkel, Jorg}, year={2016}, pages={3441–3455} }","mla":"Chen, Kuan-Hsun, et al. “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.” <i>IEEE Transactions on Computers</i>, vol. 65, no. 11, Institute of Electrical and Electronics Engineers (IEEE), 2016, pp. 3441–55, doi:<a href=\"https://doi.org/10.1109/tc.2016.2532862\">10.1109/tc.2016.2532862</a>.","chicago":"Chen, Kuan-Hsun, Jian-Jia Chen, Florian Kriebel, Semeen Rehman, Muhammad Shafique, and Jorg Henkel. “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.” <i>IEEE Transactions on Computers</i> 65, no. 11 (2016): 3441–55. <a href=\"https://doi.org/10.1109/tc.2016.2532862\">https://doi.org/10.1109/tc.2016.2532862</a>.","short":"K.-H. Chen, J.-J. Chen, F. Kriebel, S. Rehman, M. Shafique, J. Henkel, IEEE Transactions on Computers 65 (2016) 3441–3455.","apa":"Chen, K.-H., Chen, J.-J., Kriebel, F., Rehman, S., Shafique, M., &#38; Henkel, J. (2016). Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. <i>IEEE Transactions on Computers</i>, <i>65</i>(11), 3441–3455. <a href=\"https://doi.org/10.1109/tc.2016.2532862\">https://doi.org/10.1109/tc.2016.2532862</a>","ieee":"K.-H. Chen, J.-J. Chen, F. Kriebel, S. Rehman, M. Shafique, and J. Henkel, “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity,” <i>IEEE Transactions on Computers</i>, vol. 65, no. 11, pp. 3441–3455, 2016, doi: <a href=\"https://doi.org/10.1109/tc.2016.2532862\">10.1109/tc.2016.2532862</a>."},"page":"3441-3455","_id":"66257","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","doi":"10.1109/tc.2016.2532862","user_id":"128464","volume":65,"status":"public","title":"Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity","year":"2016","author":[{"first_name":"Kuan-Hsun","last_name":"Chen","full_name":"Chen, Kuan-Hsun"},{"full_name":"Chen, Jian-Jia","last_name":"Chen","first_name":"Jian-Jia"},{"full_name":"Kriebel, Florian","last_name":"Kriebel","first_name":"Florian"},{"last_name":"Rehman","first_name":"Semeen","full_name":"Rehman, Semeen"},{"full_name":"Shafique, Muhammad","first_name":"Muhammad","last_name":"Shafique"},{"last_name":"Henkel","first_name":"Jorg","full_name":"Henkel, Jorg"}],"publication_identifier":{"issn":["0018-9340"]},"date_updated":"2026-07-05T14:43:36Z","publication_status":"published","intvolume":"        65"},{"author":[{"last_name":"Rehman","first_name":"Semeen","full_name":"Rehman, Semeen"},{"first_name":"Kuan-Hsun","last_name":"Chen","full_name":"Chen, Kuan-Hsun"},{"first_name":"Florian","last_name":"Kriebel","full_name":"Kriebel, Florian"},{"full_name":"Toma, Anas","last_name":"Toma","first_name":"Anas"},{"full_name":"Shafique, Muhammad","first_name":"Muhammad","last_name":"Shafique"},{"full_name":"Chen, Jian-Jia","first_name":"Jian-Jia","last_name":"Chen"},{"last_name":"Henkel","first_name":"Jorg","full_name":"Henkel, Jorg"}],"publication_identifier":{"issn":["0018-9340"]},"year":"2015","title":"Cross-Layer Software Dependability on Unreliable Hardware","status":"public","intvolume":"        65","publication_status":"published","date_updated":"2026-07-05T14:43:34Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","_id":"66256","page":"80-94","volume":65,"user_id":"128464","doi":"10.1109/tc.2015.2417554","citation":{"mla":"Rehman, Semeen, et al. “Cross-Layer Software Dependability on Unreliable Hardware.” <i>IEEE Transactions on Computers</i>, vol. 65, no. 1, Institute of Electrical and Electronics Engineers (IEEE), 2015, pp. 80–94, doi:<a href=\"https://doi.org/10.1109/tc.2015.2417554\">10.1109/tc.2015.2417554</a>.","ama":"Rehman S, Chen K-H, Kriebel F, et al. Cross-Layer Software Dependability on Unreliable Hardware. <i>IEEE Transactions on Computers</i>. 2015;65(1):80-94. doi:<a href=\"https://doi.org/10.1109/tc.2015.2417554\">10.1109/tc.2015.2417554</a>","bibtex":"@article{Rehman_Chen_Kriebel_Toma_Shafique_Chen_Henkel_2015, title={Cross-Layer Software Dependability on Unreliable Hardware}, volume={65}, DOI={<a href=\"https://doi.org/10.1109/tc.2015.2417554\">10.1109/tc.2015.2417554</a>}, number={1}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rehman, Semeen and Chen, Kuan-Hsun and Kriebel, Florian and Toma, Anas and Shafique, Muhammad and Chen, Jian-Jia and Henkel, Jorg}, year={2015}, pages={80–94} }","apa":"Rehman, S., Chen, K.-H., Kriebel, F., Toma, A., Shafique, M., Chen, J.-J., &#38; Henkel, J. (2015). Cross-Layer Software Dependability on Unreliable Hardware. <i>IEEE Transactions on Computers</i>, <i>65</i>(1), 80–94. <a href=\"https://doi.org/10.1109/tc.2015.2417554\">https://doi.org/10.1109/tc.2015.2417554</a>","ieee":"S. Rehman <i>et al.</i>, “Cross-Layer Software Dependability on Unreliable Hardware,” <i>IEEE Transactions on Computers</i>, vol. 65, no. 1, pp. 80–94, 2015, doi: <a href=\"https://doi.org/10.1109/tc.2015.2417554\">10.1109/tc.2015.2417554</a>.","short":"S. Rehman, K.-H. Chen, F. Kriebel, A. Toma, M. Shafique, J.-J. Chen, J. Henkel, IEEE Transactions on Computers 65 (2015) 80–94.","chicago":"Rehman, Semeen, Kuan-Hsun Chen, Florian Kriebel, Anas Toma, Muhammad Shafique, Jian-Jia Chen, and Jorg Henkel. “Cross-Layer Software Dependability on Unreliable Hardware.” <i>IEEE Transactions on Computers</i> 65, no. 1 (2015): 80–94. <a href=\"https://doi.org/10.1109/tc.2015.2417554\">https://doi.org/10.1109/tc.2015.2417554</a>."},"issue":"1","publication":"IEEE Transactions on Computers","date_created":"2026-07-05T14:37:43Z","type":"journal_article"},{"type":"journal_article","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"department":[{"_id":"48"}],"date_created":"2023-08-02T11:15:22Z","extern":"1","publication":"IEEE Transactions on Computers","citation":{"ama":"Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>. Published online 2014:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>","bibtex":"@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }","mla":"Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","short":"B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.","chicago":"Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, 2014, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>.","apa":"Alizadeh, B., Behnam, P., &#38; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>","ieee":"B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2014, doi: <a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>."},"user_id":"78614","doi":"10.1109/tc.2014.2329687","page":"1-1","_id":"46266","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2023-08-02T11:32:37Z","status":"public","year":"2014","title":"A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs","author":[{"first_name":"Bijan","last_name":"Alizadeh","full_name":"Alizadeh, Bijan"},{"full_name":"Behnam, Payman","last_name":"Behnam","first_name":"Payman"},{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610"}],"publication_identifier":{"issn":["0018-9340"]}}]
