--- _id: '66180' author: - first_name: Christian full_name: Hakert, Christian last_name: Hakert - first_name: Asif Ali full_name: Khan, Asif Ali last_name: Khan - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Fazal full_name: Hameed, Fazal last_name: Hameed - first_name: Jeronimo full_name: Castrillon, Jeronimo last_name: Castrillon - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen citation: ama: 'Hakert C, Khan AA, Chen K-H, Hameed F, Castrillon J, Chen J-J. ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Transactions on Computers. 2022;72(5):1488-1502. doi:10.1109/tc.2022.3197094' apa: 'Hakert, C., Khan, A. A., Chen, K.-H., Hameed, F., Castrillon, J., & Chen, J.-J. (2022). ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Transactions on Computers, 72(5), 1488–1502. https://doi.org/10.1109/tc.2022.3197094' bibtex: '@article{Hakert_Khan_Chen_Hameed_Castrillon_Chen_2022, title={ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees}, volume={72}, DOI={10.1109/tc.2022.3197094}, number={5}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hakert, Christian and Khan, Asif Ali and Chen, Kuan-Hsun and Hameed, Fazal and Castrillon, Jeronimo and Chen, Jian-Jia}, year={2022}, pages={1488–1502} }' chicago: 'Hakert, Christian, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, and Jian-Jia Chen. “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.” IEEE Transactions on Computers 72, no. 5 (2022): 1488–1502. https://doi.org/10.1109/tc.2022.3197094.' ieee: 'C. Hakert, A. A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, and J.-J. Chen, “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees,” IEEE Transactions on Computers, vol. 72, no. 5, pp. 1488–1502, 2022, doi: 10.1109/tc.2022.3197094.' mla: 'Hakert, Christian, et al. “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.” IEEE Transactions on Computers, vol. 72, no. 5, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 1488–502, doi:10.1109/tc.2022.3197094.' short: C. Hakert, A.A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, J.-J. Chen, IEEE Transactions on Computers 72 (2022) 1488–1502. date_created: 2026-07-03T21:13:39Z date_updated: 2026-07-05T14:46:40Z doi: 10.1109/tc.2022.3197094 intvolume: ' 72' issue: '5' page: 1488-1502 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: 'ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees' type: journal_article user_id: '128464' volume: 72 year: '2022' ... --- _id: '66184' author: - first_name: Christian full_name: Hakert, Christian last_name: Hakert - first_name: Asif Ali full_name: Khan, Asif Ali last_name: Khan - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Fazal full_name: Hameed, Fazal last_name: Hameed - first_name: Jeronimo full_name: Castrillon, Jeronimo last_name: Castrillon - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen citation: ama: 'Hakert C, Khan AA, Chen K-H, Hameed F, Castrillon J, Chen J-J. ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Transactions on Computers. 2022;72(5):1488-1502. doi:10.1109/tc.2022.3197094' apa: 'Hakert, C., Khan, A. A., Chen, K.-H., Hameed, F., Castrillon, J., & Chen, J.-J. (2022). ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Transactions on Computers, 72(5), 1488–1502. https://doi.org/10.1109/tc.2022.3197094' bibtex: '@article{Hakert_Khan_Chen_Hameed_Castrillon_Chen_2022, title={ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees}, volume={72}, DOI={10.1109/tc.2022.3197094}, number={5}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hakert, Christian and Khan, Asif Ali and Chen, Kuan-Hsun and Hameed, Fazal and Castrillon, Jeronimo and Chen, Jian-Jia}, year={2022}, pages={1488–1502} }' chicago: 'Hakert, Christian, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, and Jian-Jia Chen. “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.” IEEE Transactions on Computers 72, no. 5 (2022): 1488–1502. https://doi.org/10.1109/tc.2022.3197094.' ieee: 'C. Hakert, A. A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, and J.-J. Chen, “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees,” IEEE Transactions on Computers, vol. 72, no. 5, pp. 1488–1502, 2022, doi: 10.1109/tc.2022.3197094.' mla: 'Hakert, Christian, et al. “ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.” IEEE Transactions on Computers, vol. 72, no. 5, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 1488–502, doi:10.1109/tc.2022.3197094.' short: C. Hakert, A.A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, J.-J. Chen, IEEE Transactions on Computers 72 (2022) 1488–1502. date_created: 2026-07-03T21:14:25Z date_updated: 2026-07-05T14:47:02Z doi: 10.1109/tc.2022.3197094 intvolume: ' 72' issue: '5' page: 1488-1502 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: 'ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees' type: journal_article user_id: '128464' volume: 72 year: '2022' ... --- _id: '30907' author: - first_name: Alfonso full_name: Rodriguez, Alfonso last_name: Rodriguez - first_name: Andres full_name: Otero, Andres last_name: Otero - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Eduardo full_name: De la Torre, Eduardo last_name: De la Torre citation: ama: Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196 apa: Rodriguez, A., Otero, A., Platzner, M., & De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2021.3107196 bibtex: '@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={10.1109/tc.2021.3107196}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }' chicago: Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, 2021, 1–1. https://doi.org/10.1109/tc.2021.3107196. ieee: 'A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.' mla: Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:10.1109/tc.2021.3107196. short: A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1. date_created: 2022-04-18T10:03:16Z date_updated: 2022-04-18T10:04:21Z department: - _id: '78' doi: 10.1109/tc.2021.3107196 keyword: - Computational Theory and Mathematics - Hardware and Architecture - Theoretical Computer Science - Software language: - iso: eng page: 1-1 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs type: journal_article user_id: '398' year: '2021' ... --- _id: '66206' author: - first_name: Mikail full_name: Yayla, Mikail last_name: Yayla - first_name: Sebastian full_name: Buschjager, Sebastian last_name: Buschjager - first_name: Aniket full_name: Gupta, Aniket last_name: Gupta - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen - first_name: Jorg full_name: Henkel, Jorg last_name: Henkel - first_name: Katharina full_name: Morik, Katharina last_name: Morik - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Hussam full_name: Amrouch, Hussam last_name: Amrouch citation: ama: Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers. 2021;71(7):1681-1695. doi:10.1109/tc.2021.3104736 apa: Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., & Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers, 71(7), 1681–1695. https://doi.org/10.1109/tc.2021.3104736 bibtex: '@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={10.1109/tc.2021.3104736}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }' chicago: 'Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers 71, no. 7 (2021): 1681–95. https://doi.org/10.1109/tc.2021.3104736.' ieee: 'M. Yayla et al., “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” IEEE Transactions on Computers, vol. 71, no. 7, pp. 1681–1695, 2021, doi: 10.1109/tc.2021.3104736.' mla: Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:10.1109/tc.2021.3104736. short: M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695. date_created: 2026-07-03T21:17:58Z date_updated: 2026-07-05T14:45:42Z doi: 10.1109/tc.2021.3104736 intvolume: ' 71' issue: '7' page: 1681-1695 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors type: journal_article user_id: '128464' volume: 71 year: '2021' ... --- _id: '66204' author: - first_name: Mikail full_name: Yayla, Mikail last_name: Yayla - first_name: Sebastian full_name: Buschjager, Sebastian last_name: Buschjager - first_name: Aniket full_name: Gupta, Aniket last_name: Gupta - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen - first_name: Jorg full_name: Henkel, Jorg last_name: Henkel - first_name: Katharina full_name: Morik, Katharina last_name: Morik - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Hussam full_name: Amrouch, Hussam last_name: Amrouch citation: ama: Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers. 2021;71(7):1681-1695. doi:10.1109/tc.2021.3104736 apa: Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., & Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers, 71(7), 1681–1695. https://doi.org/10.1109/tc.2021.3104736 bibtex: '@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={10.1109/tc.2021.3104736}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }' chicago: 'Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers 71, no. 7 (2021): 1681–95. https://doi.org/10.1109/tc.2021.3104736.' ieee: 'M. Yayla et al., “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” IEEE Transactions on Computers, vol. 71, no. 7, pp. 1681–1695, 2021, doi: 10.1109/tc.2021.3104736.' mla: Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:10.1109/tc.2021.3104736. short: M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695. date_created: 2026-07-03T21:17:54Z date_updated: 2026-07-05T14:46:19Z doi: 10.1109/tc.2021.3104736 intvolume: ' 71' issue: '7' page: 1681-1695 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors type: journal_article user_id: '128464' volume: 71 year: '2021' ... --- _id: '66200' author: - first_name: Mikail full_name: Yayla, Mikail last_name: Yayla - first_name: Sebastian full_name: Buschjager, Sebastian last_name: Buschjager - first_name: Aniket full_name: Gupta, Aniket last_name: Gupta - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen - first_name: Jorg full_name: Henkel, Jorg last_name: Henkel - first_name: Katharina full_name: Morik, Katharina last_name: Morik - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Hussam full_name: Amrouch, Hussam last_name: Amrouch citation: ama: Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers. 2021;71(7):1681-1695. doi:10.1109/tc.2021.3104736 apa: Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., & Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. IEEE Transactions on Computers, 71(7), 1681–1695. https://doi.org/10.1109/tc.2021.3104736 bibtex: '@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={10.1109/tc.2021.3104736}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }' chicago: 'Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers 71, no. 7 (2021): 1681–95. https://doi.org/10.1109/tc.2021.3104736.' ieee: 'M. Yayla et al., “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” IEEE Transactions on Computers, vol. 71, no. 7, pp. 1681–1695, 2021, doi: 10.1109/tc.2021.3104736.' mla: Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” IEEE Transactions on Computers, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:10.1109/tc.2021.3104736. short: M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695. date_created: 2026-07-03T21:17:12Z date_updated: 2026-07-05T14:46:28Z doi: 10.1109/tc.2021.3104736 intvolume: ' 71' issue: '7' page: 1681-1695 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 - 1557-9956 - 2326-3814 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors type: journal_article user_id: '128464' volume: 71 year: '2021' ... --- _id: '66249' author: - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Georg von full_name: der Bruggen, Georg von last_name: der Bruggen - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen citation: ama: Chen K-H, der Bruggen G von, Chen J-J. Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading. IEEE Transactions on Computers. 2017;67(4):484-497. doi:10.1109/tc.2017.2769044 apa: Chen, K.-H., der Bruggen, G. von, & Chen, J.-J. (2017). Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading. IEEE Transactions on Computers, 67(4), 484–497. https://doi.org/10.1109/tc.2017.2769044 bibtex: '@article{Chen_der Bruggen_Chen_2017, title={Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading}, volume={67}, DOI={10.1109/tc.2017.2769044}, number={4}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chen, Kuan-Hsun and der Bruggen, Georg von and Chen, Jian-Jia}, year={2017}, pages={484–497} }' chicago: 'Chen, Kuan-Hsun, Georg von der Bruggen, and Jian-Jia Chen. “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading.” IEEE Transactions on Computers 67, no. 4 (2017): 484–97. https://doi.org/10.1109/tc.2017.2769044.' ieee: 'K.-H. Chen, G. von der Bruggen, and J.-J. Chen, “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading,” IEEE Transactions on Computers, vol. 67, no. 4, pp. 484–497, 2017, doi: 10.1109/tc.2017.2769044.' mla: Chen, Kuan-Hsun, et al. “Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading.” IEEE Transactions on Computers, vol. 67, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2017, pp. 484–97, doi:10.1109/tc.2017.2769044. short: K.-H. Chen, G. von der Bruggen, J.-J. Chen, IEEE Transactions on Computers 67 (2017) 484–497. date_created: 2026-07-05T14:36:23Z date_updated: 2026-07-05T14:43:18Z doi: 10.1109/tc.2017.2769044 intvolume: ' 67' issue: '4' page: 484-497 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading type: journal_article user_id: '128464' volume: 67 year: '2017' ... --- _id: '66257' author: - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen - first_name: Florian full_name: Kriebel, Florian last_name: Kriebel - first_name: Semeen full_name: Rehman, Semeen last_name: Rehman - first_name: Muhammad full_name: Shafique, Muhammad last_name: Shafique - first_name: Jorg full_name: Henkel, Jorg last_name: Henkel citation: ama: Chen K-H, Chen J-J, Kriebel F, Rehman S, Shafique M, Henkel J. Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. IEEE Transactions on Computers. 2016;65(11):3441-3455. doi:10.1109/tc.2016.2532862 apa: Chen, K.-H., Chen, J.-J., Kriebel, F., Rehman, S., Shafique, M., & Henkel, J. (2016). Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. IEEE Transactions on Computers, 65(11), 3441–3455. https://doi.org/10.1109/tc.2016.2532862 bibtex: '@article{Chen_Chen_Kriebel_Rehman_Shafique_Henkel_2016, title={Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity}, volume={65}, DOI={10.1109/tc.2016.2532862}, number={11}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chen, Kuan-Hsun and Chen, Jian-Jia and Kriebel, Florian and Rehman, Semeen and Shafique, Muhammad and Henkel, Jorg}, year={2016}, pages={3441–3455} }' chicago: 'Chen, Kuan-Hsun, Jian-Jia Chen, Florian Kriebel, Semeen Rehman, Muhammad Shafique, and Jorg Henkel. “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.” IEEE Transactions on Computers 65, no. 11 (2016): 3441–55. https://doi.org/10.1109/tc.2016.2532862.' ieee: 'K.-H. Chen, J.-J. Chen, F. Kriebel, S. Rehman, M. Shafique, and J. Henkel, “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity,” IEEE Transactions on Computers, vol. 65, no. 11, pp. 3441–3455, 2016, doi: 10.1109/tc.2016.2532862.' mla: Chen, Kuan-Hsun, et al. “Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.” IEEE Transactions on Computers, vol. 65, no. 11, Institute of Electrical and Electronics Engineers (IEEE), 2016, pp. 3441–55, doi:10.1109/tc.2016.2532862. short: K.-H. Chen, J.-J. Chen, F. Kriebel, S. Rehman, M. Shafique, J. Henkel, IEEE Transactions on Computers 65 (2016) 3441–3455. date_created: 2026-07-05T14:37:53Z date_updated: 2026-07-05T14:43:36Z doi: 10.1109/tc.2016.2532862 intvolume: ' 65' issue: '11' page: 3441-3455 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity type: journal_article user_id: '128464' volume: 65 year: '2016' ... --- _id: '66256' author: - first_name: Semeen full_name: Rehman, Semeen last_name: Rehman - first_name: Kuan-Hsun full_name: Chen, Kuan-Hsun last_name: Chen - first_name: Florian full_name: Kriebel, Florian last_name: Kriebel - first_name: Anas full_name: Toma, Anas last_name: Toma - first_name: Muhammad full_name: Shafique, Muhammad last_name: Shafique - first_name: Jian-Jia full_name: Chen, Jian-Jia last_name: Chen - first_name: Jorg full_name: Henkel, Jorg last_name: Henkel citation: ama: Rehman S, Chen K-H, Kriebel F, et al. Cross-Layer Software Dependability on Unreliable Hardware. IEEE Transactions on Computers. 2015;65(1):80-94. doi:10.1109/tc.2015.2417554 apa: Rehman, S., Chen, K.-H., Kriebel, F., Toma, A., Shafique, M., Chen, J.-J., & Henkel, J. (2015). Cross-Layer Software Dependability on Unreliable Hardware. IEEE Transactions on Computers, 65(1), 80–94. https://doi.org/10.1109/tc.2015.2417554 bibtex: '@article{Rehman_Chen_Kriebel_Toma_Shafique_Chen_Henkel_2015, title={Cross-Layer Software Dependability on Unreliable Hardware}, volume={65}, DOI={10.1109/tc.2015.2417554}, number={1}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rehman, Semeen and Chen, Kuan-Hsun and Kriebel, Florian and Toma, Anas and Shafique, Muhammad and Chen, Jian-Jia and Henkel, Jorg}, year={2015}, pages={80–94} }' chicago: 'Rehman, Semeen, Kuan-Hsun Chen, Florian Kriebel, Anas Toma, Muhammad Shafique, Jian-Jia Chen, and Jorg Henkel. “Cross-Layer Software Dependability on Unreliable Hardware.” IEEE Transactions on Computers 65, no. 1 (2015): 80–94. https://doi.org/10.1109/tc.2015.2417554.' ieee: 'S. Rehman et al., “Cross-Layer Software Dependability on Unreliable Hardware,” IEEE Transactions on Computers, vol. 65, no. 1, pp. 80–94, 2015, doi: 10.1109/tc.2015.2417554.' mla: Rehman, Semeen, et al. “Cross-Layer Software Dependability on Unreliable Hardware.” IEEE Transactions on Computers, vol. 65, no. 1, Institute of Electrical and Electronics Engineers (IEEE), 2015, pp. 80–94, doi:10.1109/tc.2015.2417554. short: S. Rehman, K.-H. Chen, F. Kriebel, A. Toma, M. Shafique, J.-J. Chen, J. Henkel, IEEE Transactions on Computers 65 (2015) 80–94. date_created: 2026-07-05T14:37:43Z date_updated: 2026-07-05T14:43:34Z doi: 10.1109/tc.2015.2417554 intvolume: ' 65' issue: '1' page: 80-94 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Cross-Layer Software Dependability on Unreliable Hardware type: journal_article user_id: '128464' volume: 65 year: '2015' ... --- _id: '46266' author: - first_name: Bijan full_name: Alizadeh, Bijan last_name: Alizadeh - first_name: Payman full_name: Behnam, Payman last_name: Behnam - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 citation: ama: Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers. Published online 2014:1-1. doi:10.1109/tc.2014.2329687 apa: Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2014.2329687 bibtex: '@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={10.1109/tc.2014.2329687}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }' chicago: Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers, 2014, 1–1. https://doi.org/10.1109/tc.2014.2329687. ieee: 'B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.' mla: Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687. short: B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1. date_created: 2023-08-02T11:15:22Z date_updated: 2023-08-02T11:32:37Z department: - _id: '48' doi: 10.1109/tc.2014.2329687 extern: '1' keyword: - Computational Theory and Mathematics - Hardware and Architecture - Theoretical Computer Science - Software language: - iso: eng page: 1-1 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs type: journal_article user_id: '78614' year: '2014' ...