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Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. 2022;42(8):2527-2539. doi:<a href=\"https://doi.org/10.1109/tcad.2022.3228897\">10.1109/tcad.2022.3228897</a>","ieee":"N. Hölscher <i>et al.</i>, “Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory,” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, vol. 42, no. 8, pp. 2527–2539, 2022, doi: <a href=\"https://doi.org/10.1109/tcad.2022.3228897\">10.1109/tcad.2022.3228897</a>.","apa":"Hölscher, N., Hakert, C., Nassar, H., Chen, K.-H., Bauer, L., Chen, J.-J., &#38; Henkel, J. (2022). Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, <i>42</i>(8), 2527–2539. <a href=\"https://doi.org/10.1109/tcad.2022.3228897\">https://doi.org/10.1109/tcad.2022.3228897</a>","short":"N. Hölscher, C. Hakert, H. Nassar, K.-H. Chen, L. Bauer, J.-J. Chen, J. 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Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. 2022;41(11):4157-4168. doi:<a href=\"https://doi.org/10.1109/tcad.2022.3197501\">10.1109/tcad.2022.3197501</a>","bibtex":"@article{Shi_von Egidy_Chen_Chen_2022, title={Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS}, volume={41}, DOI={<a href=\"https://doi.org/10.1109/tcad.2022.3197501\">10.1109/tcad.2022.3197501</a>}, number={11}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Shi, Junjie and von Egidy, Christoph-Cordt and Chen, Kuan-Hsun and Chen, Jian-Jia}, year={2022}, pages={4157–4168} }","mla":"Shi, Junjie, et al. “Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, vol. 41, no. 11, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 4157–68, doi:<a href=\"https://doi.org/10.1109/tcad.2022.3197501\">10.1109/tcad.2022.3197501</a>.","chicago":"Shi, Junjie, Christoph-Cordt von Egidy, Kuan-Hsun Chen, and Jian-Jia Chen. “Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i> 41, no. 11 (2022): 4157–68. <a href=\"https://doi.org/10.1109/tcad.2022.3197501\">https://doi.org/10.1109/tcad.2022.3197501</a>.","short":"J. Shi, C.-C. von Egidy, K.-H. Chen, J.-J. Chen, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 (2022) 4157–4168.","apa":"Shi, J., von Egidy, C.-C., Chen, K.-H., &#38; Chen, J.-J. (2022). Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, <i>41</i>(11), 4157–4168. <a href=\"https://doi.org/10.1109/tcad.2022.3197501\">https://doi.org/10.1109/tcad.2022.3197501</a>","ieee":"J. Shi, C.-C. von Egidy, K.-H. Chen, and J.-J. Chen, “Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS,” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>, vol. 41, no. 11, pp. 4157–4168, 2022, doi: <a href=\"https://doi.org/10.1109/tcad.2022.3197501\">10.1109/tcad.2022.3197501</a>."}}]