[{"date_updated":"2025-10-30T10:08:55Z","publication_status":"published","intvolume":"        33","year":"2025","title":"Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators","status":"public","publication_identifier":{"issn":["1063-8210","1557-9999"]},"author":[{"first_name":"Muhammad","last_name":"Awais","full_name":"Awais, Muhammad"},{"full_name":"Mohammadi, Hassan Ghasemzadeh","first_name":"Hassan Ghasemzadeh","last_name":"Mohammadi"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"doi":"10.1109/tvlsi.2025.3559377","user_id":"64665","volume":33,"page":"2395-2405","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","_id":"62020","publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issue":"9","citation":{"apa":"Awais, M., Mohammadi, H. G., &#38; Platzner, M. (2025). Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, <i>33</i>(9), 2395–2405. <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">https://doi.org/10.1109/tvlsi.2025.3559377</a>","ieee":"M. Awais, H. G. Mohammadi, and M. Platzner, “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, vol. 33, no. 9, pp. 2395–2405, 2025, doi: <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>.","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i> 33, no. 9 (2025): 2395–2405. <a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">https://doi.org/10.1109/tvlsi.2025.3559377</a>.","short":"M. Awais, H.G. Mohammadi, M. Platzner, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33 (2025) 2395–2405.","mla":"Awais, Muhammad, et al. “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, vol. 33, no. 9, Institute of Electrical and Electronics Engineers (IEEE), 2025, pp. 2395–405, doi:<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>.","ama":"Awais M, Mohammadi HG, Platzner M. Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. 2025;33(9):2395-2405. doi:<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>","bibtex":"@article{Awais_Mohammadi_Platzner_2025, title={Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators}, volume={33}, DOI={<a href=\"https://doi.org/10.1109/tvlsi.2025.3559377\">10.1109/tvlsi.2025.3559377</a>}, number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Awais, Muhammad and Mohammadi, Hassan Ghasemzadeh and Platzner, Marco}, year={2025}, pages={2395–2405} }"},"type":"journal_article","department":[{"_id":"78"}],"date_created":"2025-10-30T10:07:49Z"},{"type":"journal_article","department":[{"_id":"58"}],"date_created":"2025-11-10T08:31:47Z","project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","citation":{"ieee":"B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025, doi: <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","apa":"Sadiye, B., Iftekhar, M., Müller, W., &#38; Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>","short":"B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).","chicago":"Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>.","mla":"Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","bibtex":"@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","ama":"Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>"},"doi":"10.1109/TVLSI.2025.3625787","user_id":"93634","_id":"62148","language":[{"iso":"eng"}],"publisher":"IEEE","date_updated":"2025-11-10T08:38:07Z","publication_status":"published","status":"public","title":"60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design","year":"2025","publication_identifier":{"issn":["1063-8210"]},"author":[{"id":"93634","first_name":"Babak","last_name":"Sadiye","full_name":"Sadiye, Babak"},{"last_name":"Iftekhar","first_name":"Mohammed","full_name":"Iftekhar, Mohammed","id":"47944"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"id":"37144","full_name":"Scheytt, J. Christoph","last_name":"Scheytt","first_name":"J. Christoph","orcid":"0000-0002-5950-6618 "}]},{"publisher":"IEEE","_id":"17358","funded_apc":"1","page":"2084 - 2088","volume":28,"user_id":"49051","status":"public","citation":{"mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>.","apa":"Witschen, L. M., Wiersema, T., &#38; Platzner, M. (2020). Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>, <i>28</i>(9), 2084–2088. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, pp. 2084–2088, 2020.","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i> 28, no. 9 (2020): 2084–88. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>.","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>. 2020;28(9):2084-2088. doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>","short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }"},"project":[{"_id":"12","name":"SFB 901 - Subproject B4"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"1","name":"SFB 901"}],"quality_controlled":"1","language":[{"iso":"eng"}],"doi":"10.1109/TVLSI.2020.3008061","author":[{"id":"49051","last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"issn":["1063-8210"],"eissn":["1557-9999"]},"year":"2020","title":"Proof-carrying Approximate Circuits","intvolume":"        28","article_type":"original","date_updated":"2022-01-06T06:53:09Z","publication_status":"published","date_created":"2020-07-06T11:21:30Z","department":[{"_id":"78"}],"type":"journal_article","keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"publication":"IEEE Transactions On Very Large Scale Integration Systems","issue":"9","abstract":[{"text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.","lang":"eng"}]}]