---
_id: '62020'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
last_name: Awais
- first_name: Hassan Ghasemzadeh
full_name: Mohammadi, Hassan Ghasemzadeh
last_name: Mohammadi
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: Awais M, Mohammadi HG, Platzner M. Design Space Exploration for Approximate
Circuits via Checkpointing and DNN-Based Estimators. IEEE Transactions on Very
Large Scale Integration (VLSI) Systems. 2025;33(9):2395-2405. doi:10.1109/tvlsi.2025.3559377
apa: Awais, M., Mohammadi, H. G., & Platzner, M. (2025). Design Space Exploration
for Approximate Circuits via Checkpointing and DNN-Based Estimators. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, 33(9), 2395–2405. https://doi.org/10.1109/tvlsi.2025.3559377
bibtex: '@article{Awais_Mohammadi_Platzner_2025, title={Design Space Exploration
for Approximate Circuits via Checkpointing and DNN-Based Estimators}, volume={33},
DOI={10.1109/tvlsi.2025.3559377},
number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI)
Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)},
author={Awais, Muhammad and Mohammadi, Hassan Ghasemzadeh and Platzner, Marco},
year={2025}, pages={2395–2405} }'
chicago: 'Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “Design
Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33, no.
9 (2025): 2395–2405. https://doi.org/10.1109/tvlsi.2025.3559377.'
ieee: 'M. Awais, H. G. Mohammadi, and M. Platzner, “Design Space Exploration for
Approximate Circuits via Checkpointing and DNN-Based Estimators,” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 9, pp. 2395–2405,
2025, doi: 10.1109/tvlsi.2025.3559377.'
mla: Awais, Muhammad, et al. “Design Space Exploration for Approximate Circuits
via Checkpointing and DNN-Based Estimators.” IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 33, no. 9, Institute of Electrical
and Electronics Engineers (IEEE), 2025, pp. 2395–405, doi:10.1109/tvlsi.2025.3559377.
short: M. Awais, H.G. Mohammadi, M. Platzner, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems 33 (2025) 2395–2405.
date_created: 2025-10-30T10:07:49Z
date_updated: 2025-10-30T10:08:55Z
department:
- _id: '78'
doi: 10.1109/tvlsi.2025.3559377
intvolume: ' 33'
issue: '9'
page: 2395-2405
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
publication_identifier:
issn:
- 1063-8210
- 1557-9999
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based
Estimators
type: journal_article
user_id: '64665'
volume: 33
year: '2025'
...
---
_id: '62148'
author:
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm
FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Published
online 2025. doi:10.1109/TVLSI.2025.3625787'
apa: 'Sadiye, B., Iftekhar, M., Müller, W., & Scheytt, J. C. (2025). 60-Gb/s
1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems. https://doi.org/10.1109/TVLSI.2025.3625787'
bibtex: '@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design}, DOI={10.1109/TVLSI.2025.3625787},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE},
author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2025} }'
chicago: 'Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt.
“60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 2025. https://doi.org/10.1109/TVLSI.2025.3625787.'
ieee: 'B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2025, doi: 10.1109/TVLSI.2025.3625787.'
mla: 'Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology
Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, IEEE, 2025, doi:10.1109/TVLSI.2025.3625787.'
short: B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems (2025).
date_created: 2025-11-10T08:31:47Z
date_updated: 2025-11-10T08:38:07Z
department:
- _id: '58'
doi: 10.1109/TVLSI.2025.3625787
language:
- iso: eng
project:
- _id: '325'
name: 'Scale4Edge: Skalierbare Infrastruktur für Edge-Computing'
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
publication_identifier:
issn:
- 1063-8210
publication_status: published
publisher: IEEE
status: public
title: '60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design'
type: journal_article
user_id: '93634'
year: '2025'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...