[{"citation":{"chicago":"Hakert, Christian, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, and Jian-Jia Chen. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i> 72, no. 5 (2022): 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>.","short":"C. Hakert, A.A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, J.-J. Chen, IEEE Transactions on Computers 72 (2022) 1488–1502.","ieee":"C. Hakert, A. A. Khan, K.-H. Chen, F. Hameed, J. Castrillon, and J.-J. Chen, “ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees,” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, pp. 1488–1502, 2022, doi: <a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>.","apa":"Hakert, C., Khan, A. A., Chen, K.-H., Hameed, F., Castrillon, J., &#38; Chen, J.-J. (2022). ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>, <i>72</i>(5), 1488–1502. <a href=\"https://doi.org/10.1109/tc.2022.3197094\">https://doi.org/10.1109/tc.2022.3197094</a>","bibtex":"@article{Hakert_Khan_Chen_Hameed_Castrillon_Chen_2022, title={ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees}, volume={72}, DOI={<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>}, number={5}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hakert, Christian and Khan, Asif Ali and Chen, Kuan-Hsun and Hameed, Fazal and Castrillon, Jeronimo and Chen, Jian-Jia}, year={2022}, pages={1488–1502} }","ama":"Hakert C, Khan AA, Chen K-H, Hameed F, Castrillon J, Chen J-J. ROLLED: &#60;u&#62;R&#60;/u&#62;acetrack Memory &#60;u&#62;O&#60;/u&#62;ptimized &#60;u&#62;L&#60;/u&#62;inear &#60;u&#62;L&#60;/u&#62;ayout and &#60;u&#62;E&#60;/u&#62;fficient &#60;u&#62;D&#60;/u&#62;ecomposition of Decision Trees. <i>IEEE Transactions on Computers</i>. 2022;72(5):1488-1502. doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>","mla":"Hakert, Christian, et al. “ROLLED: &#60;u&#62;R&#60;/U&#62;acetrack Memory &#60;u&#62;O&#60;/U&#62;ptimized &#60;u&#62;L&#60;/U&#62;inear &#60;u&#62;L&#60;/U&#62;ayout and &#60;u&#62;E&#60;/U&#62;fficient &#60;u&#62;D&#60;/U&#62;ecomposition of Decision Trees.” <i>IEEE Transactions on Computers</i>, vol. 72, no. 5, Institute of Electrical and Electronics Engineers (IEEE), 2022, pp. 1488–502, doi:<a href=\"https://doi.org/10.1109/tc.2022.3197094\">10.1109/tc.2022.3197094</a>."},"issue":"5","publication":"IEEE Transactions on Computers","type":"journal_article","date_created":"2026-07-03T21:13:39Z","intvolume":"        72","date_updated":"2026-10-12T20:28:35Z","publication_status":"published","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"author":[{"first_name":"Christian","last_name":"Hakert","full_name":"Hakert, Christian"},{"first_name":"Asif Ali","last_name":"Khan","full_name":"Khan, Asif Ali"},{"id":"128464","full_name":"Chen, Kuan-Hsun","last_name":"Chen","first_name":"Kuan-Hsun","orcid":"0000-0002-7110-921X"},{"last_name":"Hameed","first_name":"Fazal","full_name":"Hameed, Fazal"},{"full_name":"Castrillon, Jeronimo","first_name":"Jeronimo","last_name":"Castrillon"},{"last_name":"Chen","first_name":"Jian-Jia","full_name":"Chen, Jian-Jia"}],"status":"public","year":"2022","title":"ROLLED: <u>R</u>acetrack Memory <u>O</u>ptimized <u>L</u>inear <u>L</u>ayout and <u>E</u>fficient <u>D</u>ecomposition of Decision Trees","volume":72,"doi":"10.1109/tc.2022.3197094","user_id":"128464","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","_id":"66180","language":[{"iso":"eng"}],"page":"1488-1502"},{"page":"1-1","_id":"30907","language":[{"iso":"eng"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","doi":"10.1109/tc.2021.3107196","user_id":"398","status":"public","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs","year":"2021","author":[{"first_name":"Alfonso","last_name":"Rodriguez","full_name":"Rodriguez, Alfonso"},{"first_name":"Andres","last_name":"Otero","full_name":"Otero, Andres"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"last_name":"De la Torre","first_name":"Eduardo","full_name":"De la Torre, Eduardo"}],"publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"date_updated":"2022-04-18T10:04:21Z","publication_status":"published","date_created":"2022-04-18T10:03:16Z","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"type":"journal_article","department":[{"_id":"78"}],"publication":"IEEE Transactions on Computers","citation":{"chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }","ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>."}},{"citation":{"mla":"Yayla, Mikail, et al. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1681–95, doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>.","bibtex":"@article{Yayla_Buschjager_Gupta_Chen_Henkel_Morik_Chen_Amrouch_2021, title={FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors}, volume={71}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>}, number={7}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Yayla, Mikail and Buschjager, Sebastian and Gupta, Aniket and Chen, Jian-Jia and Henkel, Jorg and Morik, Katharina and Chen, Kuan-Hsun and Amrouch, Hussam}, year={2021}, pages={1681–1695} }","ama":"Yayla M, Buschjager S, Gupta A, et al. FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>. 2021;71(7):1681-1695. doi:<a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>","ieee":"M. Yayla <i>et al.</i>, “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors,” <i>IEEE Transactions on Computers</i>, vol. 71, no. 7, pp. 1681–1695, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3104736\">10.1109/tc.2021.3104736</a>.","apa":"Yayla, M., Buschjager, S., Gupta, A., Chen, J.-J., Henkel, J., Morik, K., Chen, K.-H., &#38; Amrouch, H. (2021). FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors. <i>IEEE Transactions on Computers</i>, <i>71</i>(7), 1681–1695. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>","short":"M. Yayla, S. Buschjager, A. Gupta, J.-J. Chen, J. Henkel, K. Morik, K.-H. Chen, H. Amrouch, IEEE Transactions on Computers 71 (2021) 1681–1695.","chicago":"Yayla, Mikail, Sebastian Buschjager, Aniket Gupta, Jian-Jia Chen, Jorg Henkel, Katharina Morik, Kuan-Hsun Chen, and Hussam Amrouch. “FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors.” <i>IEEE Transactions on Computers</i> 71, no. 7 (2021): 1681–95. <a href=\"https://doi.org/10.1109/tc.2021.3104736\">https://doi.org/10.1109/tc.2021.3104736</a>."},"publication":"IEEE Transactions on Computers","issue":"7","type":"journal_article","date_created":"2026-07-03T21:17:12Z","intvolume":"        71","publication_status":"published","date_updated":"2026-10-12T20:29:03Z","author":[{"first_name":"Mikail","last_name":"Yayla","full_name":"Yayla, Mikail"},{"full_name":"Buschjager, Sebastian","last_name":"Buschjager","first_name":"Sebastian"},{"full_name":"Gupta, Aniket","first_name":"Aniket","last_name":"Gupta"},{"first_name":"Jian-Jia","last_name":"Chen","full_name":"Chen, Jian-Jia"},{"full_name":"Henkel, Jorg","first_name":"Jorg","last_name":"Henkel"},{"last_name":"Morik","first_name":"Katharina","full_name":"Morik, Katharina"},{"orcid":"0000-0002-7110-921X","last_name":"Chen","first_name":"Kuan-Hsun","full_name":"Chen, Kuan-Hsun","id":"128464"},{"full_name":"Amrouch, Hussam","last_name":"Amrouch","first_name":"Hussam"}],"publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"title":"FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors","year":"2021","status":"public","volume":71,"user_id":"128464","doi":"10.1109/tc.2021.3104736","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","_id":"66200","language":[{"iso":"eng"}],"page":"1681-1695"}]
