[{"publication":"The Journal of Supercomputing","issue":"6","abstract":[{"lang":"eng","text":"SYCL is an open standard for targeting heterogeneous hardware from C++. In this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization uses polynomial orders zero to two on unstructured triangular meshes. Separating memory accesses from the numerical code allow us to optimize data accesses for the target architecture. A performance analysis shows good portability across x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up to 10x higher energy efficiency in terms of degrees of freedom per joule compared to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the other architectures with particularly good computational performance on smaller meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues and have similar energy efficiency as latest generation CPUs."}],"date_created":"2025-11-04T09:37:50Z","department":[{"_id":"27"},{"_id":"518"}],"type":"journal_article","publication_identifier":{"issn":["1573-0484"]},"author":[{"last_name":"Büttner","first_name":"Markus","full_name":"Büttner, Markus"},{"id":"100625","full_name":"Alt, Christoph","first_name":"Christoph","last_name":"Alt"},{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"full_name":"Köstler, Harald","first_name":"Harald","last_name":"Köstler"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"},{"first_name":"Vadym","last_name":"Aizinger","full_name":"Aizinger, Vadym"}],"year":"2025","title":"Analyzing performance portability for a SYCL implementation of the 2D shallow water equations","intvolume":"        81","publication_status":"published","date_updated":"2025-11-04T09:48:10Z","language":[{"iso":"eng"}],"article_number":"772","main_file_link":[{"open_access":"1"}],"doi":"10.1007/s11227-025-07063-7","citation":{"apa":"Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., &#38; Aizinger, V. (2025). Analyzing performance portability for a SYCL implementation of the 2D shallow water equations. <i>The Journal of Supercomputing</i>, <i>81</i>(6), Article 772. <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">https://doi.org/10.1007/s11227-025-07063-7</a>","ieee":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Analyzing performance portability for a SYCL implementation of the 2D shallow water equations,” <i>The Journal of Supercomputing</i>, vol. 81, no. 6, Art. no. 772, 2025, doi: <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>.","short":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, The Journal of Supercomputing 81 (2025).","chicago":"Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian Plessl, and Vadym Aizinger. “Analyzing Performance Portability for a SYCL Implementation of the 2D Shallow Water Equations.” <i>The Journal of Supercomputing</i> 81, no. 6 (2025). <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">https://doi.org/10.1007/s11227-025-07063-7</a>.","mla":"Büttner, Markus, et al. “Analyzing Performance Portability for a SYCL Implementation of the 2D Shallow Water Equations.” <i>The Journal of Supercomputing</i>, vol. 81, no. 6, 772, Springer Science and Business Media LLC, 2025, doi:<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>.","ama":"Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Analyzing performance portability for a SYCL implementation of the 2D shallow water equations. <i>The Journal of Supercomputing</i>. 2025;81(6). doi:<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>","bibtex":"@article{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2025, title={Analyzing performance portability for a SYCL implementation of the 2D shallow water equations}, volume={81}, DOI={<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>}, number={6772}, journal={The Journal of Supercomputing}, publisher={Springer Science and Business Media LLC}, author={Büttner, Markus and Alt, Christoph and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym}, year={2025} }"},"quality_controlled":"1","oa":"1","status":"public","_id":"62064","publisher":"Springer Science and Business Media LLC","volume":81,"user_id":"3145"},{"citation":{"apa":"Rodríguez, A., Navarro, A., Asenjo, R., Corbera, F., Gran, R., Suárez, D., &#38; Nunez-Yanez, J. (2019). Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>","ieee":"A. Rodríguez <i>et al.</i>, “Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform,” <i>The Journal of Supercomputing</i>, 2019.","short":"A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, The Journal of Supercomputing (2019).","chicago":"Rodríguez, Andrés, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Rubén Gran, Darío Suárez, and Jose Nunez-Yanez. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>.","mla":"Rodríguez, Andrés, et al. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019, doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>.","ama":"Rodríguez A, Navarro A, Asenjo R, et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. 2019. doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>","bibtex":"@article{Rodríguez_Navarro_Asenjo_Corbera_Gran_Suárez_Nunez-Yanez_2019, title={Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform}, DOI={<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>}, journal={The Journal of Supercomputing}, author={Rodríguez, Andrés and Navarro, Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez, Darío and Nunez-Yanez, Jose}, year={2019} }"},"publication":"The Journal of Supercomputing","abstract":[{"text":"Heterogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively.","lang":"eng"}],"date_created":"2020-04-06T12:09:25Z","type":"journal_article","keyword":["pc2-harp-ressources"],"author":[{"last_name":"Rodríguez","first_name":"Andrés","full_name":"Rodríguez, Andrés"},{"full_name":"Navarro, Angeles","last_name":"Navarro","first_name":"Angeles"},{"first_name":"Rafael","last_name":"Asenjo","full_name":"Asenjo, Rafael"},{"first_name":"Francisco","last_name":"Corbera","full_name":"Corbera, Francisco"},{"full_name":"Gran, Rubén","first_name":"Rubén","last_name":"Gran"},{"full_name":"Suárez, Darío","last_name":"Suárez","first_name":"Darío"},{"first_name":"Jose","last_name":"Nunez-Yanez","full_name":"Nunez-Yanez, Jose"}],"publication_identifier":{"issn":["0920-8542","1573-0484"]},"year":"2019","title":"Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform","status":"public","publication_status":"published","date_updated":"2022-01-06T06:52:50Z","language":[{"iso":"eng"}],"_id":"16423","user_id":"61189","doi":"10.1007/s11227-019-02935-1"}]