---
_id: '56604'
abstract:
- lang: eng
text: This manuscript makes the claim of having computed the 9th Dedekind number,
D(9). This was done by accelerating the core operation of the process with an
efficient FPGA design that outperforms an optimized 64-core CPU reference by 95x.
The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn
University. The resulting value for D(9) is 286386577668298411128469151667598498812366.
This value can be verified in two steps. We have made the data file containing
the 490 M results available, each of which can be verified separately on CPU,
and the whole file sums to our proposed value. The paper explains the mathematical
approach in the first part, before putting the focus on a deep dive into the FPGA
accelerator implementation followed by a performance analysis. The FPGA implementation
was done in Register-Transfer Level using a dual-clock architecture and shows
how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800
FPGAs. The total compute time used was 47,000 FPGA hours.
author:
- first_name: Lennart
full_name: Van Hirtum, Lennart
id: '100210'
last_name: Van Hirtum
- first_name: Patrick
full_name: De Causmaecker, Patrick
last_name: De Causmaecker
- first_name: Jens
full_name: Goemaere, Jens
last_name: Goemaere
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable
Technology and Systems. 2024;17(3):1-28. doi:10.1145/3674147
apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H.,
Lass, M., & Plessl, C. (2024). A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and
Systems, 17(3), 1–28. https://doi.org/10.1145/3674147
bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2024,
title={A Computation of the Ninth Dedekind Number Using FPGA Supercomputing},
volume={17}, DOI={10.1145/3674147},
number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems},
publisher={Association for Computing Machinery (ACM)}, author={Van Hirtum, Lennart
and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler,
Heinrich and Lass, Michael and Plessl, Christian}, year={2024}, pages={1–28} }'
chicago: 'Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter,
Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable
Technology and Systems 17, no. 3 (2024): 1–28. https://doi.org/10.1145/3674147.'
ieee: 'L. Van Hirtum et al., “A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing,” ACM Transactions on Reconfigurable Technology and
Systems, vol. 17, no. 3, pp. 1–28, 2024, doi: 10.1145/3674147.'
mla: Van Hirtum, Lennart, et al. “A Computation of the Ninth Dedekind Number Using
FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems,
vol. 17, no. 3, Association for Computing Machinery (ACM), 2024, pp. 1–28, doi:10.1145/3674147.
short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M.
Lass, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17
(2024) 1–28.
date_created: 2024-10-14T07:38:29Z
date_updated: 2025-11-04T09:53:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3674147
intvolume: ' 17'
issue: '3'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 1-28
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: A Computation of the Ninth Dedekind Number Using FPGA Supercomputing
type: journal_article
user_id: '3145'
volume: 17
year: '2024'
...
---
_id: '38041'
abstract:
- lang: eng
text: "While FPGA accelerator boards and their respective high-level design
tools are maturing, there is still a lack of multi-FPGA applications, libraries,
and not least, benchmarks and reference implementations towards sustained HPC
usage of these devices. As in the early days of GPUs in HPC, for workloads that
can reasonably be decoupled into loosely coupled working sets, multi-accelerator
support can be achieved by using standard communication interfaces like MPI on
the host side. However, for performance and productivity, some applications can
profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities
here when extending the dataflow characteristics to their communication interfaces.\r\n
\ In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA
support and three missing benchmarks that particularly characterize or stress
inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented
for current boards with Intel and Xilinx FPGAs, we established a baseline for
multi-FPGA performance. Additionally, for the communication-centric benchmarks,
we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched
inter-FPGA network that is currently only available for one of the boards. The
evaluation with parallel execution on up to 26 FPGA boards makes use of one of
the largest academic FPGA installations."
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge
Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions
on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200
apa: Meyer, M., Kenter, T., & Plessl, C. (2023). Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.
ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3576200
bibtex: '@article{Meyer_Kenter_Plessl_2023, title={Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks},
DOI={10.1145/3576200}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, publisher={Association
for Computing Machinery (ACM)}, author={Meyer, Marius and Kenter, Tobias and Plessl,
Christian}, year={2023} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Multi-FPGA Designs
and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA
Networks.” ACM Transactions on Reconfigurable Technology and Systems, 2023.
https://doi.org/10.1145/3576200.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Multi-FPGA Designs and Scaling of HPC
Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks,” ACM
Transactions on Reconfigurable Technology and Systems, 2023, doi: 10.1145/3576200.'
mla: Meyer, Marius, et al. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks
via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable
Technology and Systems, Association for Computing Machinery (ACM), 2023, doi:10.1145/3576200.
short: M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology
and Systems (2023).
date_created: 2023-01-23T08:40:42Z
date_updated: 2023-07-28T08:02:05Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3576200
keyword:
- General Computer Science
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://dl.acm.org/doi/10.1145/3576200
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched
Inter-FPGA Networks
type: journal_article
user_id: '24135'
year: '2023'
...
---
_id: '28099'
abstract:
- lang: eng
text: N-body methods are one of the essential algorithmic building blocks of high-performance
and parallel computing. Previous research has shown promising performance for
implementing n-body simulations with pairwise force calculations on FPGAs. However,
to avoid challenges with accumulation and memory access patterns, the presented
designs calculate each pair of forces twice, along with both force sums of the
involved particles. Also, they require large problem instances with hundreds of
thousands of particles to reach their respective peak performance, limiting the
applicability for strong scaling scenarios. This work addresses both issues by
presenting a novel FPGA design that uses each calculated force twice and overlaps
data transfers and computations in a way that allows to reach peak performance
even for small problem instances, outperforming previous single precision results
even in double precision, and scaling linearly over multiple interconnected FPGAs.
For a comparison across architectures, we provide an equally optimized CPU reference,
which for large problems actually achieves higher peak performance per device,
however, given the strong scaling advantages of the FPGA design, in parallel setups
with few thousand particles per device, the FPGA platform achieves highest performance
and power efficiency.
article_type: original
author:
- first_name: Johannes
full_name: Menzel, Johannes
last_name: Menzel
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: Menzel J, Plessl C, Kenter T. The Strong Scaling Advantage of FPGAs in HPC
for N-body Simulations. ACM Transactions on Reconfigurable Technology and Systems.
2021;15(1):1-30. doi:10.1145/3491235
apa: Menzel, J., Plessl, C., & Kenter, T. (2021). The Strong Scaling Advantage
of FPGAs in HPC for N-body Simulations. ACM Transactions on Reconfigurable
Technology and Systems, 15(1), 1–30. https://doi.org/10.1145/3491235
bibtex: '@article{Menzel_Plessl_Kenter_2021, title={The Strong Scaling Advantage
of FPGAs in HPC for N-body Simulations}, volume={15}, DOI={10.1145/3491235},
number={1}, journal={ACM Transactions on Reconfigurable Technology and Systems},
author={Menzel, Johannes and Plessl, Christian and Kenter, Tobias}, year={2021},
pages={1–30} }'
chicago: 'Menzel, Johannes, Christian Plessl, and Tobias Kenter. “The Strong Scaling
Advantage of FPGAs in HPC for N-Body Simulations.” ACM Transactions on Reconfigurable
Technology and Systems 15, no. 1 (2021): 1–30. https://doi.org/10.1145/3491235.'
ieee: 'J. Menzel, C. Plessl, and T. Kenter, “The Strong Scaling Advantage of FPGAs
in HPC for N-body Simulations,” ACM Transactions on Reconfigurable Technology
and Systems, vol. 15, no. 1, pp. 1–30, 2021, doi: 10.1145/3491235.'
mla: Menzel, Johannes, et al. “The Strong Scaling Advantage of FPGAs in HPC for
N-Body Simulations.” ACM Transactions on Reconfigurable Technology and Systems,
vol. 15, no. 1, 2021, pp. 1–30, doi:10.1145/3491235.
short: J. Menzel, C. Plessl, T. Kenter, ACM Transactions on Reconfigurable Technology
and Systems 15 (2021) 1–30.
date_created: 2021-11-30T10:00:31Z
date_updated: 2022-01-06T06:57:51Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3491235
intvolume: ' 15'
issue: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://dl.acm.org/doi/10.1145/3491235
oa: '1'
page: 1-30
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
quality_controlled: '1'
status: public
title: The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations
type: journal_article
user_id: '3145'
volume: 15
year: '2021'
...
---
_id: '29150'
abstract:
- lang: eng
text: Robotics applications process large amounts of data in real time and require
compute platforms that provide high performance and energy efficiency. FPGAs are
well suited for many of these applications, but there is a reluctance in the robotics
community to use hardware acceleration due to increased design complexity and
a lack of consistent programming models across the software/hardware boundary.
In this article, we present ReconROS, a framework that integrates the widely used
robot operating system (ROS) with ReconOS, which features multithreaded programming
of hardware and software threads for reconfigurable computers. This unique combination
gives ROS 2 developers the flexibility to transparently accelerate parts of their
robotics applications in hardware. We elaborate on the architecture and the design
flow for ReconROS and report on a set of experiments that underline the feasibility
and flexibility of our approach.
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems
with ReconROS. ACM Transactions on Reconfigurable Technology and Systems.
Published online 2021:1-20. doi:10.1145/3494571
apa: Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable
Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology
and Systems, 1–20. https://doi.org/10.1145/3494571
bibtex: '@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable
Robotics Systems with ReconROS}, DOI={10.1145/3494571},
journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen,
Christian and Platzner, Marco}, year={2021}, pages={1–20} }'
chicago: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, 1–20. https://doi.org/10.1145/3494571.
ieee: 'C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics
Systems with ReconROS,” ACM Transactions on Reconfigurable Technology and Systems,
pp. 1–20, 2021, doi: 10.1145/3494571.'
mla: Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable
Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology
and Systems, 2021, pp. 1–20, doi:10.1145/3494571.
short: C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and
Systems (2021) 1–20.
date_created: 2022-01-04T08:30:10Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
doi: 10.1145/3494571
language:
- iso: eng
page: 1-20
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
status: public
title: Design of Distributed Reconfigurable Robotics Systems with ReconROS
type: journal_article
user_id: '60323'
year: '2021'
...