@article{20,
  abstract     = {{Approximate computing has shown to provide new ways to improve performance
and power consumption of error-resilient applications. While many of these
applications can be found in image processing, data classification or machine
learning, we demonstrate its suitability to a problem from scientific
computing. Utilizing the self-correcting behavior of iterative algorithms, we
show that approximate computing can be applied to the calculation of inverse
matrix p-th roots which are required in many applications in scientific
computing. Results show great opportunities to reduce the computational effort
and bandwidth required for the execution of the discussed algorithm, especially
when targeting special accelerator hardware.}},
  author       = {{Lass, Michael and Kühne, Thomas and Plessl, Christian}},
  issn         = {{1943-0671}},
  journal      = {{Embedded Systems Letters}},
  number       = {{2}},
  pages        = {{ 33--36}},
  publisher    = {{IEEE}},
  title        = {{{Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}}},
  doi          = {{10.1109/LES.2017.2760923}},
  volume       = {{10}},
  year         = {{2018}},
}

@article{1043,
  abstract     = {{Approximate computing (AC) is an emerging paradigm for energy-efficient computation. The basic idea of AC is to sacrifice high precision for low energy by allowing hardware to carry out “approximately correct” calculations. This provides a major challenge for software quality assurance: programs successfully verified to be correct might be erroneous on approximate hardware. In this letter, we present a novel approach for determining under what conditions a software verification result is valid for approximate hardware. To this end, we compute the allowed tolerances for AC hardware from successful verification runs. More precisely, we derive a set of constraints which—when met by the AC hardware—guarantees the verification result to carry over to AC. On the practical side, we furthermore: 1) show how to extract tolerances from verification runs employing predicate abstraction as verification technology and 2) show how to check such constraints on hardware designs. We have implemented all techniques, and exemplify them on example C programs and a number of recently proposed approximate adders.}},
  author       = {{Isenberg, Tobias and Jakobs, Marie-Christine and Pauck, Felix and Wehrheim, Heike}},
  issn         = {{1943-0663}},
  journal      = {{IEEE Embedded Systems Letters}},
  pages        = {{22--25}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Validity of Software Verification Results on Approximate Hardware}}},
  doi          = {{10.1109/LES.2017.2758200}},
  year         = {{2018}},
}