@article{46264,
  abstract     = {{System-level interconnects provide the
backbone for increasingly complex systems on a chip. Their
vulnerability to electromigration and crosstalk can lead to
serious reliability and safety issues during the system lifetime.
This article presents an approach for periodic in-system testing
which maintains a reliability profile to detect potential
problems before they actually cause a failure. Relying on a
common infrastructure for EM-aware system workload
management and test, it minimizes the stress induced by the
test itself and contributes to the self-healing of system-induced
electromigration degradations. }},
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  issn         = {{2168-2356}},
  journal      = {{IEEE Design &Test}},
  keywords     = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}},
  pages        = {{1--1}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Workload-Aware Periodic Interconnect BIST}}},
  doi          = {{10.1109/mdat.2023.3298849}},
  year         = {{2023}},
}