[{"year":"2023","page":"1-1","citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>}, journal={IEEE Design &#38;Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &#38;Test (2023) 1–1.","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, 2023, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” <i>IEEE Design &#38;Test</i>, pp. 1–1, 2023, doi: <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>. Published online 2023:1-1. doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>"},"publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published","title":"Workload-Aware Periodic Interconnect BIST","doi":"10.1109/mdat.2023.3298849","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2024-03-22T17:15:10Z","author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_created":"2023-08-02T11:07:43Z","abstract":[{"text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. ","lang":"eng"}],"status":"public","publication":"IEEE Design &Test","type":"journal_article","keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"article_type":"original","language":[{"iso":"eng"}],"_id":"46264","department":[{"_id":"48"}],"user_id":"209"}]